Analog Integr Circ Sig Process DOI 10.1007/s10470-016-0916-9

A new CMOS comparator robust to process and temperature variations for SAR ADC converters Gisela de La Fuente-Cortes1 • Guillermo Espinosa Flores-Verdad1 Victor R. Gonzalez-Diaz2 • A. Diaz-Mendez1

•

Received: 22 September 2016 / Accepted: 19 December 2016 Ó Springer Science+Business Media New York 2017

Abstract This paper presents a novel comparator being robust to temperature and process variations. The new comparator is confronted to a conventional topology used in most of the Successive Approximations Analog to Digital Converters (SAR ADCs) for biomedical applications. To verify the benefits of the new comparator, it was designed on a CMOS 65 nm process and characterized with post layout simulations under conditions of process and temperature fluctuations. With the proposed circuit, a SAR ADC exhibits 83.11 dB of Signal to Noise Ratio at 1.28 MS/s and 375 lW of power consumption. The PT variations for critical corners are less than 0.58 bits. Keywords Analog comparator  ADC SAR  Process and temperature variations  Robust design

1 Introduction Recently, health care improvement brings a growing demand for portable biopotential acquisition systems. Some of the principal blocks for these systems can be fully & Gisela de La Fuente-Cortes [email protected] Guillermo Espinosa Flores-Verdad [email protected] Victor R. Gonzalez-Diaz [email protected] A. Diaz-Mendez [email protected] 1

National Institute for Astrophysics, Optics and Electronics, Calle Luis Enrique Erro No. 1 Tonantzintla, Puebla, Mexico

2

Facultad de Ciencias de la Electro´nica, Beneme´rita Universidad Auto´noma de Puebla, Av. San Claudio y 18 Sur, Col. Jardines de San Manuel, Puebla, Mexico

integrated [1]. Normally these medical devices are monitored or controlled by a wireless system and the sensed biomedical signals are converted to the digital domain before transmitted. Therefore, the Analog to Digital Converter (ADC) is a key element for the overall integrated circuit performance. As biomedical signals range in a low frequency bandwidth, the Successive Approximation Register (SAR) ADC is suitable for these applications [2]. This is as it offers the combination of high accuracy and moderate conversion speed thanks to a simple structure [3, 4]. The main advantage of a SAR–ADC is the simple trial and error technique with a feedback loop to approximate the analog signal with a corresponding digital word. Being for medical applications, these systems must warrantee reliability by means of a robust integrated circuit design [5]. The robustness to process, temperature and voltage variations help to preserve a high signal resolution in spite of adverse conditions. A critical component in the SAR–ADC system is the voltage comparator, which takes the decision in the successive approximation algorithm. This paper resumes the impact of process and temperature (PT) variations on the voltage comparator in a conventional SAR–ADC structure. The analysis shows that even with a careful design, a conventional comparator is not reliable to PT variations. This work proposes a new robust comparator topology improving the overall SAR–ADC performance subjugated to PT variations. The new circuit is based on a symmetrical topology that improves in general the circuit response. The paper is organized as follows. Section 2 resumes the PT variations impact of a conventional comparator for the SAR–ADC resolution. Section 3 describes the proposed comparator and shows its performance compared to the conventional results. Section 4 shows the transistor level simulations of a SAR ADC to evaluate the proposed circuit

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and compares the PV variations with similar topologies. Finally Sect. 5 concludes the paper.

2 The SAR ADC performance to PT variations

Let us focus on the voltage comparator of Fig. 1, which is commonly used in the aforementioned SAR ADCs topologies [6–8]. This high resolution comparator exhibits a multistage configuration where each stage uses one low gain amplifier (PAi). For the mentioned comparator, the output offset storage (OOS) scheme reduces the voltage offset impact [9]. The offset is canceled by shorting the preamplifier inputs and storing the amplifier’s offset into the output coupling capacitors, see Fig. 1. To design the comparator, the number of amplifier stages (n) and the amplifier’s DC gain (AvPA ) is selected with Eqs. (1), where VosL represents the latch offset and LSB is the quantization step [10]. VosL \0:5  LSB ðAvPA Þn

ð1Þ

The comparator’s requirements are obtained from the data converter specs and Eqs. (1). For the present application, the signal’s bandwidth upper limit is considered as 20 kHz. The selected SAR is an oversampling topology which uses 16 cycles to execute a conversion. With and OSR of 32, the comparator clock frequency is Fclk ¼ 20:48 MHz. The comparator and latch circuits are dimentioned to reach a time step response below half of this period (24 ns). In addition, the optimal gain calculated for the pre-amplifier circuit is 24 dB and the gain bandwidth product is GBWPA ¼ 20:48 MHz. With the previous parameters, the maximum allowable latch offset is VosL \179 mV and the preamplifiers offset is limited to

Fig. 1 Conventional multistage comparator used in the SAR–ADC’s

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Table 1 Comparator specs to fulfill the explored SAR ADC performance Power supply

1.2 V

Pre-amp stages

3

AVPA

24 dB

GBWPA

20 MHz

VosPA

10 mV

VosL

\179 mV

Step response Dyn. range

\24 ns 1.2 V

Sensitivity OSR

36:62 lV 32

VosPA \  10 mV. Table 1 resumes the comparator specs to fulfill the previous SAR ADC requirements. To explore the comparator’s performance, the preamplifier and latch stages were designed and simulated under PT variations in a 65 nm CMOS process. The temperature range is considered from 40, 60 and 120  C with corner cases available in the design kit: typical typical (TT), Fast Fast (FF), Slow Slow (SS), Fast Slow (FS) and Slow Fast (SF) for NMOS and PMOS respectively. This gives rise to 15 corner cases which were run in Spectre. A step input applied to the comparator has an amplitude of 36:62 lV which is the limit for voltage sensitivity. Figure 2 shows the comparator’s step response for the typical corner case (TT @ 60  C) and PT variations. Most of the corner cases present a time response in the limit allowed. However, the resulting amplitude outputs below 0:95 V threat the next block in the SAR–ADC. Note the comparator’s speed not only depends on the time response but also depends on the OOS technique. In this topology there is a trade off between delay and latch offset voltage. Similarly, Fig. 3 shows the DC response for the preamplifier. The response for TT @ 40, 60 and 120  C corners remain in the allowable ranges. The corners with fast mobility in PMOS transistors (FS) exhibit important variations around þ45:5 mV. The corners with slow mobility for PMOS transistors (SS, ST) show a variation of 28:8 mV, both rising above the allowed 10 mV. These results show that the reliable function of the OOS technique in the preamplifier stage is threatened. For the latch stage case in Fig. 4, the offset voltage variations reach values up to 201:2 mV. In this case the most critical corners are the SS @ 40, 60 and 120  C, exceeding the specified value for more than 50 mV. In accordance with (1), the number of pre-amplifiers and DC gain must increase as offset increases. For corners where the latch offset exceeds 179 mV, the necessary DC gain is not easily achievable with the number of preamplifiers and the comparator misses the estimation as, the DAC processes small values. As a matter of fact, the systematic offset variations for the preamplifier and Latch stages are caused by the output currents mismatch in the output transistors. As a preliminary conclusion, this architecture is not robust enough to PT variations, with a negative impact to the SAR ADC ENOB.

Analog Integr Circ Sig Process

3 The proposed comparator robust to PT variations

Fig. 2 Step response for the pre-amplifier and Latch for 15 corner cases

Fig. 3 DC PT variations for the preamplifier stage

The proposed comparator uses symmetrical differential pairs with NMOS and PMOS transistors to compensate for the output currents mismatch. This topology limits variations in the Latch comparator output and improves the overall performance under PT variations. Figure 5 shows the schematic along with the timing scheme, which is based in a structure presented in [10]. The improved latch scheme makes the SAR–ADC comparator to need only one preamplifier stage, note the difference between the schematics in Figs. 5 and 1. For the proposed comparator the Latch stage is a bistable multivibrator. Transistors M1 to M14 work as a preamplifier stage and transitors M15 to M20 compose the bistable multivibrator. The circuit works as follows: when /1 ; /2 and /3 are high, the preamplifier is selfbiased and C1 and C2 are precharged to ðVin  VA Þ and ðVinþ  VB Þ, respectively. In this stage, nodes VA y VB are equivalent to the offset voltage of the preamplifier VosPA , the switch SR keeps the same voltage level in VA and VB . Subsequently, a low value in /1 enables the preamplifier circuit, leaving VA and VB as floating nodes. Immediately /3 is high and the lower capacitor plates are connected to Vinþ and Vin respectively. This causes a difference of potential between the nodes Vout and Voutþ and the offset voltage is cancelled. At this point, phases /2 and /2 smoothly change. This causes the multivibrator to set to one stable state. The selected state is determined by the difference of ðVout  Voutþ Þ. The comparator design starts from the Latch. It must drive the output current with the necessary speed for the SAR–ADC. The proposed comparator uses the input offset storage technique and the number of preamplifier stages is only one. With these changes, the preamplifier’s gain is calculated by Eq. (1) with two important modifications: n ¼ 1 and the offset is calculated by the expression: VosL \AvPA LSB

Fig. 4 DC PT variations latch stage

ð2Þ

In addition, the preamplifier’s gain is a function of the Latch’s intrinsic offset. Therefore, to obtain the best preamplifier’s gain it is necesary a recursive process. The circuit is simulated with an expected preamplifier’s gain and by measuring the Latch’s intrinsic offset it is possible to obtain a more approximated value for the preamplifier’s gain. For instance, by expecting AvPA ¼ 25 dB, the complete circuit is designed and the intrinsic offset is measured by the difference of the complete comparator’s offset when is enabled and disabled by the crossing point of /2 and /2 respectively. For the actual design case, the resulting intrinsic offset is ðVosLON  VosLOFF Þ ¼ ð95  94:1Þ mV, which results in VosL ¼ 0:9 mV. By knowing the intrinsic

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Fig. 5 Topology of the proposed comparator and the timing scheme (Vb2 and Vb1 are the bias voltages) Table 2 Proposed comparator specs to fulfill the ADC performance in biomedical applications Power supply

1.2 V

Pre amplifier stages

1

AvPA

[22 dB

GBWPA

20 MHz

VosPA

±70 mV

VosL

1 mV

Step response

\24 ns

Sensitivity Dynamic output range

36.62 lV 1.2 V

latch offset the optimal preamplifier’s gain can be found by the recursive equation (AvPA ½j ¼ VosL ½j  1 =LSB) the result is AvPA ¼ 21:8 dB (Table 2). The comparator circuit of Fig. 5 was designed in the same 65 nm CMOS process and the layout is shown in Fig. 6. The transistors are disposed with the same orientation and the circuit is symmetrical, which is a clear advantage. The traditional (not symmetrical comparators) will not fulfill this requirement. Figure 7 shows the post layout simulation when preamplifier and latch are active in the same corner configuration for PT variations. For every corner case the preamplifier’s gain and Latch intrinsic offset is bellow 1 mV, ensuring the comparator works as expected under PT variations. Figure 8 illustrates the DC variations in the comparator when /2 is in high. These curves show the comparator’s behavior when the amplifier stage is active. The variations for the preamplifier’s offset are below 3 mV. For every corner there is a similar behavior. Note the big difference between the response of the proposed comparator and the multistage solution (Figs. 3, 8 respectively).

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Fig. 6 Proposed comparator in a 65 nm CMOS process

The response to the step input of the proposed comparator is obtained when the preamplifier and Latch are active, these are shown in Fig. 9. For a step input with amplitude equal to half of a LSB, the time response in the typical corner is 13 ns and variations for the remaining corners are between 1 ns. Moreover, the variations in voltage levels are significantly reduced to 0:01 V compared to the resulting 0:44 V of the multistage comparator. This is a very good result that increases the overall comparator’s reliability. The proposed comparator’s permanence is confronted to state of the art schemes in Table 3. The comparator

Analog Integr Circ Sig Process Table 3 Comparison performance comparators

Fig. 7 DC variations simulation post layout (preamplifier and latch are active)

Spec

Multistage

This work

[11]

[12]

Tecnology (nm)

65

65

65

90

Supply voltage (V)

1.2

1.2

1.2

1.2

Step response (ns)

23

13

–

–

VosPA (mV)

±10

±75

–

–

VosL (mV)

179

1

–

–

Power (mW)

0.828

0.3756

2.88

1.2

Sensitivity (mV)

0.03672

0.03672

16.5

3

fclock (GHz)   FOM f WV Hz

0.02

0.02

4

0.750

1.52

0.69

11.88

0.85

reported in [11] is designed for high speed applications, reducing the residual offset. The comparator in [12] is designed for a SAR ADC with 13 bits of resolution. A well known figure of merit (FOM) is used [11] to propose a new FOM which strictly considers the comparator’s performance without considering the ADC application: FOM ¼

Vsens P fclock

ð3Þ

where P is the static power consumption, Vsens is the comparator sensitivity, and fclock is the maximum switching frequency. Our new circuit improves the voltage resolution and reduces power consumption. Besides, the comparator is this work is evaluated in PT with the corner analysis tools which are not reported in most of the recent solutions.

4 Performance comparison on a SAR ADC Fig. 8 DC variations simulation in preamplifier stage (/2 ¼ High)

Fig. 9 Step Response variations proposed comparator

To test the comparator’s performance a SAR ADC is designed with the specifications detailed in Sect. 2. A simplified circuit implementation of the SAR ADC is shown in Fig. 10. With this topology it is possible to obtain a higher than 10 bits resolution. The architecture is composed of a series of DAC capacitive arrays, the analog comparator and the successive approximation control logic. The logic includes the shift registers and switch drivers which control the DAC operation by performing the binary-scaled feedback during the successive approximation [10]. For this SAR ADC implementation, the DAC capacitive array is a well known structure and it samples the input signal and estimates the residue approximation in a single step. The resolution and robustness in this architecture mainly depends on the DAC structure and comparator’s topology [10]. Also, the DAC structure is based on the split capacitor array shown in Fig. 10 which reduces the total area for high resolution

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Analog Integr Circ Sig Process Table 4 Result of the statical corner analysis to the SAR ADC with the proposed and conventional multi stage amplifier comparatorscc Corner

TT 60 °C

FS 40  C

SF 40  C

SS 40  C

Conventional ENOB (bits)

13.60

12.30

8.80

10.00

Proposed ENOB (bits)

13.78

13.65

13.50

13.20

Fig. 10 ADC SAR fully differential with split array capacitor

Fig. 12 ADC SAR variations with multistage comparator

Fig. 11 Power spectral density to 1.28 MS/s in 20 kHz

[13]. It makes possible to obtain good results even in nano scaled technologies [14]. Moreover, the switches positions are determined by the successive approximation register and the control logic block. For the present case, the switches are designed to have low variations and the bootstrapping technique minimizes errors and RON variations during the sampling task [15]. The proposed and conventional comparators were tested in the ADC structure to compare their performance under PT variations. Figure 11 shows the power spectral density of the SAR–ADC in the TT corner @ 60  C. For the typical case both comparators structures allowed the SAR–ADC to achieve a similar SNR of 83.11 dB with an the ENOB of 13.51 bits. At a first glance, a conventional multi stage comparator will fulfill the requirements for the proposed application. Of course when the SAR ADC is subjugated to a conner analysis the typical comparator will not remain in the designed case. The ADC SAR was simulated under PT variations and Table 4 shows the most critical corners comparing the

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Fig. 13 ADC SAR variations with proposed comparator

ADC performance with both comparators. The results show that for the conventional comparator the critical corner is the slow NMOS—fast PMOS @ 40  C, in this corner the ADC SAR loses more than four bits. For the ADC using the proposed comparator the corner cases present a ENOB of more than 13 bits, the worst corner loses only 0.58 bits. A final test case is the time evolution of the SAR ADC. The 15 corner cases where simulated and the results are in Figs. 12 and 13 for the conventional and proposed

Analog Integr Circ Sig Process

comparator respectively. The time evolution is observed up to 700 ns. For the sake of clearness the zoomed transient for the last nanoseconds is highlighted. The conventional comparator makes the SAR ADC to have a significant amount of error at the end of the SAR algorithm (lowering resolution). For the proposed circuit even the zoomed plot details a good approximation for every corner analyzed in this paper. This is a clear evidence that the novel comparator in this work will improve the overall SAR ADC performance.

5 Conclusions The circuit comparator proposed in this work shows a very good performance under process and temperature variations in a 65 nm CMOS process. In addition, the topology has a good trade off between sensitivity, voltage offset and speed because it is composed of a single preamplifier stage. The principal difference with other topologies is that the proposed comparator reduces mismatch on the branch currents with a symmetrical circuit architecture. With the proposed circuit, a SAR ADC exhibits an 83.11 dB of Signal to Noise Ratio at 1.28 MS/s with a 375 lW of static power consumption. The process and temperature variations for critical corners are less than 0.58 bits which ensures a reliable SAR ADC for important applications. Acknowledgements The authors give special thanks to CONACyT Mexico for the financial support of the Project Infra 2013 #205873.

References 1. Xu, J., Bu¨sze, B., Van Hoof, C., Makinwa, K. A. A., & Yazicioglu, R. F. (2015). A 15-channel digital active electrode system for multi-parameter biopotential measurement. IEEE Journal of Solid-State Circuits, 50(9), 2090–2100. 2. Shu, Y. S., Kuo, L. T., & Lo, T. Y. (2016). 27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1 kHz BW in 55nm CMOS. In 2016 IEEE international solid-state circuits conference (ISSCC) (pp. 458–459). 3. Liang, Y., Zhu, Z., & Ding, R. (2015). A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS. Microelectronics Journal, 46, 988–995. 4. Chang, H.-W., Huang, H.-Y., Juan, Y.-H., Wang, W.-S., & Luo, C.-H. (2013). Adaptive successive approximation ADC for biomedical acquisition system. Microelectronics Journal, 44, 729–735. 5. Fitzpatrick, D. (2015). Implantable electronic medical devices (1st ed.). Atlanta: Elsevier. 6. Ohnhaeuser, F. (2012). A 1.5mW IMSPS 16bit SAR ADC with high performance. In 2012 International on semiconductor conference Dresden–Grenoble (ISCDG) (pp. 9–12).

7. Chi, Y. (2013). 16-bit 1MS/s 44mW successive approximation register analog-to-digital converter achieving signal-to-noiseand-distortion-ratio of 94.3dB. In 2013 IEEE international conference electron devices and solid-state circuits (EDSSC) (pp. 1–2). 8. Chen, M. (2013) A low-power Auto-zeroed Comparator for Column paralleled 14b SAR ADCs of 384x288 lRFPA ROlC. In IEEE international conference on electron devices and solid-state circuits (EDSSC) (pp. 1–2). 9. Figueiredo, P. M., & Vital, J. C. (2009). Offset reduction teqchniques in higspeed analog to digital converters. Berlin: Springer. 10. Gregorian, R. (1999). Introduction to CMOS OPAMPs and comparators. New York: Wiley. 11. Goll, B. (2009). A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V. IEEE Transactions on Circuits and Systems II: Express Briefs, 56(11), 810–814. 12. Miki, T. (2015). A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC with SNR and SFDR enhancement techniques. IEEE Journal of Solid-State Circuits, 50(6), 1372–1381. 13. Osipov, D. (2012). Behavioral model of split capacitor array DAC for use in SAR ADC design. In 8th Conference research in microelectronics and electronics (PRIME) (pp. 127–130). 14. Rehman, SU (2015) Reference-less SAR ADC for on-chip thermal monitoring in CMOS. In IEEE international symposium on circuits and systems (ISCAS) (pp. 2441–2444). 15. Aksin, D., Al-Shyoukh, M., & Maloberti, F. (2006). Switch bootstrapping for precise sampling beyond supply voltage. IEEE Journal of Solid-State Circuits, 41(8), 1938–1943.

Gisela de La Fuente-Cortes was born in Mexico City in 1987. She received her B.Sc. degree in Electronic Engineering at the Autonomous University of Puebla, Mexico in 2012. She also received her M.Sc. degree in Electronic Circuit Design at National Institute of Astrophysics, Optics and Electronics (INAOE), Mexico in 2014. She is also currently studying her Ph.D. degree at INAOE. Her research interests include Analog and Mixed Integrated Circuit Design, Robust Design of Analog Integrated Circuits and Medical applications. Guillermo Espinosa FloresVerdad was born in Mexico City, he obtained the M.Sc. degree from INAOE, Mexico, and the Ph.D. degree from Pavia University, Italy in 1983 and 1989. From 1980 to 1985 he worked in the Electronic Engineering Department at the Autonomous University of Puebla, Mexico. From 1990 to 1993 he worked in the Central Research and Development Department at SGS- THOMSON Microelectronics Corp., Italy, as head of the Analog Library Automation Group. In February 1993, he joined the Electronics Department at the National Institute of Astrophysics, Optics and Electronics (INAOE), Mexico as a Professor

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Analog Integr Circ Sig Process Researcher. He was with Freescale Semiconductor from 2005 to 2008 leading the Freescale Mexico Technology Center. Since 2008, he is, again, at INAOE Electronics Department as a Professor Researcher. His main research interests are in Analog and Mixed Integrated Circuit Design and CAD development for the automatic design, synthesis, analysis and layout of ICs, also he is interested in Robust Design of Analog Integrated Circuits, Medical applications, and Communications Systems. Victor R. Gonzalez-Diaz was born in Puebla, Mexico. Received the M.Sc. and Ph.D. at the National Institute for Astrophysics, Optics and Electronics (INAOE) Puebla Mexico in 2005 and 2009 respectively. He collaborated as a postdoc fellow at the Microsystems Laboratory of University of Pavia, Italy from 2009 to 2010. Since 2011 he is full time professor at the Faculty of Electronics BUAP, Puebla. His main research interests are frequency

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synthesizers, data converters and Sigma-Delta modulation for analog and digital applications. A. Diaz-Mendez is a Full Researcher in the Electronics Department at INAOE. He received his B.Sc degree from Universidad Veracruzana, Me´xico; followed by M.Sc and Ph.D. degrees from Instituto ´ ptica Nacional de Astrofı´sica, O y Electro´nica (INAOE), Me´xico, in 1995 and 1999 respectively. In 1999 he was appointed as professor-Researcher at Instituto Polite´cnico Nacional, Me´xico. He has authored 30 Journal papers and around 80 conference papers. He has been a member of technical committees in national and international conferences. He is an IEEE Senior member and a member of national researcher’s system of Me´xico.