Analog Integr Circ Sig Process (2014) 78:439–452 DOI 10.1007/s10470-013-0219-3

A time-domain noise-coupling technique for continuous-time sigma-delta modulators Hossein Pakniat • Mohammad Yavari

Received: 15 June 2013 / Revised: 20 October 2013 / Accepted: 21 October 2013 / Published online: 1 November 2013  Springer Science+Business Media New York 2013

Abstract In this paper, a time-domain noise-coupling technique based on the pulse width modulation is proposed. The time-domain quantization error is digitally extracted and shaped by an asynchronous digital filter. This digitally filtered quantization error is applied to the quantizer input to increase the modulator’s noise-shaping order. By using this technique in continuous-time sigma-delta modulators, the modulator’s shaping property is significantly enhanced. Comparative analytical calculations and simulation results are presented to estimate the performance of modulators employing the proposed quantizer. System-level simulation results reveal a (L ? 2)th order noise-shaping capability of the proposed modulator while it employs only L analog integrators. The effects of main circuit non-idealities in the modulator’s performance are analytically investigated and confirmed by the simulation results. Keywords Noise-coupling  Continuous-time sigma-delta modulators  Time-mode signal processing  Pulse width modulation  Time-mode quantization

increases the time resolution by enhancing the speed of transistors. Time-domain signal processing is a suitable solution to alleviate the problem of the supply voltage reduction in nano-meter CMOS technologies [1–11]. In time-domain signal processing, the information in amplitude of a signal is mapped into the time difference between two rising and/or falling edges. The process on the resultant digital signal is benefited from the advantages of modern digital circuits. Time-mode signal processing has been proposed in [1]. By using the time-mode signal processing, different quantizers, such as the pulse width modulation (PWM) [2, 3], time encoding (TEQ) [4–7] and VCO-based [8–11], have been introduced. Except the VCO-based quantizer, usually the other quantizer schemes have no inherent noise-shaping capability. Hence, the noise-shaping order of sigma-delta modulators is usually equal to the order of their loop filter. By using the noise-coupling technique, the noise-shaping property of sigma-delta modulators can be enhanced [12–17]. In the conventional noise-coupling shown in Fig. 1, the quantization noise, Eq(z), is extracted, filtered by S(z), and then injected into the quantizer’s input. Assuming a linear model, the output signal is given by:

1 Introduction

RðzÞ ¼ STFðzÞ  XðzÞ þ Eq ðzÞ NTFðzÞ  ½1  SðzÞ

The scaling of CMOS technology directly limits the available dynamic range in analog circuits due to the supply voltage reduction. On the other hand, the scaling

where NTF(z) is the discrete time equivalent of the modulator noise transfer function (NTF) in the absence of noise-coupling and STF(z) is the discrete time equivalent of the modulator signal transfer function. According to the relation (1), the quantization noise is shaped by (1 - S(z)) and then multiplied by the modulator’s NTF. In the noise-coupling path in Fig. 1, both the subtraction and filtering operations require analog elements. The passive implementation of both subtraction and filtering suffers from the high sensitivity to the parasitic capacitances and device elements mismatch [12, 15], while

H. Pakniat  M. Yavari (&) Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran e-mail: [email protected]

ð1Þ

123

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Analog Integr Circ Sig Process (2014) 78:439–452

X(s)

F(s)

2 Proposed time-mode noise-coupling for CT-RDMs

R(z)

fs DAC

DAC

M-level Eq(z)

S(z)

Fig. 1 Conventional voltage-mode noise-coupling in CT-RDMs

the active implementation requires an additional power [15]. These are the main drawbacks of the conventional noisecoupling technique. In fact, the voltage-mode noise-coupling (or the error feedback) structure may be impractical for RD ADCs especially for orders higher than one [12, 15]. This problem is more serious in CT-RD ADCs [15, 17]. In this paper, a time-mode noise-coupling technique with digital implementation is proposed for CT-RDMs. Due to its digital nature, the proposed technique eliminates the disadvantages of its analog counterpart. For this purpose, the conventional quantizer of CT-RDMs is replaced by a PWM-based quantizer. The PWM block transfers the input signal amplitude into the pulse width and it is then quantized by a time-to-digital converter (TDC). The quantization noise of TDC is digitally extracted, filtered and fed back into the quantizer input. Depending on filtering properties of noise-coupling path, the modulator’s noise-shaping order is enhanced. Furthermore, unlike the multi-bit modulator, there is no DAC nonlinearity problem due to the usage of the three-level PWM feedback signal. The paper is organized as follows. The proposed noisecoupling technique for CT-RDMs is presented in Sect. 2. In Sect. 3, the comparative simulation results confirm the analytical results of Sect. 2. In Sect. 4, the effects of main circuit non-idealities in the proposed modulator are explained. The clock jitter immunity of the proposed CTRDM is examined in Sect. 5. The proposed modulator is compared with the conventional multi-bit modulators in Sect. 6. Finally, Sect. 7 concludes the paper.

Figure 2 illustrates the proposed time-based noise-coupling scheme employed in the CT-RDMs. In this architecture, the conventional flash ADC is replaced by a PWM-based one and it is comprised of a PWM generator and a TDC. The output signal of TDC, pq[r], is fed back into the loop filter (F(s)) to constitute the main loop of the proposed modulator. The FIR-DAC improves the modulator’s immunity against clock jitter [18, 19]. In this architecture, similar to the conventional noise-coupled RDM (Fig. 1), the quantization error is extracted, filtered and then applied to the quantizer’s input. But unlike the conventional architecture, most of the signal processing is performed in time-domain which is benefited from the digital circuits’ advantages. 2.1 PWM generator The PWM generator transfers the voltage-mode input signal into a time-domain one. There are various types of PWM generator implementation including rising-ramp (RR) PWM, falling-ramp (FR) PWM, triangular-wave (TW) PWM, and double-ramp (DR) PWM [18]. With the same number of quantization levels, the quantization noise floor of a PWM-based quantizer is more than that of the conventional amplitude quantizer resulting in lower dynamic range [2]. In other words, the harmonic distortion of the quantized signal folds over to form the quantization noise floor [1], while the symmetry of DRPWM reduces the harmonic distortion of the quantized PWM signal [18]. It is shown that unlike the other kind of PWM, the DR-PWM neither increases the noise floor nor introduces the second-order harmonic distortion [18]. Therefore, the DR-PWM is used as the PWM generator in the proposed quantizer to enhance the dynamic range of PWM-based quantizers. As shown in Fig. 2, the voltage of

Voltage-mode (analog) x(t)

F(s)

RR-PWM

f s v [nTs] Ts=1/fs

Time-mode (digital) Vd -V d

Vd

−1

FIRDAC

-Vd

16

32

k(t )

Fig. 2 Proposed time-mode noise-coupling in CT-RDMs

123

Vd -Vd

M=16 M-level 16

32

p(t)

TDC TDC

H 1(s)

y [n] pq[r]

fs 16

Vd

32

Vd

H(s) H2(s)

32

1/2 DR-PWM

FR-PWM

PWM generator

16 Vd -Vd

-Vd

-Vd 16

32

e(t) Noise-coupling

3-level

16

32

Analog Integr Circ Sig Process (2014) 78:439–452

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DR-PWM (p(t)) is the average of two-level voltages of RRPWM and FR-PWM. The output signal of a PWM generator is a three-level signal (-Vd, 0, Vd), where Vd is the half of the full-scale peak-to-peak input voltage, VFS. In each modulator’s sampling period, the pulse of p(t) is symmetric with respect to its period center. During the nth sampling period, nTs B t \ (n ? 1)Ts, the pulse width of p(t) can be expressed as: T½n ¼

2Ts  jv½nTs j VFS

ð2Þ

where 2Ts/VFS is the PWM gain conversion, v[nTs] is the sampler output signal, and the sampling period, Ts, is the maximum value of T(.). The sign of p(t) and v[nTs] is the same. Considering (2), the input–output relation of the PWM generator or the time-to-voltage converter (TVC) is given by: 1 v½nTs  ¼ Ts

ðnþ1ÞT Z s

pðtÞ dt

ð3Þ

r2q ¼

ðVFS =MÞ2 12

ð5Þ

Similarly, the variance of quantization noise in both TEQ [4, 5] (with fs = M 9 fc) and VCO-based [8, 9] (with M-level TDC) quantizers is proportional to 1/M2, where fs is the sampling frequency and fc is the TEQ self-oscillation frequency. It is stated in [6] and [7] that the quantization noise variance of a TEQ quantizer with an M 9 fc sampling frequency is proportional to 1/M, while other works [4, 5], show that the quantization noise variance is proportional to 1/M2. The simulation results of this paper (with models given in [6] and [7]) confirm the latter. With the same sampling frequency, fs, both the proposed PWM and VCO-based quantizers require M different phase shifts of the sampling clock. In contrast, a TEQ quantizer with the same oversampling ratio (OSR = fc/(2 9 BW) as is its counterparts, require M times higher clock rate for M quantization levels [4, 5].

nTs

Relation (3) is the inverse transform of the PWM generator and its Laplace domain equivalent is as follows: GðsÞ ¼

VðsÞ 1  esTs ¼ fs  PðsÞ s

ð4Þ

2.2 Time-to-digital converter The TDC quantizes the pulse width of a PWM signal. In a conventional M-level flash ADC, M-1 comparators with a resistive-ladder are used to quantize the voltage levels of the sampled input signal [12]. In contrast, in the M-level TDC, a ring oscillator divides the phase of the input clock into M-1 similar parts. Then, M-1 D-flip-flops employ these M-1 phase-shifted samples of the clock to quantize the pulse width of the input signal [3]. Similar to p(t), one of the output signals of TDC, pq[r], is a three-level signal. But unlike p(t), both rising and falling edges of pq[r] are aligned to one of M-1 rising edges of the TDC clock phaseshifted samples. Another output signal of TDC, y[n], is the M-level digital equivalent of v[n]. As mentioned before, in each modulator’s sampling period, the pulse of p(t) is symmetric with respect to its period center. In order to preserve this symmetry in pq[r], the sampling times of TDC are also symmetric with respect to the center of the corresponding period. Simulation results reveal that the aforementioned symmetry reduces the quantization noise floor of TDC. The PWM generator and the TDC block together map the full-scale voltage (VFS) into an M-level digital signal. Therefore, for a busy (i.e., rapidly and randomly varying) input signal, the quantization error can be approximated with a zero-mean white noise with the mean square value of [12]:

2.3 Noise-coupling The noise-coupling block extracts the TDC quantization error, e(t), by subtracting p(t) from pq[r] in digital domain as shown in Fig. 2. Although both p(t) and pq[r] are threelevel signals, but in each sampling time, both of them have two-level voltages with the same sign. Thereby, the subtraction result, e(t), is a three-level signal. Similar to the conventional architecture in Fig. 1, the modulator’s noise-shaping capability can be improved by injecting the quantization error voltage into the loop filter and the suitable design of H(s). e(t) is a time-domain signal which can be transferred into a voltage-domain signal by TVC, H(s) = G(s). Regarding the sampling time, fs = 1/Ts, and using the modified Z-transform, the discrete-time equivalent of G(s) is obtained as: ðZm1 fGðsÞ=sg  Zm2 fGðsÞ=sgÞ ¼ ð1  z1 Þ  ¼ z1



z1 1  z1

 ð6Þ

This implicates that the discrete-time model of TVC, G(s), is a unit delay at the rate of fs. Hence, by passing e(t) through H(s) = G(s), a first-order noise-coupling (1 z-1), is achieved. H(s) may be implemented by the cascade of H1(s) = 1 - e-sTs and H2(s) = fs/s. H1(s) consists of a continuous-time (CT) delay and a digital adder. e(t) is a digital signal, and so, the CT delay can be implemented, for example, by the cascade of currentstarved digital inverters. Low-power widely tunable CT delay cells are introduced in [20, 21]. H2(s) is an analog integrator which can be merged in the last integrator of F(s).

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Fig. 3 Proposed modulator with simplified noise-coupling circuit (an Lth order CT-RDM combined with a second-order noise-shaping PWM quantizer)

In modulator of Fig. 1, by selecting S(z) = z-19(2 - z-1), a second-order noise-coupling is achieved (1 - S(z) = (1 z-1)2). Intuitively, the noise-coupling order of the proposed system can be further increased similarly. The simplest way is to multiply the feedback signal by 2 - z-1, while TVC has an inherent z-1. The time-mode feedback signal continually varies, and hence, the transfer function 2 - z-1 should be replaced by its continuous-time equivalent, 2 - e-sTs. Briefly, in the proposed noise-coupling system, H1(s) = 1 - e-sTs leads to a first-order noise-coupling while modifying it as H1(s) = (1 - e-sTs) 9 (2 - e-sTs) results in a second-order noisecoupling. Also, higher order noise-coupling may be achieved provided that the stability requirements are carefully considered [12]. Unlike the conventional noise-coupling, in the proposed digital noise-coupling scheme, the feedback coefficients are implemented by digital elements which are not prone to the variations. Figure 3 illustrates an Lth order CT-RDM which employs the proposed noise-coupling PWM-quantizer. The noise-coupling block is simplified and it is explained in the next sub-section. The noise-coupling does not change the STF of the modulator [13–17]. Thereby, the (L ? 2)th order modulator shown in Fig. 3 benefits from the immunity of the Lth order CT-RDM against the excess loop delay. The fast path around the quantizer through DACL?1 compensates the excess loop delay in CT-RDMs [22, 23]. The NTF of the Lth order CT-RDM shown in Fig. 3 without any zero optimization can be expressed as: L

NTFCT ðsÞ ¼

s sL þ kL fs sL1 þ    þ k2 fsL1 s þ k1 fsL

ð7Þ

In the signal bandwidth, [0, fs/(2 9 OSR)], NTFCT(s) is equal to the Lth order high-pass filter of sL/(k1fLs ), while its frequency domain equivalent is (1/k1) 9 (2pf/fs)L. In the proposed quantizer, all of the sampling and time-domain signal processing take place after the loop filter. Hence, they are shaped by NTFCT and the proposed modulator is as tolerant as its CT-modulator against sideband blockers.

123

The quantizer overload level ratio, which is defined as AOL = 2 9 max[x(t)]/VFS, is equal to [12, 24]: NTFð1Þ  2 ð8Þ AOL ¼ 1  M For a sinusoidal input signal with the amplitude of AOL 9 VFS/2, the dynamic range of CT-RDM can be estimated as [22]:   3 OSR 2Lþ1 DRCT ¼ pA2OL ðk1  M Þ2 ð2L þ 1Þ  ð9Þ 2 p where OSR is the modulator’s oversampling ratio. If a pair of NTFCT zeros were optimally placed at the inband frequencies, the DR introduced in (9) is multiplied by (L - 0.5)2 [25]. The proposed noise-coupling technique increases the noise-shaping order by a factor of Ld. In other words, the discrete-time equivalent of the modulator’s NTF is multiplied by (1 - z-1)Ld. Therefore, the whole modulator’s NTF in the signal bandwidth is obtained as:  2  2ðLþLd Þ 1 2pf 2 jNTFðf Þj  ; f  fs ð10Þ k1 fs Thus, for a sinusoidal input signal with the amplitude of AOL 9 VFS/2, the dynamic range of the proposed modulator is given by: 3 DR ¼ pA2OL ðM  k1 Þ2 ð2ðL þ Ld Þ þ 1Þ 2   OSR 2ðLþLd Þþ1  p   2ðL þ Ld Þ þ 1 OSR 2Ld  ¼ DRCT ; ð2L þ 1Þ p Ld ¼ 0; 1; 2

ð11Þ

If a pair of NTFCT zeros were optimally placed at the inband frequencies, similar to the relation (9), the dynamic range in relation (11) is multiplied by (L-0.5)2 [25]. The dynamic range of a VCO-based quantizer can be achieved by setting Ld = 1 in relation (11), while for a TEQ quantizer, Ld = 0, M = 2fs/(3fc) and OSR = fc/(2*BW). fc

Analog Integr Circ Sig Process (2014) 78:439–452

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and BW are the PWM self-oscillation frequency and signal bandwidth, respectively. It should be noted that using each aforementioned quantizers may require its own NTF design, and consequently, k1 may be different for each one. 2.4 Simplified TVC As introduced in relation (4), (1 - e-sTs) 9 fs/s is the TVC which can be used to calculate the voltage equivalent of the time-domain error (e(t)) in each modulator’s sample. By a suitable design of a, the low-pass filter of a/(s/fs ? a) can estimate the average of e(t) on each sampling interval as well. The replacement of (1 - e-sTs) 9 fs/s by a/(s/fs ? a) has four advantages. Both the jitter noise and nonlinearity error of corresponding DAC in Fig. 3 referred to the modulator’s input is one-order more shaped. The quantizer’s digital circuit is simplified. The number of levels in w(t) and its corresponding DAC elements are reduced from 13 to 7. Finally, the number of transitions per sampling period in w(t) is reduced, and consequently, the sensitivity of the corresponding DAC to the clock jitter is reduced. In order to design the value of a, we may equalize the value of functions at the end of each sampling interval. Due to the circuit level limitations, the maximum voltage swing in the last integrator is limited to k 9 VFS/2 (k \ 1) or equally -k 9 VFS/2 B v[n 9 Ts] B k 9 VFS/2. Hence, according to the relation (2), the output pulse width is limited to kTs (T[n] B kTs). For an input signal with the maximum pulse width of kTs ((u(t)–u(t - kTs) (u(.) is the step function), the function of (1 - e-sTs) 9 fs/s gives the value of k 9 VFS/2. For the same input signal, the function of a/(s/ fs ? a) is supposed to give the same voltage value at the end of each sampling interval (VFS = 2 V). So, we have: Ve ðt ¼ Ts Þ ¼ ð1  ea Þ  ð1  eað1kÞ Þ ¼ k  VFS =2)a 1 þ ln ð1  kÞ ; ¼ k1 1 while 1  e \k\1 ðfor 0\a\1Þ ð12Þ

IDACL+1

IDACL+2

R

R C

C

RI

CI

2.5 FIR-DAC The three-level PWM signal of TDC, pq[r], is used as the feedback signal in the CT-RDM. In order to transfer the digital PWM signal of TDC (pq[r]) into a multi-bit signal, the discrete-time equivalent of G(s) is used. In this way, the clock jitter immunity of the modulator can be improved. The time resolution of pq[r] is M times higher than the modulator’s sampling time. Hence, by using the modified Z-transform [22], the discrete-time equivalent of G(s) at the sampling rate of M 9 fs is given by: GðzÞ ¼ ðZm1 fGðsÞ=sg  Zm2 fGðsÞ=sgÞ ¼

This relation suggests an M-tap first-order sinc filter followed by a unit delay. G(z) is merged in the feedback DACs as an FIR-DAC to improve the clock jitter immunity of the modulator. As illustrated in Fig. 5, the FIR-DAC is the pseudo digital implementation of G(z) in the body of the original 3-level DAC [19]. The delay line consists of D (z)

VintegL

z1 ð1  zM Þ 1  z1 ð13Þ

2Nd-1 v0 f0

z -1

v1

f1

v2

z -1 f2 +

z -1

vM-1

fM-1

FIR-DAC

Vinteg(L-1) R0

Relation (12) designs a depending on the maximum swing allowed in the last integrator. The lower value of a, the lower is the delay of a/(s/fs ? a). Hence, for a [ 2, a = 2 is suggested. Based on the simulation results, both the modulator’s SNDR and stability have very low sensitivity to the variation in a (e.g. for 20 % variation of a, the SNDR varies only by 1 dB and the modulator remains stable). In the noise-coupling loop, the function 2 - e-sTs is directly implemented and the 1 ? ss/fs & ess/fs term compensates the excess loop delay of e-ss/fs for s 9 f  fs [26]. By using this compensation method, the quantizer’s excess loop delay up to 2Ts/M can be compensated without any significant performance degradation. Also, in the delay compensation loop (k*), the 1 ? ss/fs & ess/fs term compensates the delay of the last integrator. Figure 4 shows the implementation of the last integrator, in which the function of a(1 ? ss/fs)/(s/fs ? a) in both mentioned paths is realized, where 1/(RC) = a 9 fs, 1/(RICI) = fs/s and max[IDAC] 9 RC/CI = VFS. The transfer functions of IDACL (DACL?1 and DACL?2) to the integrator output is IDAC 9 Cs 9 (RI ? 1/CIs)/(Cs ? 1/R).

YDAC (z) Fig. 4 Impelementation of the last loop-filter integrator

Fig. 5 FIR-DAC implementation

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Table 1 The coefficients used in Fig. 3 for different simulations of Figs. 6 and 7 Quantizer type

L = 2, M = 8

L = 2, M = 16

k1

k2

k1

k2

k1

k2

k3

PWM

0.25fs

0.5fs

0.25fs

0.75fs

0.3fs

0.8fs

fs

VCO

0.25fs

0.5fs

0.25fs

0.75fs

0.05fs

0.3fs

0.6fs

TEQ

0.0987fs = 6.31fc

0.314fs = 2.51fc

0.0987fs = 6.31fc

0.314fs = 2.51fc

0.004fs = 0.9fc

0.044fs = 1.6fc

0.283fs = 1.7fc

M-1 delay elements. Each element has a delay of Ts/ M. Calculating the phase of G(z), its corresponding delay is M/2 9 Ts/M, and thus, the delay of the FIR-DAC is Ts/2. The delay elements may be implemented, like CT delays, by the cascade of current-starved digital inverters or they can be implemented by digital latches working at M 9 fs. The prior is more power efficient while the later is more accurate. The analog parts of FIR-DAC (the adder and the coefficients, f0, f1,…,fM-1) are implemented as the DAC components in the body of the loop filter integrators (i.e. through weighted current cells injected to the amplifier’s virtual ground). Unlike the conventional multi-bit DAC, the elements mismatch in an FIR-DAC leads to the coefficients mismatch which only modifies the frequency response [18, 19]. Although, two outer feedback paths (DAC1 and DAC2) have inherent TVC (loop filter integrators), but G(z) is merged in these DACs as two FIR-DACs to improve the modulator’s clock jitter immunity.

3 Comparative behavioral simulation results of proposed noise-coupling quantizer The performance of the CT-RDM in Fig. 3, employing the proposed noise-shaping PWM quantizer, is predicted in relation (11) and it depends on the OSR, the loop-filter order (L), the order of noise-coupling (Ld), and the number of levels in the embedded quantizer (M). As noted in the previous section, the performance of CT-RDMs employing the other time-based quantizers (TEQ and VCO-based) can be predicted by the relation (11) as well. In this Sect., these parametric analyses are supported by the comparative behavioral simulations. 3.1 Simulation assumptions and models For simulation purposes, the proposed noise-coupled PWM quantizer, the TEQ quantizer (as presented in [6, 7]) and the VCO-based quantizer (as introduced in [8]) were modeled in SIMULINK and MATLAB. The nonlinearity was not modeled either for the voltage-to-delay converter

123

L = 3, M = 16

Table 2 The local feedback coefficient (f) used in Fig. 3 for different simulations of Figs. 6 and 7 Quantizer type

L = 2, OSR = 10

L = 2, OSR = 16

L = 3, OSR = 8

PWM

0.05

0.02

0.12

VCO

0.05

0.02

0.12

TEQ

0.0046

0.002

0.1667

of VCO-based quantizer or for the ramp signals in the proposed PWM quantizer. However, the TEQ quantizer has an inherent nonlinearity due to its one-bit quantizer. Each quantizer was separately simulated in the CT-RDM of Fig. 3 with different performance metrics (L, M and OSR). The modulator’s loop filter has different designs for each quantizer and also for different values of L and M. Table 1 summarizes the modulator coefficients shown in Fig. 3 when different quantizers and performance metrics are utilized. Also, Table 2 shows the values of the local feedback (f) coefficient in different simulation cases. The TEQ quantizer has a two-level (M = 2) nature with a very simple circuit. However, the modulators employing this quantizer require a very high OSR (fs/(2 9 BW)) [4–7] and they are severely prone to the nonlinearity problems [4]. A self-oscillation PWM signal is embedded in these modulators to prepare an alternative interpretation. By assuming the oscillation frequency as the modulator’s sampling frequency (fc \ fs), the modulator can be interpreted as a multi-bit one with M = 2fs/(3fc) levels and a lower OSR of fc/(2 9 BW). Assuming fc as the sampling frequency instead of fs leads to the higher gain of modulator’s integrators related to the sampling frequency (c 9 fs = c 9 (fs/fc) 9 fc = c0 9 fc and c \ c0 . However, both the single-bit and multi-bit interpretations of modulators with a TEQ quantizer have approximately the same analytical dynamic range given by relation (11), while the later is better matched with the simulation results. Therefore, the second interpretation is used in future explanations. The coefficients of the second and third order modulators employing the TEQ quantizer are exactly the same as those reported in [6] and [7], respectively. Referred to the sampling frequency (fs), these coefficients introduce conservative NTFs suitable for modulators with

Analog Integr Circ Sig Process (2014) 78:439–452 80

445

(a) L=2, M=16, OSR=10

80

60

SNDR (dB)

60 70

SNDR (dB)

(a) L=2, M=16, OSR=8

70

60

60

40

-10

-5

0

20

PWM TEQ VCO

0 -80

-60

-40

40

50 -10

-5

20

PWM TEQ VCO

0

-20

-80

0

-70

-60

80

(b) L=2, M=8, OSR=10

60

SNDR (dB)

50

40

-10

-5

0

20

PWM TEQ VCO

0 -70

-30

-20

-10

0

(b) L=3, M=16, OSR=8

80

-60

-50

-40

-30

-20

-10

90

60 50

40

-10

-5

0

PWM TEQ VCO

0

0

-80

-70

-60

-50

-40

-30

-20

-10

0

Amplitude (dBFS)

Fig. 7 Comarision of SNDR versus the input signal of the modulator shown in Fig. 3, when employing the proposed noise-coupled PWM, TEQ quantizer, and VCO-based quantizers for two values of L

(c) L=2, M=8, OSR=16

80

60

20

Amplitude (dBFS)

80

SNDR (dB)

-40

70

SNDR (dB)

60

-50

Amplitude (dBFS)

Amplitude (dBFS) 70

0

60 70 60

40

-10

-5

0

20

PWM TEQ VCO

0 -80

-60

-40

-20

0

Amplitude (dBFS)

Fig. 6 Comarision of SNDR versus the input signal of the modulator shown in Fig. 3 when employing the proposed noise-coupling PWM, TEQ, and VCO-based quantizers for differents values of M and OSR

one-bit quantization. However, when referred to the TEQ self-oscillation frequency (fc), the modulator’s coefficients present an aggressive NTF. In relation (11), the second interpretation is used for metrics k1, M and OSR to calculate the analytical performance of the modulator with the TEQ quantizer. The VCO-based quantizer has a systematic delay of Ts (= 1/fs) which is compensated by a fast path around the quantizer. Also, the quantizer has an inherent noise-shaping capability, (1 - z-1) (or Ld = 1), which multiplies the out-band-gain of NTF (NTF(z = -1)) by 2. Considering two aforementioned points, the modulator’s NTF with the VCO-based quantizer is designed and the corresponding coefficients are summarized in Table 1.

The proposed noise-coupling PWM quantizer employs an FIR-DAC which has a delay of Ts/2. This delay is compensated by a fast path around the quantizer. On the other hand, the modulator’s shaping order is enhanced two times, (1 z-1)2 or (Ld = 2), by the proposed noise-coupling scheme which multiplies the out-band-gain of NTF (NTF(z = -1)) by 4. Considering the above points, the NTF of the modulator with the proposed quantizer is designed and the corresponding coefficients are also summarized in Table 1. 3.2 Simulation results and discussions The simulation results of the proposed noise-coupling PWM quantizer and TEQ and VCO-based quantizers are shown in Figs. 6 and 7. Dashed line curves are corresponding to the system level simulation of modulators employing three above-mentioned quantizers, while the solid lines are their corresponding analytical results calculated from the relation (11). As is clear, there is a good accuracy between the analytical calculations and simulation results. Compared to Fig. 6(b), (a) and (c) illustrate the modulator’s performance versus M and OSR variations, respectively. Figure 7 shows the simulated modulators performance versus different modulator’s order, L. In all curves shown in Figs. 6 and 7, the modulators with a VCO-based quantizer have the lowest SNDR and the

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3.3 Behavioral simulation of proposed noise-coupling quantizer in feed-forward topology In order to test the proposed noise-coupling PWM quantizer in a different topology, the modulator of Fig. 3 was reconfigured as the feed-forward architecture. An active adder

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0 L=3, M = 16, OSR = 8 FFT-points = 8192 SNDR = 78 dB

-20

PSD (dB)

dynamic range. In fact, the large delay of a VCO-based quantizer leads to the conservative design of the modulator’s NTF or equally a low value for the outer most feedback gain (k1) resulting in the lowest dynamic range among the simulated modulators as also predicted by the relation (11). In both Figs. 6 and 7, comparing the performance of a VCO-based quantizer with its counterparts, it can be inferred that this quantizer is more suitable for low values of L and high values of M and OSR. In fact, the simple nature of this quantizer is well suitable for high values of M and OSR, while its systematic delay forces the design to low values of L due to stability requirements. These statements are more supported by considering the experimental results presented in [8–10]. Modulators with both proposed PWM and TEQ quantizers have almost similar SNDR and dynamic range. According to Fig. 6, for higher values of OSR, the performance of modulators with the proposed PWM quantizer outperforms that of the TEQ quantizer. On the other hand, as illustrated in Fig. 7, even for a low OSR, selecting L = 3 leads to a higher performance in the modulator with the proposed PWM quantizer. In other words, the proposed quantizer is well suited for L C 3 and low values of OSR, while both TEQ and VCO-based quantizers are more suited for low values of L and high values of OSR. Without having a practical implementation of the proposed PWM quantizer, it is difficult to compare its power consumption with the other time-based quantizers. However, a course estimation may be possible. The TEQ quantizer has a simpler architecture compared to the proposed noise-coupling PWM quantizer, while the TEQ quantizer requires a very higher (M times) sampling clock and introduces severe nonlinearity problem [4]. This high sampling clock increases the required gain-bandwidth product (GBW) of the operational amplifiers. A modulator with the TEQ quantizer is less sensitive to the feedback coefficient variations [7]. In contrast, the proposed quantizer offers excellent flexibilities for multi-standard applications. The TDCs used in both VCO-based and proposed PWM quantizers are approximately the same, while the voltageto-time conversion in the VCO-based quantizer is simpler than the PWM one. On other hand, the proposed quantizer suggests more linear voltage-to-time conversion and adds less delay compared to its counterpart. Besides, the modulator with the proposed quantizer requires a much lower OSR in comparison to the VCO-based one.

Analog Integr Circ Sig Process (2014) 78:439–452

-40 -60 -80 -100 -120 -140

-3

10

-2

10

-1

10

Normalized frequency (fs =1)

Fig. 8 Output PSD of the proposed modulator shown in Fig. 3 when reconfigured in the feed-forward architecture

with a GBW of 2p 9 fs was assumed prior to the quantizer to add the feed-forward paths. In these simulations, L = 3, OSR = 8, and M = 16 (4-bit quantizer) were used. The noise-coupling NTF is fixed as (1 - z-1)2, where two zeros and all poles of the CT-RDM NTF are optimized for higher SNDR and stability considerations, respectively. For M = 16, fifth-order noise shaping, and OSR = 8, the modulator’s coefficients are k1 = 0.3, k2 = 0.8 and k3 = 1, while the local feedback gain is n = 0.12. In this way, the discrete-time equivalent of the modulator’s NTF has an outof-band gain of 8, NTF(z = -1) = 8. Thereby, according to the relation (8), the modulator is not overloaded for input levels up to 0.62 9 VFS. For an excess loop delay of 3/4 9 Ts, the coefficients were redesigned as k1 = 0.3, k2 = 1, k3 = 1.6 and k* = 1. The excess loop delay of the noise-coupling loop was assumed to be two times that of the digital time resolution (s 9 Ts = 2Ts/M). A sinusoidal input signal at the frequency of fs/512 was used. The output swing of integrators is limited to 0.75 9 VFS (k = 0.75), and according to the relation (12) a = 1.55 is achieved. Figure 8 shows the simulated output power spectral density (PSD) corresponding to the peak SNDR of 78 dB when a -4.4 dBFS input signal is applied. The third harmonic distortion in Fig. 8 is due to the limited swing in the operational amplifiers which has been modeled at the system level.

4 Circuit non-idealities The effect of main circuit non-idealities on the proposed modulator performance are investigated in this section and the clock jitter noise is analyzed in the next section. In future analysis and simulations, the excess loop delay of the modulator and noise-coupling loops are considered as 3/4 9 Ts and Ts/8, respectively, and they are compensated for. Therefore, both the NTF and STF of the modulator are unchanged. Besides, in all future simulations, the

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447

SNDR (dB)

SNDR (dB)

80 60

N=4 OSR = 8 M = 16

40 20 0

Multi-bit modulator Proposed modulator 0

2

4

6

8

Fig. 9 SNDR versus the normalized GBW of the first and second amplifiers used in the proposed modulator shown in Fig. 3

modulator shown in Fig. 3 is employed with OSR = 8, M = 16, and L = 3. 4.1 Quantizer input-referred errors The circuit non-idealities of the PWM-based quantizer (e.g. the nonlinearity problem of the ramp signal, both inputreferred noise and offset of the comparators) are shaped by the loop filter integrators. In Fig. 3, the quantizer errors are transferred to the output by the function presented in relation (7). As noted before, in the signal bandwidth, [0, fs/ (2 9 OSR)], |NTFCT(f)|2 & (1/k1)2 9 (2pf/fs)2L. The input-referred error of the proposed quantizer is modeled as a white noise with one-sided PSD of 2r2eq/fs shaped by |NTFCT(f)|2. The integral of this noise over the signal bandwidth [0fs/(2 9 OSR)], should be less than the half least significant bit (LSB) of the modulator. For the maximum input signal of AOL 9 VFS/2 and the modulator’s effective number of bits of B, the modulator’s LSB is AOL 9 (VFS/2)/2B. The modulator’s local feedback coefficient, n, decreases the inband noise by a factor of (L - 0.5)2 [25]. The inband noise should be less than half of the modulator’s LSB resulting in: r2eq p2L

) req 

M = 16 OSR = 8

0.9

0.95

A2  ðVFS =2Þ2  OL 2 2 4  22B ðL  0:5Þ k1 OSR2Lþ1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Lþ0:5 k1 AOL ðVFS =2ÞOSR ðL  0:5Þ  ð2L þ 1Þ 2Bþ1 pL ð14Þ

For the parameters used in the simulation of Fig. 8, the relation (14) suggests that req B 3.6 9 10-39VFS/2. So, the proposed quantizer requires about 9-bit accuracy which is practical as well [3]. However, the quantizer offset can be much more than the upper limit given in (14). As mentioned before, the last integrator output signal is bounded to -k 9 VFS/2 B v[n 9 Ts] B k 9 VFS/2. As a result, there is a voltage margin of ±(1 - k) 9 VFS for the quantizer offset. Besides, in this voltage margin, the linearity of the ramp signal is not important, and so, it needs a simplified implementation.

1

1.05

1.1

Delay/ Ts

10

ω u/(2π fs )

ð2L þ 1Þ 

78 76 74 72 70 68 66

Fig. 10 SNDR versus the normalized delay of delay elemnt (e-sTs in Fig. 3)

4.2 Limited gain bandwidth of modulator amplifiers The active-RC implementation was assumed for all integrators in Fig. 3. The limited GBW of modulator’s amplifiers were modeled similar to [5] as a first-order system with the GBW and -3 dB cutoff frequency of xu and xp, respectively. Figure 9 compares the simulated SNDR versus the normalized xu of both first and second amplifiers between the proposed modulator (Fig. 3) and the conventional multi-bit modulator of Fig. 1. According to Fig. 9, both modulators require the same xu. In these simulations, the amplifier employed in the third integrator assumed to have a GBW of xu = 2 9 2pfs rad/s. It can be inferred from this figure that xu = 2 9 2pfs rad/s is a suitable value for the first and second integrators amplifier in both modulators. In other words, the required amplifier GBW of the proposed modulator is the same as the conventional multi-bit one. 4.3 Delay variation of delay element in noise-coupling loop The delay element (e-sTs) used in the noise-coupling loop of Fig. 3 has a nominal delay of Ts. The value of this delay may change due to the various reasons (e.g. the process, temperature and power supply variations). The effect of delay variations on the proposed modulator performance is shown in Fig. 10. As is seen, the admissible range of delay with a 2 dB SNDR degradation is [0.96 9 Ts 1.04 9 Ts]. In other words, the allowable delay error is ±4 %. In these simulations, the bit length of w(t) was fixed to its original value (7-level shown in Fig. 3) and any likely additional level due to the delay element variation is truncated.

5 Clock jitter immunity According to Fig. 3, the modulator’s feedback paths use pq[r] as the input while the noise-coupling feedback path employs both pq[r] and p(t). pq[r] is a discrete-time digital signal whose information is stored in its amplitude. The

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edge’s jitter of pq[r] does not change its digital equivalent and just in feedback path, it changes the integral of the current injected into the loop filter through the corresponding DACs. Therefore, the jitter error of pq[r] is added in the feedback path and it is directly appeared at the output signal. In contrast, p(t) is a PWM signal whose information is stored in the time difference of its rising and falling edges. As a result, the edge’s jitter of p(t) affects its information, while simultaneously it changes the integral of the current injected into the loop filter through the corresponding DAC. Hence, the jitter noise of p(t) is added in the forward path and shaped by NTFCT(s) (relation (7)). rev is assumed as the standard deviation of edge’s jitter of p(t) in voltage per second. According to (3), its equivalent voltage noise referred to the quantizer input is rev/Ts. This error should be less than the upper limit of the quantization error introduced in (14), rev/ Ts B req. An upper limit is calculated for the jitter noise of pq[r], in the analysis of this section. 5.1 The jitter noise of conventional multi-bit DAC In conventional multi-bit RDMs, the current of feedback DAC is converted into the voltage by injecting the charge to the integrator feedback capacitor. Any deviation of the outermost DAC pulse duration from its nominal value leads to a voltage error added at the input of the modulator. This error is directly transferred to the modulator’s output, and hence, degrades the modulator’s performance. For a non-return-to-zero (NRZ) DAC, the error sequence can be represented by [27]: ej ½n ¼

b½n : ðb½n  b½n  1Þ Ts

ð15Þ

where b[n] is the digital output of the conventional modulator, b[n] is the time deviation of DAC pulse edge at the nth sample time. b[.] is assumed to be a Gaussian white stationary random process independent on b[.] with a PSD of r2b . The variance of e[n] for a modulator with an N-bit quantizer due to the clock jitter is given by:   n o r2b 2 r2b gVFS 2 2 2 rMB ¼ E ej ½n ¼ 2 rDb ¼ 2  ð16Þ Ts Ts 2N where E{.} is the mathematical expectation operator and rDb is the standard deviation of (b[n] - b[n - 1]). Without any loss of generality, it assumed that the mathematical expectation of (b[n] - b[n - 1]) is a coefficient of the quantizer’s LSB, g 9 VFS/2N. Considering (16) and only the jitter noise, the signal-to-noise ratio (SNR) of the multi-bit modulator for a sinusoidal input signal with amplitude A is given by: SNRMB;rb ¼

123

A2 =2 A2 Ts2 ð2N Þ2  OSR ¼  OSR 2 2 rMB 2r2b g2 VFS

ð17Þ

In the next sub-section, the clock jitter effect in the proposed modulator is analyzed for FIR-DACs (DAC1 and DAC2). It is assumed that the integrator’s dc gain prior to the other DACs, (DAC3, DAC4,…,DACL) can overcome their jitter error. In cases this assumption is not valid; they can be also replaced by FIR-DACs. Therefore, due to the fast time-domain signal processing, the jitter noise effects in DACL?1 and DACL?2 are investigated. 5.2 The jitter noise of FIR-DACs In modulator of Fig. 3, the clock jitter noise in the first loop DAC directly degrades the whole modulator’s performance. As will be shown here, by using the FIR-DAC, the immunity of the first loop against clock jitter is improved better than the clock jitter immunity of a conventional multi-bit DAC. As a result, by employing the same FIRDAC in the second loop, its clock jitter noise, which is also shaped by the preceding integrator, will be negligible. The time resolution of digital circuit and FIR-DACs are M times higher than the CT-RDM. Hence, the worst case assumption is that, during the modulator’s sampling period (Ts), the error due to the clock jitter is produced for M times. Assuming the TDC has the same quantization levels as the conventional multi-bit quantizer, M = 2N, it is shown in [18] that the variance of the jitter noise at the FIR-DAC output is as follows: r2PWM; OL 

M2 2 r 2 D2 MB

ð18Þ

where D is the tap number of a first-order sinc filter used in the outermost feedback path. Consequently, the SNR of the proposed modulator for a sinusoidal input signal with amplitude A, where only the jitter noise of the outer loop is considered, is given by:  2 A2 =2 D SNRPWM;rb ; OL ¼ 2 OSR ¼ 2   SNRMB;rb M rPWM; OL ð19Þ For D C M, the clock jitter immunity of the proposed modulator in the outer loop is surely more than that of the conventional multi-bit modulator. In the system design of this paper, D = M is employed (according to the relation (13)). It should be noted that using an M-level VCO-based quantizer, the clock jitter immunity of the modulator is similar to an M-level multi-bit modulator. However, a dynamic element matching (DEM) technique should be used to overcome the DAC nonlinearity problem [9, 10]. By employing an M-level TEQ quantizer, the modulator will be much more sensitive to the clock jitter compared to an M-level multi-bit modulator. In fact, the output signal of

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the proposed PWM quantizer has at most two changes during the modulator’s sampling time, while the TEQ quantizer has up to M changes during that time. Thereby, an M-tap FIR-DAC cannot reduce the clock jitter sensitivity of the modulator with a TEQ quantizer down to the M-level multi-bit modulator. However, like to the proposed modulator, the modulator with a TEQ quantizer has no DAC nonlinearity problem. 5.3 The jitter noise of quantizer and compensation loops

The jitter noises of DACL?1 and DACL?2 are shaped by the transfer function of:

As shown in Fig. 3, pq ½r  is fed back to the quantizer input through the compensation loop (DACLþ1 and gain of k*) and noise-coupling loop ðDACLþ2 and H1 ðsÞ ¼ 2  esTs Þ, respectively. The discrete-time equivalent of H1(s) at the sampling rate of the digital circuit ðM  fs Þ is 2  zM . The overall digital transfer function of pq ½r  to the quantizer input is Hd ðzÞ ¼ ð2 þ k ÞzM . During nth sample of the modulator, the overall error is the summation of M errors and it is given by: eqL ½n ¼

M 1 X k¼0

 b ½nM  k ð2 þ k ÞDdk;1 þ DdkþM;1 Ts ð20Þ

where Ddk;j ¼ pq ðnMkÞ pq ðnMjkÞ and bðnMkÞ is the time deviation of the DAC pulse edge at the ðnMkÞth DAC sample. By assuming that Ddk;1 and Ddk;M are uncorrelated and have the same variance, the variance of eqL ½n is obtained as: 1  n o  n o X r2b M ð2 þ k Þ2 þ 1 E Dy2d;1 r2qL ¼ E e2qL ½n ¼ 2 Ts k¼0   r2b r2Dd;1 ¼ ð2 þ k Þ2 þ 1  M Ts2

ð21Þ n o 2 where r2Dd;j ¼ E Ddk;j . In each modulator’s sample, pq ½r  has M pulse with amplitudes of -Vd, 0 or Vd ðVd ¼ VFS =2Þ. During each sample, the sign of pq ½r  does not change, and hence, pq ½r  has at most two changes with the amplitude of Vd. Without any loss of generality, it is assumed that in average, the difference of two adjacent pulses is a coefficient of the TDC’s quantization error, c  Ts =M (the TDC’s quantization-error is Ts/M). In other words, during Ts, in average, Ddk;1 is zero except for two time intervals with the length of c  Ts =M. Therefore, by using (3), r2Dd;1 can be expressed as: r2Dd;1

¼

2 EfDdk;1 g

2 ¼  Ts

Z  2 VFS V2 dt ¼ c FS 2 2M cTs M

For a course estimation of the jitter noise in the FIRDAC, the coefficient c is assumed equal to g2. In other words, it is assumed that in average, the difference of two adjacent pulses of PWM signal in the proposed modulator is equal to the difference of two adjacent samples of output signal in the conventional multi-bit modulator. Replacing (22) in (21), the jitter noise power is obtained as:   r2 g2 V 2 FS b r2qL ¼ ð2 þ k Þ2 þ 1  ð23Þ 2Ts2

ð22Þ

asL ðs=fs þ aÞðsL þ kL fs sL1 þ    þ k2 fsL1 s þ k1 fsL Þ  2  2L 1 2pf jCðf Þj2 ¼ ; if f  fs k1 fs

CðsÞ ¼

ð24Þ where for the sake of simplicity, the local feedback effect, n, is ignored in (24). The PSD of the jitter noise can be represented as 2r2qL/fs shaped by |C(f)|2. By integrating the jitter noise over the signal bandwidth, the inband jitter noise power is obtained as:   r2PWM; qL ¼ ð2 þ k Þ2 þ 1 

2 r2b g2 VFS

2Ts2 k12

:

p2L ð2L þ 1Þ OSR2Lþ1

ð25Þ

The SNR of the proposed modulator for a sinusoidal input signal with amplitude A, where only the jitter noise of relation (25) is considered, is equal to: SNRrb; qL ¼ ¼

A2 =2 r2PWM; qL A2 Ts2 2 r2b g2 VFS

¼2 

ð2L þ 1Þ k12 OSR2Lþ1  :  ð2 þ k Þ2 þ 1  p2L

ð2L þ 1Þ k12 OSR2L  SNRMB;rb ð2 þ k Þ2 þ 1  p2L 22N ð26Þ

In modulator of Fig. 3 with L = 3, k* = 1 and OSR = 8, according to (26), SNRrb,qL is 8.7 dB less than SNRMB,rb. By considering the local feedback effect, n, SNRrb,qL improves about (L-0.5)2 = 8 dB, and hence, it has approximately the same value as SNRMB,rb. In order to confirm the analytical results of this section, system level simulations were performed. Figure 11 shows the SNR versus the clock jitter in three cases: outer loop FIR-DAC (DAC1) jitter noise, the inner loops overall jitter effect in the proposed modulator (DACL?1 and DACL?2), and the outer loop DAC jitter in the conventional multi-bit modulator of Fig. 1. In all cases, L = 3, OSR = 8 and a

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Analog Integr Circ Sig Process (2014) 78:439–452 80 75

SNDR (dB)

70 N=4 OSR = 8 M = 16

65 60 55 50 45

Outer loop Inner loops Multi-bit -4

10

-3

10

-2

10

Jitter deviation related to Ts

Fig. 11 SNR versus the standard deviation of jitter noise in three different cases: multi-bit modulator, outer loop (DAC1) and inner loops (DACL?1 and DACL?2) in the proposed modulator

-4.4 dBFS sinusoidal input signal at the frequency of fs/ 512 was employed. Both quantizers of aforementioned modulators, (voltage-mode and time-mode) have 16 levels (N = 4, M = 16). Dashed line curves are corresponding to the system level simulations in three mentioned cases where the jitter noise is modeled according to (15). The solid lines are analytical results calculated from (17), (19) and (26) for the outer loop of conventional multi-bit modulator, outer loop and two inner loops of the proposed modulator, respectively. As illustrated in Fig. 11, there is a good accuracy between the analytical and simulation results where the clock jitter is the dominant noise source. According to both analytical and simulation results, the outer loop DACs in the proposed modulator have better immunity against clock jitter compared to the multi-bit DAC. Two inner loops (DACL?1 and DACL?2) have approximately the same clock jitter immunity as the multi-bit DAC. Therefore, the clock jitter insensitivity of the proposed modulator is approximately the same as the multi-bit conventional modulator.

6 Comparison with the conventional multi-bit RDMs As shown in relation (11), the noise-shaping order of the proposed modulator with the time-based noise-coupling quantizer is two times higher than its number of integrators, while in the conventional multi-bit modulators, the number of integrators and the noise-shaping order are usually equal. Due to analog elements mismatch, the voltage-mode noise-coupling in conventional RDMs (error feedback structure) may have practical limitations, especially for the orders higher than one [12, 15]. In the

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proposed modulator, the conventional voltage-mode quantizer is replaced by the time-mode PWM-based one which is more compatible with the recent nano-meter CMOS technologies. The output signal of both proposed and conventional modulators are M-level signals at the rate of fs. This means that both modulators require the same decimation filters. Although the time resolution of digital circuit in Fig. 3 is higher than the time resolution of other parts of the modulator, but independent on the value of M, pq[r] has a maximum of two changes in every sampling period, Ts. Furthermore, all elements of FIR-DAC are excited by the delay versions of pq[r]. Therefore, the speed requirement of the FIR DAC unit elements is not more than that is needed in a multi-bit return-to-zero DAC in the conventional modulator clocked at the rate of fs [18]. Also, according to the simulation results, the proposed modulator amplifiers require approximately the same analog specifications as the conventional multi-bit modulator. The proposed modulator has approximately the same clock jitter immunity as the multi-bit modulator. All feedback DACs of a multi-bit modulator require M = 2N unit elements. In contrast, in the proposed modulator, the first and second FIR-DACs require M = 2N unit elements, the (L ? 2)th DAC is 7-level and other DACs have 3-level. A serious problem of the multi-bit modulator is the outer loop DAC nonlinearity which degrades the whole modulator performance. For moderate and high values of OSR, the dynamic element matching (DEM) techniques can alleviate this problem [28]. However, in low OSRs, the DEM may be insufficient. Besides, the DEM techniques such as the data-weighted-averaging (DWA) are unsuitable for CT-RDMs with multi-bit NRZ DACs [29]. In contrast, the proposed modulator with the three-level PWM feedback signal has no nonlinearity problem [18]. The digital circuit of the proposed modulator comprises of a 1-bit signed adder to extract e(t), a 3-bit signed adder to calculate w(t), one asynchronous delay element in H1(s), M-1 delay elements for the delay line employed in FIR-DACs (only one delay line is required for both FIR-DACs). On the other hand, in conventional multi-bit modulators, a DEM technique must be used to overcome the DAC nonlinearity. Only for the sake of comparison, the hardware of DWA algorithm as one of the simplest DEM techniques is considered here. The DWA technique requires an N-bit adder, an N-bit register, a randomizer, and a logic block to implement the barrel shifter. Considering the fabricated modulator reported in [2], a course estimation of the overall figure of merit (FoM) may be achieved for the modulator with the proposed quantizer. The third order CT-RDM of [2] employs a TW-PWM and a

Analog Integr Circ Sig Process (2014) 78:439–452

50-level TDC. This 50-level TDC has 4-bit effective resolution and consumes 5.66 mW at 250 MHz sampling frequency. The whole power consumption of the modulator is 10.5 mW from a 1.2 V power supply at 250 MHz sampling frequency. This modulator achieves 60 dB SNDR in a 20 MHz bandwidth (OSR = 6). According to the explanation of Sect. 2.1, the proposed quantizer, which employs DR-PWM, requires much less TDC quantization levels for the same accuracy (i.e. 16-level for 4-bit resolution). On the other hand, the proposed quantizer has a digital noise-coupling path employing a 1-bit signed adder, a 3-bit signed adder and one asynchronous delay element. As predicted by relation (11), the proposed noise-coupling PWM quantizer enhances the modulator’s performance by amount of (2(L ? Ld) ? 1) 9 (OSR/p)2Ld/(2L ? 1) = 20.9 (L = 3, OSR = 6, Ld = 2). The second-order noise-coupling multiplies the out-band gain of NTF (NTF(z = -1)) by 4. To preserve the modulator stability, the NTF should be scaled down accordingly. As a worst case condition, it is assumed that this scaling is done by the outer feedback gain (k1). This assumption reduces the modulator’s performance enhancement to 20.9/4 = 5.22. Therefore, if the proposed noisecoupling quantizer is used in the modulator of [2], the modulator’s FoM (= Power/(2 9 BW 9 2B) = 319 fJ/ Step) may be improved to 61 fJ/Step. As another comparison reference, we may consider the results of [30]. The fifth-order CT-RDM of [30] employs both a 3-bit flash ADC and a digital level-to-PWM generator to prepare the PWM feedback signal. The whole power consumption of the modulator is 44.8 mW from a 1.8 V power supply at 400 MHz sampling frequency. The modulator provides 67.7 dB SNDR in a 25 MHz bandwidth (OSR = 8). For the sake of comparison, the proposed modulator can achieve the same fifth-order noiseshaping, while it employs only three integrators. Besides, in the proposed modulator, the flash ADC is not employed. On the other hand, the proposed modulator requires an analog voltage-to-PWM generator. As a course estimation, it is assumed that both modulators require the same digital circuit. Besides, the power consumption of [30] could be reduced by a factor of 0.667 (= 1.2/1.8), if the power supply is reduced from 1.8 to 1.2 V. In other words, the FoM (= Power/(2 9 BW 9 2B) = 484 fJ/Step) of [30] might be improved to 322.67 fJ/Step (= 484 9 0.667), if the power supply voltage is reduced to 1.2 V. Furthermore, the nonlinearity problem of the PWM generator in the feedback path limits the maximum SNDR in [30], while in the proposed modulator, the nonlinearity problem of the PWM generator is eliminated by using the DR-PWM and benefiting the loop filter shaping. Therefore, the SNDR of the proposed modulator may be improved up to 76 dB (Fig. 8). Considering the aforementioned power reduction and the SNDR improvement, if the proposed noise-

451

coupling quantizer is used in the modulator of [30], the modulator’s FoM may be improved to 124.86 fJ/Step (= 322.67 9 210.97/212). Besides, by replacing two analog integrators and a 3-bit flash ADC of [30] by a voltage-toPWM generator, the power consumption of [30] may be reduced further.

7 Conclusions A time-based noise-coupling scheme benefiting from both the digital signal processing and noise-shaping capabilities was proposed. This technique with a second-order noiseshaping was used in CT-RDMs. This proposed modulator has at least three advantages over the corresponding CTRDMs. Firstly, by replacing the voltage-based quantizer with a time-based one, it is more compatible with the technology scaling. The NTF of CT-RDM is multiplied by the noise-coupling NTF providing one or two higher order noise-shaping without any change in the modulator’s STF. Finally, it employs a three-level PWM signal to drive the outermost feedback DAC without any nonlinearity problem. Furthermore, the proposed modulator approximately preserves the clock jitter immunity of the conventional multi-bit modulators.

References 1. Tsividis, Y. (2003). Continuous-time digital signal processing. Electronics Letters, 39(21), 1551–1552. 2. Dhanasekaran, V., Gambhir, M., Elsayed, M. M., Sa´nchezSinencio, E., Silva-Martinez, J., Mishra, C., et al. (2011). A continuous time multi-bit RD ADC using time domain quantizer and feedback elements. IEEE Journal of Solid-State Circuits, 46(3), 639–650. 3. Elsayed, M. M., Dhanasekaran, V., Gambhir, M., Silva-Martinez, J., & Sanchez-Sinencio, E. (2011). A 0.8 ps DNL time-to-digital converter with 250 MHz event rate in 65 nm CMOS for timemode-based RD modulator. IEEE Journal of Solid-State Circuits, 46(9), 2084–2095. 4. Prefasi, E., Pato´n, S., & Hernandez, L. (2011). A 7 mW 20 MHz BW time-encoding oversampling converter implemented in a 0.08 mm 65 nm CMOS Circuit. IEEE Journal of Solid-State Circuits, 46(7), 1562–1574. 5. Colodro, F., Torralba, A., & Laguna, M. (2008). Continuous-time sigma-delta modulator with an embedded pulse width modulation. IEEE Transactions on Circuits and Systems I, 55(3), 775–785. 6. Vuyst, B. D., & Rombouts, P. (2011). A 5-MHz 11-bit selfoscillating RD modulator with a delay-based phase shifter in 0.025 mm2. IEEE Journal of Solid-State Circuits, 46(8), 1919–1927. 7. Woestyn, P., Rombouts, P., Xing, X., & Gielen, G. (2012). A selectable-bandwidth 3.5 mW. 0.03 mm2, self-oscillating sigma delta modulator with 71 dB dynamic rang at 5 MHz and 65 dB at 10 MHz bandwidth. Analog Integrated Circuits and Signal Processing, 72, 55–63.

123

452 8. Straayer, M. Z., & Perrott, M. H. (2008). 12-Bit, 10-MHz bandwidth, continuous-time RD ADC with a 5-bit, 950-MS/s VCO-based quantizer. IEEE Journal of Solid-State Circuits, 43(4), 805–814. 9. Park, M., & Perrott, M. H. (2009). A 78 dB SNDR 87 mW 20 MHz bandwidth continuous-time RD ADC with VCO-based integrator and quantizer implemented in 0.13 lm CMOS. IEEE Journal of Solid-State Circuits, 44(12), 3344–3358. 10. Reddy, K., et al. (2012). A 16-mW 78-dB SNDR 10-MHz BW CT ADC using residue-cancelling VCO-based quantizer. IEEE Journal of Solid-State Circuits, 47(12), 2916–2927. 11. Yu, W., Kim, J., Kim, K., & Cho, S.-H. (2013). A time-domain high-order MASH RD-ADC using voltage-controlled gated-ring oscillator. IEEE Transactions on Circuits and Systems I, 60(4), 856–866. 12. Schreier, R., & Temes, G. C. (2005). Understanding delta-sigma data converters. Hoboken, NJ: Wiley/IEEE Press. 13. Lee, K., & Temes, G. C. (2008). Enhanced split-architecture delta-sigma ADCs. Analog Integrated Circuits and Signal Processing, 56, 157–251. 14. Wang, Y., & Temes, G. C. (2009). Noise-coupled continuous time delta sigma ADCs. Electronics Letters, 45(6), 302–303. 15. Ali, F., & Hamoui, A. A. (2008). Continuous-time RD modulators with noise-transfer-function enhancement. In Proceedings of IEEE international symposium on Circuits and Systems (pp. 1428–1431), May 2008. 16. Lee, K., Chae, J., Aniya, M., Hamashita, K., Takasuka, K., Takeuchi, S., et al. (2008). A noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, 98 dB THD, and 79 dB SNDR. IEEE Journal of Solid-State Circuits, 43(12), 2601–2612. 17. Wang, Y., Hanumolu, P. K., & Temes, G. C. (2011). Design techniques for wideband discrete-time delta-sigma ADCs with extra loop delay. IEEE Transactions on Circuits and Systems I, 58(7), 1518–1530. 18. Colodro, F., & Torralba, A. (2009). New continuous-time multibit sigma–delta modulators with low sensitivity to clock jitter. IEEE Transactions on Circuits and Systems I, 56(1), 74–83. 19. Su, D. K., & Wooley, B. A. (1993). A CMOS oversampling D/A converter with a current-mode semi-digital reconstruction filter. IEEE Journal of Solid-State Circuits, 28(12), 1224–1233. 20. Schell, B., & Tsividis, Y. (2008). A low power tunable delay element suitable for asynchronous delays of burst information. IEEE Journal of Solid-State Circuits, 43(5), 1227–1234. 21. Kim, G. (1996). A low-voltage, low-power CMOS delay element. IEEE Journal of Solid-State Circuits, 31(7), 966–971. 22. Ortmanns, M., & Gerfers, F. (2005). Continuous-time sigma-delta A/D conversion. Berlin: Springer. 23. Mitteregger, G., Ebner, C., Mechnig, S., Blon, T., Holuigue, C., & Romani, E. (2006). A 20-mW 640-MHz CMOS continuoustime ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB. IEEE Journal of Solid-State Circuits, 41(12), 2641–2649. 24. Kenney, J. G., & Carley, L. R. (1988). CLANS: A high-level synthesis tool for high resolution data converters. In ICCAD Dig. Tech. Papers, Nov. 1988, pp. 496–499. 25. Hamoui, A. A., & Martin, K. W. (2004). High-order multi-bit modulators and pseudo data-weighted-averaging in low-oversampling RD ADCs for broad-band applications. IEEE Transactions on Circuits and Systems I, 51(1), 72–85. 26. Hanafi Alamdari, H., El-Sankary, K., & El-Masry, E. (2009). Excess loop delay compensation for continuous-time RD modulators using interpolation. Electronics Letters, 45(12), 609–610.

123

Analog Integr Circ Sig Process (2014) 78:439–452 27. Cherry, J. A., & Snelgrove, W. M. (1999). Clock jitter and quantizer metastability in continuous-time delta-sigma modulators. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 46(6), 661–676. 28. Barid, R. T., & Fiez, T. S. (1995). Linearity enhancement of multibit RD A/D and D/A converters using data weighted averaging. IEEE Transactions on Circuits and Systems II, 42(12), 753–762. 29. Risbo, L., Hezar, R., Kelleci, B., Kiper, H., & Fares, M. (2011). Digital approaches to ISI-Mitigation in high-resolution oversampled multi-level D/A converters. IEEE Journal of Solid-State Circuits, 46(12), 2892–2903. 30. Lu, C.-Y., Onabajo, M., Gadde, V., Lo, Y. C., Chen, H.-P., Periasamy, V., et al. (2010). A 25 MHz bandwidth 5th-order continuous-time low-pass sigma-delta modulator with 67.7 dB SNDR using time-domain quantization and feedback. IEEE Journal of Solid-State Circuits, 45(9), 1795–1808.

Hossein Pakniat was born in Iran. He received the B.Sc. and M.Sc. degrees in electrical engineering from the University of Shiraz, and Amirkabir University of Technology, Tehran, Iran, in 2007 and 2009, respectively. He is currently working toward the Ph.D. degree at the Amirkabir University of Technology. His research interests include integrated circuit design and sigma-delta ADCs.

Mohammad Yavari received the B.Sc., M.Sc., and Ph.D. degrees in electrical engineering from the University of Tehran, Tehran, Iran, in 1999, 2001, and 2006, respectively. He has been an Assistant Professor with the Department of Electrical Engineering, Amirkabir University of Technology (Tehran Polytechnic), Tehran, since 2006, where he founded the Integrated Circuits Design Laboratory, in 2007. He spent several research periods with the Institute of Microelectronics of Seville (IMSE-CNM), Seville, Spain. He was with Niktek, from May 2004 to April 2005 and October 2006 to May 2007, as a Principal Design Engineer, where he was involved in the design of high-resolution A/D and D/A converters for professional digital audio applications. He is the author or co-author of more than 100 peer-reviewed papers in international and national journals and conference proceedings on analog integrated circuits. His current research interests include analog and mixed-signal integrated circuits and signal processing, data converters, and CMOS RFIC design for wireless communications. Dr. Yavari was a recipient of the Best Student Research Award of the University of Tehran in 2004.