Analog Integr Circ Sig Process (2009) 61:271–278 DOI 10.1007/s10470-009-9309-7
An efficient power reduction technique for CMOS flash analog-to-digital converters Yuh-Shyan Hwang Æ Po-Hsiang Huang Æ Bo-Han Hwang Æ Jiann-Jong Chen
Received: 8 January 2008 / Revised: 1 March 2009 / Accepted: 4 April 2009 / Published online: 22 April 2009 Ó Springer Science+Business Media, LLC 2009
Abstract An efficient power reduction technique for CMOS flash analog-to-digital converter (ADC) is presented. The presented technique adopts the procedure with a simple coarse comparison first followed by a finer comparison later. Our ADC design does not decrease the total number of comparators, though it is able to reduce the power consumption. Subject to time signal controlling, the manipulation is to interchangeably shut down the comparator sections for the coarse comparison function. Experimental results show that this new method consumes about 48.14 mW at 400 MHz with 3.3 V supply voltage in TSMC 0.35 lm 2P4 M process. Compared with the traditional flash ADC, our low power method can reduce up to 47.8% in power consumption. The DNL of our proposed flash ADC is 0.5 LSB, the INL is 0.7 LSB, and the ENOB is 5.75 bits. The chip area occupies 0.4 9 0.9 mm2 without I/O pads. Keywords Flash ADC Analog-to-digital converter Power reduction
1 Introduction Mixed-signal integrated circuits have a tendency in the design of system-on-chip (SOC) in recent years. Digital receivers for high-bit-rate communications are spurring on the conversion rate of analog-to-digital converter (ADC). The ADC plays an important role between analog and digital signals. Because the flash ADC is a simple and Y.-S. Hwang (&) P.-H. Huang B.-H. Hwang J.-J. Chen Department of Electronic Engineering, National Taipei University of Technology, Taipei 106, Taiwan, ROC e-mail:
[email protected]
parallel architecture, it has the advantage with very high sampling frequency and high conversion data rate, but it has the disadvantage with very large chip area, low resolution and high power consumption [1–3]. In the traditional flash ADC architecture, it uses 2n resistors and 2n-1 comparators to convert an n-bit data. Figure 1 shows an example of a traditional flash ADC architecture and all 2n-1 comparators are working in every clock cycle [4]. That will cause high power consumption. To save the power consumption, a quite amount of power reduction techniques have been published for flash ADC, such as folding and interpolating [5], pipelined look-ahead architecture [6], distortion correction [7] and so on [8–10]. The authors have also proposed a bisection method to reduce the number of comparators working in every clock cycle [11], to avoid the unnecessary power consumption. In this paper, as an example of 6-bit flash ADC, we use three extra comparators in our design to divide the next stage into four sections and control timing signals that determine which sections of the 63 original comparators to activate. Within a timing period, only two sections of the comparators are allowed to operate, which achieve the aim of the low power consumption. In the paper, Sect. II describes the building blocks of the flash ADC. Our proposed technique and circuit are examined in Sect. III. In Sect. IV, the simulation and experimental results are demonstrated. Finally, the conclusion is provided in Sect. V.
2 Basic building blocks As we know, the comparator plays a very important role in the flash ADC. To overcome the high power consumption of the traditional flash ADC and modify the method presented in [11], we use the modified comparators shown in
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Analog Integr Circ Sig Process (2009) 61:271–278 VIN
VREF MSB
Encoder
Fig. 3 Thermometer codes
LSB
Fig. 1 A traditional flash ADC architecture
Fig. 4 Digital correction building block
Fig. 2 for reducing the power consumption [4]. The comparator is composed of a power switch transistor (M11), a positive-feedback latch circuit (M1 * M4), resetting transistors (M5 * M6), input transistors (M7 * M8), and current cutting transistors (M9 * M10) with feedback inverters (Inv1 * Inv2). When the clock is high, entire comparator is in resetting mode. Vout? and Vout- are pulled down to ground. When the clock is low, we assume that Vin [ Vref, the resistor of transistor M7 is smaller than M8, the voltage of positive-feedback latch circuit (M1 * M2) Clk
M11
Vout-
is smaller than (M3 * M4) at this time. By latching, we can obtain Vout? is high and Vout- is low. In the flash ADC, the comparators generate an output pattern consisting of a series of zero or one bits called the thermometer codes shown in Fig. 3. Figure 4 shows the digital correction building block including both the bubble error corrector and the encoder. Due to CMOS process variation and threshold voltage influence, the generated thermometer codes may have possible bubble errors which are subsequently detected and corrected by the bubble error corrector. The following encoder can generate the digital binary outputs.
Vout+
3 Proposed technique and circuit M1
M3 Inv2
Inv1 Vin
M7
M8 M2
M9
M5
M4 M6
Fig. 2 Low power comparator in proposed ADC
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M10
Vref
In order to reduce the power dissipation of the conventional flash ADC, one can try to reduce the power consumption of comparators [4] or using fewer number of comparators operated in every clock cycle [11]. We propose a new power reduction technique to modify the traditional flash ADC. Figure 5 shows the modified low power 6-bit flash ADC. Using the proposed method to detect where the input signal intervenes, and let the selected region work. It is like when we read the degrees of the thermometer, we only care about
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the level of the mercury. We use three extra comparators in our design to divide the next stage into four sections; meanwhile, the time signal controlling is given to decide which comparator sections shall proceed or cease. To verify our idea, we divide 63 original comparators (C1–C63) into four sections (S1–S4). From the first section S1 to the fourth section S4, they individually include C1–C16, C17–C32, C33–C48, and C49–C63, respectively. In each clock cycle, only two sections of the comparators are allowed to operate. We achieve the aim of the low power consumption since only a half of number of the comparators in this flash ADC are working in every clock cycle. For deciding the region of voltage for input signal and generating the control signals, we use three extra comparators to detect where the input signal voltage intervenes. The three extra comparators generate four control signals also shown in Fig. 5. The first section is controlled using the negative output of the bottom one of the three extra comparators in Fig. 5. The negative and positive outputs of the middle one are connected to the second and third sections to control comparators C17 * C32 and C33 * C48, respectively. The fourth section is controlled by the positive output of the up comparator. The operating principle of the modified low power 6-bit flash ADC is depicted in Figs. 6, 7, 8 which are telling when the different sections are working. The proposed ADC architecture can be only effective when there is meta-stability in the ‘‘fine’’ comparators instead of in ‘‘coarse’’ comparators. To reduce the meta-stability error of the comparator, two sections must be operated at the same time. When the first and second sections work, the others cease, as shown in Fig. 6. Figure 7 shows the second and third sections working
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Fig. 6 A modified low power 6-bit flash ADC (First and second sections work)
Fig. 7 A modified low power 6-bit flash ADC (Second and third sections work)
Fig. 5 A modified low power 6-bit flash ADC
situation. It is similar to Fig. 8 when the third and fourth sections work. Therefore, we can reduce the unnecessary power consumption. Moreover, based on the architecture of our proposed ADC, the averaging method of reducing the offset voltage of comparators cannot be employed. In order to lower the effects of mismatch of devices and the offset voltage of comparators, we use the pre-simulation to
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Fig. 8 A modified low power 6-bit flash ADC (Third and fourth sections work)
predict the offset voltage and choose the relatively larger sizes of devices although the power consumption will increase slightly.
4 Simulation and experimental results Figures 9, 10 show the HSPICE simulation results of the comparator circuit and our proposed 6-bit flash ADC in TSMC 0.35 lm 2P4 M technology. The simulations are based on the same condition, i.e., the input sine-wave Fig. 9 The simulation result of the comparator
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signal is operated at 10 MHz along with Vp-p = 2 V, the reference voltage Vref = 1.1 V, sampling clock rate at 400 MHz, and power supply on 3.3 V. We also simulate the higher sampling frequency of 600 MHz of proposed ADC. The result is shown in Fig. 11. The aim of the paper is proposed for a new power reduction method. Because the comparator in Fig. 2 used in the paper is based on 0.35 lm process and reference [4], it is special for low power techniques and not for high speed applications. Moreover, the additional parasitic capacitances placed on the resistor chain have an effect on the limitation of a maximum operating frequency. We have also simulated the input analog frequency of 100 MHz at a sampling frequency of 400 MHz. The simulation result is shown in Fig. 12. When the input frequency is operated in 200 MHz, the missing codes would be happened for the speed limitation of used comparator. The power dissipation will be grown when the operating speed of the proposed flash ADC is increasing. So the power and performance of proposed circuit should be trade-off. To make sure our proposed method can reduce power consumption, we simulate the traditional 6-bit flash ADC, the bisection method [11] and our proposed circuit with HSPICE in TSMC 0.35 lm technology. The power consumptions are 92.28, 61.52, and 48.14 mW from the traditional ADC, bisection method and our proposed ADC, respectively. The power saving is up to 47.8 and 21.7% compared to traditional method and bisection method, respectively. We have implemented and tested the modified low power 6-bit flash ADC in TSMC 0.35 lm 2P4 M technology. Measurement conditions are the same as simulation. The measurement results for differential nonlinearity (DNL) and integral non-linearity (INL) of our proposed
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Fig. 10 The simulation result of ADC with 10 MHz input at 400 MHz sampling
Fig. 11 The simulation result of ADC with 10 MHz input at 600 MHz sampling
flash ADC are shown in Figs. 13, 14, respectively. The DNL of our proposed flash ADC is 0.5 LSB, and the INL is 0.7 LSB. The linearity is controlled within ±1 LSB because of well design. The DNL and INL in the sampling frequency over 600 MHz are larger than 1 LSB, so the missing codes would be happened for the speed limitation of used comparator. The dynamic linearity of the flash ADC is analyzed by the fast Fourier transform (FFT). Figure 15 shows the FFT plot with 10 MHz sine-wave input sampled at 400 MHz conversion rate. The signal to
noise and distortion ratio (SNDR) is 36.4 dB and the effective number of bit (ENOB) is 5.75-bit at input frequency 10 MHz. The chip power consumption of experimental result is 49.56 mW, which is very close to the simulation results. This result shows the advantage of our proposed method in reducing power consumption. Figure 16 shows a microphotograph of our proposed flash ADC. The chip area occupies 0.4 9 0.9 mm2 without I/O pads. Table 1 shows the comparison of specifications of proposed flash ADC and previous works.
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Fig. 12 The simulation result of ADC with 2000 MHz input at 400 MHz sampling
Fig. 13 The DNL of proposed 6-bit flash ADC
Fig. 15 The FFT plot of proposed 6-bit flash ADC
Fig. 14 The INL of proposed 6-bit flash ADC
5 Conclusions This paper has proposed an approach to reduce the power consumption of flash ADC, by using a low-power comparator and estimating rough voltage level with extra comparators, and turning off comparators not in need. An example of 6-bit flash ADC is given, in which we use three extra comparators to divide next stage into four sections. The four sections with 63 original comparators are subject to a time signal controlling to decide themselves when to proceed or cease. With a timing control, only two sections of the comparators are allowed to operate, so as to achieve the deduction of power consumption. Compared with a
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Fig. 16 Microphotograph of proposed 6-bit flash ADC
traditional flash ADC, it can save the power consumption about 47.8%, and reduce power dissipation of the bisection method about 21.7%, respectively. The DNL of our
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Table 1 Comparison of specifications of three flash ADCs Output result
Traditional method Simulation
[8] Measured
[9] Simulation
[10] Measured
[11] Simulation
Proposed method Measured
Technology
0.35 lm
0.12 lm
0.18 lm
2 lm
0.35 lm
0.35 lm
Architecture
Flash
Flash
Flash
Flash
Flash
Flash
Power supply
3.3 V
1.2 V
N.A
5V
3.3 V
3.3 V
Resolution
6-bit
6-bit
6-bit
6-bit
6-bit
6-bit
Sampling frequency
400 MHz
260 MHz
2.22 GHz
100 MHz
400 MHz
400 MHz
Power consumption
92.28 mW
32 mW
120.29 mW
0.4 mW
61.52 mW
48.14 mW
DNL (LSB)
0.3
0.2
0.0037
0.65
0.5
0.5
INL (LSB)
0.3
0.4
0.0025
0.34
0.6
0.7
SNDR
37.1 dB
N.A
N.A
N.A
36.8 dB
36.4 dB
ENOB
5.87-bit
5.3-bit
N.A
N.A
5.82-bit
Chip area without I/O pads
2
0.5 9 0.7 mm
N.A.
proposed flash ADC is 0.5 LSB, the INL is 0.7 LSB, and the SNDR is 36.4 dB, the ENOB is 5.75-bit. The chip area occupies 0.4 9 0.9 mm2 without I/O pads. These results approve the proposed power reduction technique has achieved on the saving of the power consumption for a CMOS flash ADC effectively.
2
0.34 9 0.63 mm
7.
8.
Acknowledgments The authors would like to thank the reviewers for their valuable suggestions. The authors would also like to thank the Chip Implementation Center of Taiwan for the technical supporting and IC implementation. This work was supported by the National Science Council of Taiwan under Grant NSC 96-2221-E027-130.
10.
References
11.
1. Choi, M., & Abidi, A. A. (2001). A 6-b 1.3-Gsample/s A/D converter in 0.35-lm CMOS. IEEE Journal of Solid-State Circuits, 36(12), 1847–1858. doi:10.1109/4.972135. 2. Scholtens, P. C. S., & Vertregt, M. (2002). A 6-b 1.6-Gsample/s flash ADC in 0.18 lm CMOS using averaging termination. IEEE Journal of Solid-State Circuits, 37(12), 1599–1609. doi:10.1109/ JSSC.2002.804334. 3. Uyttenhove, K., & Steyaert, M. S. J. (2003). A 1.8-V 6-bit 1.3GHz flash ADC in 0.25 lm CMOS. IEEE Journal of Solid-State Circuits, 38(7), 1115–1122. doi:10.1109/JSSC.2003.813244. 4. Terada, J., Matsuya, Y., Morisawa, F., & Kado, Y. (2000). 8-mW, 1-V, 100-MSPS, 6-bit A/D converter using a transconductance latched comparator. In: IEEE Asia Pacific conference on ASIC (pp. 53–56). 5. Kim, S., & Song, M. (2001). An 8-bit 200MSPS CMOS A/D converter for analog interface module of TFT-LCD driver. In: IEEE international symposium on circuits and systems (pp. 528– 531). 6. Hotta, M. & Matsuura, T. (2006). Key technologies for miniaturization and power reduction of analog-to-digital converters for
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0.4 9 0.9 mm2
video use. In: IEICE transactions on electronics (Vol. E89-C, No. 6, pp. 664–672). Srinivas, V., Pavan, S., Lachhwani, A., & Sasidhar, N. (2006). A distortion compensating flash analog-to-digital conversion technique. IEEE Journal of Solid-State Circuits, 41(9), 1959–1969. doi:10.1109/JSSC.2006.880601. Scholtens, P. C. S., Smola, D., & Vertragt, M. (2005). Systematic power reduction and performance analysis of mismatch limited ADC designs. In: International symposium on low power electronics and design (pp. 78–83). Yoo, J., Lee, D., Choi, K., & Kim, J. (2002). A power and resolution adaptive flash analog-to-digital converter. In: International symposium on low power electronics and design (pp. 233– 236). Tangel, A., & Choi, K. (2004). The CMOS inverter as a comparator in ADC designs. Analog Integrated Circuits and Signal Processing, 39(2), 147–155. doi:10.1023/B:ALOG.00000 24062.35941.23. Tsai, C. C., Hong, K. W., Hwang, Y. S., Lee, W. T., & Lee, T. Y. (2004). New power saving design method for CMOS flash ADC. In: IEEE international midwest symposium on circuits and systems (pp. III-371–III-374).
Yuh-Shyan Hwang was born in Taipei, Taiwan, in 1966. He received the Ph.D. degree in the Department of Electrical Engineering from National Taiwan University, Taipei, Taiwan, in 1996. He is now an associate professor in the Department of Electronic Engineering and Institute of Computer and Communication, National Taipei University of Technology, Taiwan. His current research interests include analog integrated circuit design, mixedsignal integrated circuit design, power electronics integrated circuit design, electronic circuit design, and analog signal processing.
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Analog Integr Circ Sig Process (2009) 61:271–278 Po-Hsiang Huang received the bachelor degree in the Department of Electronic Engineering, National Taipei University of Technology, Taiwan, in 2008. His research interests include analog-to-digital converters and analog integrated circuit.
Bo-Han Hwang received the bachelor degree in the Department of Electronic Engineering, National Taipei University of Technology, Taiwan, in 2007. He is currently toward the Ph.D. in the Institute of Computer and Communication, National Taipei University of Technology, Taiwan. His research interests include mixed-signal and power integrated circuits.
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Jiann-Jong Chen was born in Keelong, Taiwan, in 1966. He received the M.S. and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1992 and 1995, respectively. From 1994 to 2004, he was on the faculty of Lunghwa University of Science and Technology, Taiwan. Since August 2004, he has been with the Department of Electronic Engineering, National Taipei University of Technology, Taiwan, where he is now an Associate Professor. His research interests are in the area of mixed-signal integrated circuits and systems for power management.
