Analog Integrated Circuits and Signal Processing, 46, 7–15, 2006 c 2005 Springer Science + Business Media, Inc. Manufactured in The Netherlands.
An Implantable CMOS Front-End System for Nerve-Signal Sensors
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JANNIK HAMMEL NIELSEN AND ERIK BRUUN Ørsted
DTU, Technical University of Denmark, DK-2800 Kgs. Lyngby, Denmark E-mail:
[email protected]
Received February 15, 2005; Revised May 17, 2005; Accepted May 24, 2005
Abstract. An analog front-end dedicated to processing of cuff-recorded human nerve signals is presented in this paper. The system is comprised of a low-noise preamplifier and an A/D converter (ADC) for quantizing the recorded nerve signal. The instrumentation amplifier utilizes CMOS transistors biased in the weak/moderate inversion region at a relatively high current for low thermal noise performance and achieves low flicker noise performance through √ chopper stabilization. The resulting measured equivalent input referred thermal noise is 6.6 nV/ Hz at a chopping frequency of 20 kHz. A two-stage design is implemented which achieves a measured amplification of 72.5 dB over a signal bandwidth of 4 kHz. For the ADC, a third order -modulator employing a continuous-time (CT) loopfilter was implemented. Each of the integrators in the loop-filter are implemented as G m − C elements. For a sampling frequency of 1.4 MHz, the measured SNDR for the ADC is 62 dB, whereas the dynamic range (DR) is 67 dB over a 4 kHz bandwidth, equivalent to a resolution of 10 bits. The system draws a current of 196 µA from a 1.8 V supply thus consuming approximately 350 µW excluding buffers and bias circuitry. Key Words:
1.
biomedical circuits, implantable microsystem, low-power, low-voltage, neural sensor
Introduction
As the median age of western society population continues to grow, an increase in age- and life-style related chronic illness is observed. A projected major growth area for the integrated circuit business, is hence in the field of biomedical devices applicable for alleviating the effects of various afflictions, e.g., systems for automatic prosthetic device control, artifical retinas for rudimentary vision recovery etc. Classical electronic biomedical devices such as hearing aids and pacemakers can be mentioned. As an appreciable percentage of the population suffer from disability due to paralysis, the nature of peripheral nerve signals (electroneurogram ENG) has constituted a major study field in order to apprehend the underlying mechanisms in humans for body limb control and the feedback mechanisms present for accurate muscle force regulation. The comprehension of human nerve signals has matured to the point where electronic generation of artifical ENG through functional electrical stimulation (FES) for muscle control, in response to evoked nerve signals is now achievable. Prototype de-
vices intended for the correction of foot-drop [1] and for restoration of basic hand grasp using force feedback control [2] has been developed and demonstrated to be functional. In both the aforementioned systems, a cuff-electrode is mounted around a nerve trunk and is employed for both nerve signal sensing and for FES, i.e., conveying the artifically generated electronic ENG to the nerve. The prototype systems involves the use of numerous discrete devices external to the body, e.g., preamplifiers, filters and signal processors for analysis of the recorded ENG. Interfacing with the implanted sensor is done via wiring through a chronic incision. Our involvement comes from the development of integrated circuits which incorporate all the functions performed by the discrete prototype and which are suitable for chronic implantation. Numerous challenges are evident from the desired specifications for such devices. To ensure skin continuity, power transmission and all communication is to be done through a wireless link putting severe limitations on the implanted device power consumption. The body consitutes a noisy environment as electrical signals are evoked when muscles
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Nielsen and Bruun
Fig. 1. (a) Distributed chip solution including actuator- and sensor chips for nerve trunk interfacing and transceiver chip for wireless communication and power reception. (b) Block diagram of the proposed sensor chip.
are activated, hence the nerve signal processing has to be noise-immune and be able to cope with large interferers evoked from muscles in close proximity to the implant. The circuitry further has to operate correctly when facing an unclean power supply, which is inherent to telemetric power transfer as the fundamental transmission frequency and it’s harmonics will be present on the supply. The paper is organized as follows: A system description is given first, whereafter the individual system subcomponents that comprise the front-end are discussed at design level, Measurement results of the implemented front-end are then presented and finally conclusions are drawn.
2.
System Description
The envisioned full nerve stimulation- and sensing system is shown in Fig. 1(a) and comprises a set of three chips: A transceiver chip which facilitates wireless communication and provides the internal power supply, an actuator chip for FES and finally a sensor chip for nerve-signal recording. A distributed solution is preferred over a single-chip solution since the transceiver chip can be implanted at a shallow depth to ensure high power transfer efficiency thus minimizing the necessary field strength. Also, the sensor- and actuator chips can be placed adjacent to their respective recording/stimulation sites which may be two different locations, thus ensuring good signal pickup and minimal signal loss. Furthermore, the nerve interfacing chips can be placed far from the power/communication RF-field which may desentisize the sensing front-end or interfere with the stimulation signal. Prototypes of the actuator chip [3] and the transceiver chip [4] have
been designed, fabricated and tested. All chips that comprise the system are implemented in CMOS technology allowing for inexpensive batch fabrication and integration of digital logic with analog functions. This paper is concerned with the design and implementation of the sensing chip which comprises a front-end suitable for interfacing with a cuff-electrode for human ENG recording. A block diagram of the sensor chip is shown in Fig. 1(b). A cuff-electrode is mounted around the nerve trunk and provides the raw nerve ENG. The recorded nerve signal has a magnitude of only a few microvolts and it is therefore imperative that the signal is amplified prior to further processing. After preamplification, the signal is quantized making it suitable for wireless transmission. The cuff is manufactured from silicone and typically has a length of a few centimetres while the diameter is approximately 20% larger than the nerve itself to avoid pressure damage to the nerve when mounted. Three electrodes are fitted inside the cuff and provide balanced signal pickup when the center electrode is used as reference. As the nerve signal may contain DC-offsets on the order of several volts, the cuff signal is ACcoupled prior to interfacing with the sensor chip itself. This is done not only to avoid saturation of the amplifier itself, but also since offsets of this magnitude may exceed the device reliability limits of a modern CMOS process. Although AC-coupling imposes a transmission zero at DC in the signal path, this has no effect on signal recovery as the main energy of human nerve signals lie in a range from 400 Hz to 4 kHz [1]. Due to minute magnitude of the raw cuff-recorded ENG signal, very low noise performance is required for the preamplifier in order to retain a sufficient SNR. As intrinsic thermal noise in CMOS transistors is inversely proportional to power consumption, this constitutes a
An Implantable CMOS Front-End System for Nerve-Signal Sensors
major design challenge for low power operation. The amplifier noise performance is dictated by the noise floor intrinsic to the resistiveness of the cuff electrode itself, i.e., the amplifier noise contribution should be negligable compared to the inherent cuff noise. Interfering signals evoked by activated nearby muscles will couple to the cuff as common-mode signals requiring the amplifier to have a high common-mode rejection ratio (CMRR). As a clean power supply cannot be guaranteed, a high amplifier power supply rejection ratio (PSRR) is also a necessity. The nominal gain of the amplifier was set to 74 dB, bringing a cuff signal of 20 µVpp to 100 mVpp at the amplifier output. As digital signal transmission has superior noise immunity over analog transmission, the signal is quantized by an ADC after amplification. This also conditions the signal for further processing which is to be performed in the digital domain. As the signal at this point has gained 74 dB in magnitude, the noise requirements of the ADC can be heavily relaxed. The resolution of the ADC was set to 10 bits in order to provide a good margin to the 8–9 bits of inherent resolution with respect to the cuff thermal noise. 3.
Instrumentation Amplifier
The overall amplifier gain of 74 dB is achieved by using a two-stage open-loop topology as shown in Fig. 2. As the first stage is the most noise critical it features the higher gain of 40 dB, whereas the second stage, which has relaxed noise requirements, has a gain of 34 dB. For low flicker noise performance, the first stage furthermore employs chopper modulation. For faithful signal recovery, an interstage low-pass (LP) filter is needed to suppress signal images and chopper imposed dynamic offsets present at the chopper frequency and its harmonics. The LP filter was not included on-chip in the prototype but rather applied between stages offchip. A transistor level description of the amplifier can be found in [10].
Fig. 2.
Instrumentation amplifier block diagram.
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An approximate expression for the input referred noise spectral density of a MOS transistor (MOST) is given by [5]: Kf 2 1 vni2 ( f ) = 4 kT + 3 gm WLCox f thermal
(1)
flicker
The first term of (1) is the wideband thermal noise contribution of the MOST, which is seen to be inversely proportional to the MOST transconductance gm . For a given current IDS , the MOST transconductance is maximized by biasing the device in the weak inversion region where a bipolar mode of operation is imposed upon the transistor giving [6]: gm /IDS = 1/nVT
(2)
where n is the slope factor. I.e. the gm /IDS ratio is maximized in the weak inversion region, thus implying optimum input referred thermal noise suppression. The main drawback of weak inversion operation is that a rather large aspect ratio of the MOSTs is needed for any appreciable current [7]. In our case an acceptable input MOST size of 600 µm/0.6 µm was chosen for an input pair bias current of IDS = 100 µA, giving 70% of the asymptotic maximum transconductance value given by (2). Hence the thermal noise contribution can be controlled by power consumption. At low frequencies the flicker (1/ f ) noise of MOSTs typically dominate and the noise corner can be located at several tens of kHz, thus being the prime noise contributor in our design. By employing the chopper modulation technique for the first stage of the amplifier, the 1/ f -noise can be shifted out of the signal band of interest and be removed by post-filtering thus leaving us solely with the thermal noise contribution. Since the amplifier input signal is modulated twice, i.e., the signal is up-converted to the chopper frequency at the amplifier input and downconverted at the output, the input signal present at baseband frequencies is left unaffected by the modulation. A prerequisite for employing the chopper modulation technique is that only negligable phaseshift is induced by the amplifier at the chopping frequency. This is however easily fulfilled as the bandwidth of the chopped first stage is in the range of several MHz due to the relatively high biasing current. Chopping of the 1/ f -noise inevitably results in downfolding of 1/ f -noise spectral replicas into the
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Nielsen and Bruun
Fig. 4.
Fig. 3.
Downfolded 1/ f -noise spectral replicas.
baseband. In Fig. 3, the PSD for the first three downfolded 1/ f -noise components and their sum at the first stage output is shown. The output power Sy ( f ), is shown normalized to the output thermal noise power: Sy,th ( f ) = A20 S0
By setting the feedback coefficients cx appropriately, the noise transfer function (NTF) was designed as a Butterworth high-pass filter with a corner frequency of 80 kHz, thus moving the quantization noise from the baseband to higher frequencies. If the quantization noise power σq2 , is assumed to be white, the total amount of inband noise power for a reference voltage Vr e f , can be calculated [8]:
(3)
where A0 is the amplifier gain and S0 is the thermal noise PSD. The first downfolded 1/ f -noise component accounts for more than 95% of the overall downfolded 1/ f -noise power. Taking only the first component into account and assuming a flat inband noise contribution, it can be shown that an approximate expression for the resulting effective thermal noise is given by [8]: 8 fc Sth, eff ( f ) ≈ A20 S0 1 + 2 (4) π f chop where f c is the 1/ f -noise corner frequency and f chop is the chopping frequency. From (4) it is seen that the 1/ f -noise contribution to the effective thermal noise floor can be minimized by choosing a sufficiently high chopping frequency. 4.
Third order -modulator ADC block diagram.
A/D Converter
In order to provide a good margin to the 8–9 bits of resolution inherent to the cuff signal, a desired ADC resolution of N = 10 bits was set. A third order continuous-time Candy-loop -modulator using a single-bit quantizer as shown in Fig. 4 was chosen for the task. The quantization noise due to the comparator is modelled as an additive noise source q(n).
Pq,inband =
2 2 σq Vref
fs
fb
|NTF( f )|2 d f
(5)
0
The sampling frequency was set to 1.4 MHz, resulting in an oversampling ratio OSR = 175 for a signal bandwidth of 4 kHz. The feedback DAC waveform employed is a NRZ square wave. A continuous-time (CT) implementation was chosen over the classical discrete-time (DT) switchedcapacitor (SC) approach as a more power-efficient circuit can be obtained [9]. Firstly, an explicit anti-aliasing (AA) filter is not needed for the CT solution as the sampling process takes place deep inside the loop-filter as shown in Fig. 4, hence employing the preceeding integrators as an implicit AA filter. Secondly, the necessary gain-bandwidth (GBW) for the OTA driving the integrating capacitor Cint , in the SC solution is given by the necessary number of time-constants n, needed for sufficient settling within the desired resolution of the overall ADC. For a desired resolution of B bits, n is given by: n > (B + 1) ln(2)
(6)
Asumming a first-order model of the OTA, the settling time-constant is given by: τ = 1/(2π GBW)
(7)
An Implantable CMOS Front-End System for Nerve-Signal Sensors
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amplitude MSA, the minimum allowable capacitor size can be determined [8]: Cint = NEF · kT
Fig. 5.
The size of the integrating capacitor Cint , is determined by the tolerable amount of noise power, which thereby implicitly sets the needed OTA GBW. Hence, the power consumption of a SC integrator is determined by the capacitor size. For CT integrators, the GBW of the active elements is typically not dependent on the integrator capacitor size, but rather on internal parasitic capacitors which can be minimized by careful design. Thus a lower power consumption can be tolerated for a given desired integrator GBW. For the integrator implementation, a fully differential G m − C topology was chosen. A single-ended version of the integrator cells is shown for simplicity in Fig. 5. The integrator GBW is set by GBW = G m1 /Cint , and the DAC feedback coefficient c, is determined by the transconductance ratio c = G m2 /G m1 . The total accumulated thermal noise present on the integrating capacitor taking the transconductor into account is given by [11]: NEF · kT Cint
5.
G Th,out Gm
(10)
Measurements
The proposed sensing front-end has been implemented in a standard double-poly, four-metal, 0.35 µm CMOS technology. The chip micrograph showing the implemented circuit is shown in Fig. 6. The upper half of the chip contains two different versions of the instrumentation chopper amplifier. As previously mentioned, the interstage LP filter of Fig. 2 was not implemented onchip. Instead a Stanford Research System model SR640 filter was applied off-chip for the following measurements.
(8)
where NEF is the Noise Excess Factor defined as the ratio of total output thermal noise conductance G th,out , over the cell transconductance: NEF =
−1
This capacitor size is the minimum allowable for the first integrator in the loop-filter. This integrator is noise-critical as it constitutes the input integrator and allows all input signals to pass unimpeded to the modulator output. All other integrator outputs in the Candy loop are filtered and their noise requirements can be relaxed. The biggest power consumer in the loop is therefore the first integrator which accounts for more than half the total power consumed by the modulator.
G m − C integrator.
Pth =
(MSA · Vref )2 − Pq,inband 2 · 10(6.02B+1.76)/10
(9)
The total inband quantization noise was found from (5). For a resolution of B bits and a maximum stable input
Fig. 6.
Chip micrograph.
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Nielsen and Bruun
Fig. 7.
Instrumentation amplifier frequency response.
The lower half contains the -modulator A/D converter. The system supply voltage was set to 1.8 V. The following measurements are based on averages over the set of ten test chips if nothing else is mentioned. 5.1. Instrumentation Amplifier The amplifier magnitude frequency response is shown in Fig. 7. A slightly lower than expected average gain of 72.5 dB is measured over the 4 kHz signal bandwidth. The observed gain variation over the set of test chips was however within ±5%, indicating that very good matching is achieved. The 3 dB frequency was measured to 10 kHz. For an input frequency of 1 kHz, less than 0.5% of total harmonic distortion is observed for an input amplitude of 40 µVpp . A measured slew-rate of 5.8 V/ms ensures prompt recovery of a saturated output in case of amplifier input overload. The chopped output noise spectrum is seen in Fig. 8. A chopping frequency of 20 kHz is used for these measurements. The chopper signal and it’s harmonics are clearly visible in the spectrum. What is seen from the spectrum is an absence of flicker noise at low frequencies indicating that this noise type is removed by the chopper modulation, leaving only thermal noise to dominate the low-frequency noise performance. The overall inband noise performance of the amplifier is √ measured to 28 µV/ Hz output √ referred, equivalent to approximately 6.6 nV/ Hz at the amplifier input.
Fig. 8.
Instrumentation amplifier output chopped noise spectrum.
As the amplifier is subject to common-mode interferes and power supply noise, a good CMRR and power supply rejection ratio PSRR are desirable. For both rejection ratios, a significant increase of more than 20 dB was be observed when chopper modulation was enabled, thus leading to an inband CMRR above 105 dB and a PSRR of more than 90 dB. This is due to an added benefit of chopper modulation: Any signal couping into the noise-critical first stage after the first chopper but prior to the second chopper will only be modulated once and will hence be shifted out of the frequency band of interest where they can be removed by postfiltering, thus leaving us with a clean signal band. The total power consumption of the amplifier was measured at 242 µW, where 80% of the power is consumed in the first stage as it is the most power hungry due to the imposed low-noise requirements. 5.2. A/D Converter An example output spectrum of the bit-stream from the -modulator ADC is shown in Fig. 9. The noiseshaping action of the NTF is clearly seen as the quantization noise is moved to higher frequencies. Although the design is fully differential, the second harmonic is seen to dominate the harmonic performance of the ADC indicating unbalanced operation. A likely cause of the even order harmonic dominance is intersymbol interference which is caused by unequal rise- and falltimes in the DAC feedback pulse. In Fig. 10 this error effect is illustrated: Although the two non-return-to-zero (NRZ) feedback waveforms
An Implantable CMOS Front-End System for Nerve-Signal Sensors
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an input tone of 120 m V pp at a frequency of 1860 Hz. The dynamic range was measured to 67 dB. The total power consumption of the ADC was measured to 108 µW, where the first integrator accounts for approximately 60% of the power dissipation as it is the most critical component of the ADC. The measured main specifications of the front-end is summarized in Table 1. 6.
Fig. 9.
-modulator ADC example output spectrum.
x1 (t) and x2 (t) in Fig. 10(a) have the same median signal feedback energy, the total amount of glitch energy is non-equal due to the difference in rise/fall time. As this effect is signal dependent, it is a cause of harmonic distortion. A solution to this is proposed in Fig. 10(b) where a return-to-zero (RZ) waveform is used. Here, the number of transitions is forced to be equal for x1 (t) and x2 (t), thus forcing an equal amount of glitch energy and hence eliminating this source of non-linearity. A drawback of using the RZ waveform is the increase of clock jitter susceptibility. Although the even-order harmonics unexpectedly dominate the output spectrum, the maximum SNDR was measured to 62 dB over the nerve signal bandwidth as shown in Fig. 11, equivalent to a resolution of 10 bits. The SNDR measurements were done using
Fig. 10.
Conclusion
A low-power front-end for cuff-recorded nerve signals has been presented in this paper. The front-end is comprised of a low-noise, high-gain pre-amplifier for initial signal amplification and a -ADC for quantization. The system was implemented in a standard 0.35 µm CMOS technology. Due to the minute magnitude of the sensor input signal, most of the system power is consumed by the pre-amplifier. By employing a mix of MOS transistors biased in the weak/moderate inversion region and by using the chopper modulation technique, very low overall noise performance of the amplifier is achieved. The interstage LP filter was applied off-chip but does not pose a severe design challenge for on-chip implementation and the expected power budget overhead for an on-chip solution is minimal. A continuous-time -modulator was chosen for the ADC as a lower integrator GBW can be tolerated in CT -modulators over their discretetime counterparts, implying lower power consumption. A drawback is higher sensitivity to non-idealities, e.g., intersymbol interference which is conjectured to be the prime cause for the unexpected even order
Harmonic distortion caused by intersymbol interference in single-bit DAC feedback waveforms.
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Nielsen and Bruun Table 1.
Front-end performance summary.
Acknowledgment
System Supply voltage
1.8 V
Power consumption
353 µW
This work was supported by the Danish Medical Research Council.
Instrumentation amplifier Power consumption
245 µW
3 dB frequency
10 kHz
References
THD ( f = 1 kHz)
<0.5%
CMRR
>105 dB, f < 10 kHz
PSRR
>85 dB, f < 10 kHz
Gain
72.5 dB
Eq. input ref. noise
√ 6.6 nV/ Hz
Slew rate
5.8 V/ms
A/D converter Power consumption
108 µW
Signal bandwidth
3.6 kHz
Sampling frequency
1.4 MHz
Peak SNDR
62 dB
Dynamic range
67 dB
Fig. 11. -modulator ADC measured distortion ratio for increasing signal amplitude.
1. M.K. Haugland, “Natural sensory feedback for closed-loop control of paralyzed muscles.” Ph.D. thesis, University of Aalborg 1994. 2. A. Lickel, “Restoration of lateral hand grasp in a tetraplegic patient applying natural sensory feedback.” Ph.D. thesis, University of Aalborg 1998. 3. G. Gudnason et al., “An implantable mixed analog/digital neural stimulator circuit,” in Proc. ISCAS, Orlando FL, USA, vol. 5, pp. 375–378, 1999. 4. G. Gudnason, et al., “A distributed transducer system for functional electrical stimulation,” Proc. ICECS, Malta, vol. 1, pp. 397–400, 2001. 5. D.A. Johns and K. Martin, Analog Integrated Circuit Design. John Wiley and Sons, Inc. New York, NY, 1997. 6. C. Enz, et al., “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and lowcurrent applications,” Analog Int. Circ. and Signal Proc., vol. 8, pp. 83–114, 1995. 7. J.H. Nielsen and T. Lehmann, “An implantable CMOS amplifier for nerve signals,” Analog Int. Circuits and Signal Proc., vol. 36, pp. 153–164, 2003. 8. J.H. Nielsen, “Low power CMOS interface circuitry for sensors and actuators.” Ph.D. thesis, Technical University of Denmark, 2003. 9. F. Gerfers, et al., “A 1.5 V 12-bit power-efficient continuoustime third order modulator,” IEEE J. Solid State Circ., vol. 8, pp. 1343–1352, 2003. 10. J.H. Nielsen and E. Bruun, “A CMOS chopper amplifier for implantable sensors,” in Proc. 21st NORCHIP Conf., Riga, Latvia, 2003, pp. 275–278. 11. J.H. Nielsen and E. Bruun, “A low-power 10-bit continuoustime CMOS A/D converter.” in Proc. ISCAS, Vancouver BC, Canada, vol. 1, 2004, pp. 417–420.
signal-noise-and-
harmonic dominance measured in the prototype test chips. The feasibility of all-CMOS solutions for electronic biomedical implants is confirmed, allowing for fabrication of high performance implantable circuits in the inexpensive CMOS technology without requiring any special process options.
Jannik Hammel Nielsen was born in Nuuk, Greenland, in 1972. He received the M.Sc. and Ph.D. degrees in electrical engineering in 1999 and 2004 respectively, from the Technical University of Denmark. In 2004 he
An Implantable CMOS Front-End System for Nerve-Signal Sensors
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was employed as a postdoctoral researcher at Ørsted DTU. Since 2004 he has been Assistant Professor of analog electronics at Ørsted DTU. His main research interests are in low-voltage, lowpower analog systems, medical electronics and data converters.
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Erik Bruun received the M.Sc. and Ph.D. degrees in electrical engineering in 1974 and 1980, respectively, from the Technical University of Denmark. In 1980 he received the B.Com. degree from the Copenhagen
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Business School. In 2000 he also received the dr. techn. degree from the Technical University of Denmark. From January 1974 to September 1974 he was with Christian Rovsing A/S, working on the development of space electronics and test equipment for space electronics. From 1974 to 1980 he was with the Laboratory for Semiconductor Technology at the Technical University of Denmark, working in the fields of MNOS memory devices, I2 L devices, bipolar analog circuits, and custom integrated circuits. From 1980 to 1984 he was with Christian Rovsing A/S. From 1984 to 1989 he was the managing director of Danmos Microsystems ApS. Since 1989 he has been a Professor of analog electronics at the Technical University of Denmark where he has served as head of the Sector of Information Technology, Electronics, and Mathematics from 1995 to 2001. Since 2001 he has been head of Ørsted DTU. His current research interests are in the areas of RF integrated circuit design and integrated circuits for mobile phones.
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