Analog Integrated Circuits and Signal Processing, 14, 143–157 (1997)
c 1997 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands. °
Analysis of Metastable Operation in a CMOS Dynamic D-Latch J. JUAN-CHICO1,2 , M. J. BELLIDO1,2 , A. J. ACOSTA1,3 , M. VALENCIA1,2 AND J. L. HUERTAS1,3 1 Instituto de Microeletr´onica de Sevilla. Centro Nacional de Microelectr´onica. Edificio CICA, Avda. Reina Mercedes s/n, 41012-Sevilla, Spain, 2 Dpt. de Tecnolog´ıa Electr´onica, Universidad de Sevilla, 3 Dpt. de Electr´onica y Electromagnetismo de la Universidad de Sevilla
[email protected]
Received May 1, 1996; Accepted November 4, 1996
Abstract. Nowadays, metastability is becoming a serious problem in high-performance VLSI design, mainly due to the relatively-high probability of error when a bistable circuit operates at high frequencies. As far as we know, there is not any work published that justifies and formally characterizes metastable behavior in dynamic latches. With current technologies, dynamic latches are widely used in high-performance VLSI circuits, mainly due to their lower cost and higher operation speed than static latches. In this work, we demonstrate that dynamic memory cells present an anomalous behavior referred to as metastable operation with characteristics similar to those of static latches. We perform a suitable generalization of metastability to the dynamic case, applying it to a CMOS dynamic D-latch. A theoretical model will be proposed, allowing the quantification of metastability, and it will be validated through electric simulation with HSPICE. After that, we have compared the metastable behavior of the dynamic latch with its static counterpart, obtaining results about the characteristic parameters of metastability and the Mean Time Between Failures (MTBF) for both kinds of bistable circuits. These results have allowed us to conclude that, unlike metastability windows in static latches, a clearly defined input interval exists which produces an infinite resolution time. Regarding MTBF, the dynamic latch presents a very low MTBF value compared to the static latch. These results show that dynamic latches should not be used in those circuits where the risk of asynchronism between clock and data signals is not negligible. Key Words: Metastability in dynamic latches, high performance CMOS VLSI design, mean time between failures, synchronization and arbitration 1.
Introduction
In digital systems, the metastable state refers to the operation of bistable circuits in an unstable equilibrium point under specific input conditions called marginal triggering. Once the bistable circuit enters its metastable region, it can remain in such a state for an indefinite time prior to evolving into one of its stable states. During this time the bistable circuit’s outputs present a voltage value undefined at a logical level. In these conditions, it is impossible to guarantee that two circuits reading the same metastable signal simultaneously, will interpret the same logic value. Consequently, a system operating in its metastable state is a potential source of errors [1]. Since the initial age of digital systems, metastability has been extensively studied. At the beginning, general aspects over the existence of this phenomenon were faced, showing experimental evidences [2, 3, 4] and presenting abstract proofs [5, 6], and both theoretical and empirical models describing the metastable be-
havior were presented [7, 8]. Furthermore, these models provide expressions to determine the probability of fault caused by metastability [9, 10]. In the same way, the characterization of bistable circuits appeared: techniques for the measurement of metastable parameters [11, 12, 13], circuits detecting the metastable operation [14, 15], design of metastable-robust synchronizers and arbiters [16, 17, 18, 19], etc. On the other hand, the evolution of microelectronics itself has contributed to increase the importance of the metastable operation. Indeed, since the complexity of systems is rapidly increasing, the timing problems are becoming more and more important, and hence, there are more probabilities of marginal triggering. Therefore, the high speed of current systems is leading to a shorter time for resolving the metastable state to a stable state. Both factors (i.e. the high probability of marginal triggering and the possibility of lower resolution times) make VLSI designers take metastability into account when designing high performance VLSI
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Fig. 2. Logic scheme of a dynamic D-Latch.
Fig. 1. a) 2-INV Loop. b) Equilibrium points in 2-INV loop.
digital systems. This trend has been stated in recent literature, on the one hand, in books on VLSI Logic Design [20, 21, 22, 23] and, on the other hand, in research papers specialized in digital design, where metastability studies focus on the VLSI perspective: metastability in CMOS RS latches [24, 25], CMOS D latches [14, 26, 27], NMOS D latches [28] and BiNMOS D latches [29]. In these references, the main tool used for characterizing metastability is electrical simulation (usually SPICE or HSPICE [30]). In these previous references, metastability is treated as the anomalous behavior of static bistable circuits. Specifically, it is associated to the basic memory cell for the static storage of one bit (Fig. 1a), henceforth called 2-INV loop. If we represent its stationary operation (Fig. 1b), three equilibrium points can be observed: A, B and M. Points A and B are stable and correspond to the well-defined logic levels. Point M is unstable and corresponds to the metastable state, with the output of the inverters presenting an intermediate value, between logic levels and, hence, outputs are not defined as 0 or 1 [31]. From this point of view, metastability is an analog phenomenon within a digital system, thus, an analog analysis must be carried out. Nowadays, dynamic latches are widely used in high performance VLSI circuits, mainly due to their lower cost and higher operation speed than static latches. In spite of the high number of papers dealing with metastability, as far as we know, there is no other work published that justifies and formally characterizes the metastable behavior in dynamic latches. A close approach is presented in [32] where the dynamic behavior of two dynamic CMOS latches is analyzed. However, that analysis is focused on the problems related to clock-skew, and not on the metastable operation. In any case, for dynamic memory cells, an anomalous behav-
ior is expected, corresponding to the storage of a voltage between 0 and 1 logic levels. This anomalous behavior happens under the same set of marginal triggering as in the static latches and, as it will be demonstrated in this work, presents similar characteristics. Thus, we are going to refer to this behavior as metastable operation of dynamic latches, for its similarity with the static case. However, the generalization of this concept must be carefully carried out, since dynamic latches do not contain the 2-INV loop (Fig. 1a) as basic cell, which is the basis of the static metastability. In this work, we propose a generalization of metastability suited to the dynamic case, applying it to the CMOS dynamic D-latch shown in Fig. 2. A theoretical model will be proposed, allowing for the quantification of metastability, and it will be validated through electrical simulation with HSPICE. After that, we will compare the metastable behavior of the dynamic latch with its static counterpart, obtaining results about the characteristic parameters of metastability (the so-called metastability window) and the Mean Time Between Failures (MTBF function) for both kinds of bistable circuits. These results will allow us to determine which bistable is ideal for those applications that are prone to fail due to metastable operation. The organization of the paper is as follows: The next section presents a summary of metastability in static latches, with the purpose of showing the most important concepts, terms and parameters related to metastability. In section 3, the theoretical model of a dynamic D-latch in metastability is shown. In section 4, the proposed model is verified through electrical simulation. In section 5, a comparison between static and dynamic latches is performed. Finally, the most important conclusions are presented. 2.
Metastability in Static D-latches
Fig. 3 shows the schematic of a CMOS VLSI standard static D-latch. With C K = 1, q takes the value of input D, while with C K = 0, it operates as a 2-INV loop. In this case, the bistable operates as a cell memory, statically storing the value previously introduced.
Analysis of Metastable Operation In this situation, the bistable might operate in metastability when input triggering have led the 2-INV loop to the M point. In that sense, the input triggering is known as marginal triggering. For the D-latch of the Fig. 3, the marginal triggerings are (Fig. 4): a) With q = 0, D = 0 and C K = 1, almost simultaneous change between D: 0 → 1 and C K : 1 → 0. b) With q = 1, D = 1 and C K = 1, almost simultaneous change between D: 1 → 0 and C K : 1 → 0. c) With q = 0, D = 1 and C K = 0, runt pulse in C K : 0 → 1 → 0. d) With q = 1, D = 0 and C K = 0, runt pulse in C K : 0 → 1 → 0. These marginal triggerings can be quantitatively characterized through the following timing parameters: • Time skew, g: it measures the time interval elapsed between the change of D and the fall of C K (Fig. 4a and b). It characterizes the marginal triggering for cases a and b. • Pulse width, Tw : it measures the time interval elapsed between the rising and the falling edges of one signal, C K in our case (Fig. 4c and d). It characterizes the marginal triggering for cases c and d. For every marginal triggering, a region of values corresponding to g or Tw exists that may produce metastable operation. This region is known as metastability window. The metastable behavior of the bistable circuit is characterized by its operation in an undefined state (non-logic) until its resolution to one of its stable states after an indefinite time. A quantitative measurement of this behavior is given by the so-called resolution time, tr (Fig. 4), which measures the time needed by the bistable circuit to reach a stable state, after the marginal triggering happens.
Fig. 3. Static D-Latch.
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Fig. 4. Marginal triggering and timing parameters.
The most common way of determining the metastability window is by the representation of tr versus the parameter describing the marginal triggering (g or Tw ), named T for simplicity. A typical shape of a metastability window is shown in Fig. 5. In such a representation, the tr 0 parameter is the resolution time in which the bistable changes its state without operation in metastability (normal resolution time). With all the above, the metastability window for a given tr is defined as the range of time skew (T ) that yields a resolution
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Fig. 5. Typical shape of tr versus T curve. Metastability window.
time larger than tr . The metastability window width (1T (tr )) is the measure of that range. The metastability window characterizes how good the bistable circuit is with respect to metastability. Several theoretical and empirical studies [7, 8, 9] have led to the following expression (1) for the metastability window 1T (tr ) of Fig. 5, depending on the resolution time tr : 1T (tr ) = T0 e− τ
tr
(1)
where T0 and τ are parameters characteristic of each bistable.
3.
Theoretical Analysis of Metastability in Dynamic D-Latches
When analyzing the D-latch incorporating a dynamic structure as the one shown in Fig. 2 (this work is focused on CMOS technology), the first concern is that it does not contain any 2-INV loop. This means that there is no unstable equilibrium point M, as with the static D-latch (Fig. 3). However, it does not mean that there is not anomalous behavior under specific input triggering. Thus, for the same set of marginal triggering defined for the static D-latch, the dynamic D-latch may operate in an irregular way, trying to store a logic value (by charging or discharging the parasitic capacitor at the input of the CMOS inverter) but doing it incorrectly. In this way, the output will remain in a non-defined
logic value during an undetermined period of time. In other words, there is a range of input triggering yielding tr > tr 0 and hence, a metastability window exists in these kinds of latches. This anomalous behavior is henceforth called metastable behavior of the dynamic D-Latch, based on the analogy of the static case.
3.1.
Fundamentals of the Metastable Operation in Dynamic Latches
The metastable behavior of the dynamic D-latch lies in the storage of a voltage value at the input of the inverter in the latch, making the voltage at the output not defined at a logical level. Fig. 6 shows the transfer characteristic of a CMOS inverter. The logic character of the output is defined by thresholds VTOL and VTOH , in such a way that, for VTOL , the output is a logic “0” and for Vo > VTOL there is a logic “1” at the output. By observing Fig. 2 and the transfer characteristic of the inverter (Fig. 6), the way of driving the output Vq 0 to a non-determined state between both logic thresholds VTOL and VTOH is placing VX between the corresponding threshold logic levels at the input of the inverter: VTIL and VTIH . Therefore, the marginal triggering voltages for this bistable are those transitions in C K and D such that VTIL < VX < VT I H . The triggering set that can produce this behavior is the same as the one described in the previous section
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Fig. 6. DC Transfer characteristic of a CMOS inverter.
Fig. 7. Simple Model for the CMOS switch.
Fig. 8. Equivalent input circuit for the dynamic D-Latch.
as marginal triggering for the static D-latch, and called a, b, c and d types.
metastable state when the triggering through C K and/or D places VX in the interval VTIL < VX < VTIH . With the described model and, supposing for simplicity, instantaneous transitions in D and C K , a and c types marginal triggering are equivalent, from the point of view of the voltage stored in VX . The same happens for b and d types. For this reason, we refer to T as the timing parameter describing the marginal triggering (either g or Tw ) and we will study the case a-c, the case b-d being analogous. In the electrical analysis, we can consider two different zones: 1) Between the rising edge of D or C K (a or c triggering types, respectively) and the falling edge of C K , and 2) after the falling edge of C K . The first zone corresponds to the time interval 0 ≤ t ≤ T and the second one to t > T . The equivalent circuits
3.2. tr Versus T Curve For the sake of clarity, a simplified model for the switch gate in the CMOS dynamic D-latch, as the one shown in Fig. 7 will be considered. In this model, the resistive effects are represented by an ideal switch with VDD /2 threshold and an effective resistance Reff . The capacitive effects are included in C S . Furthermore, we suppose that the inverter presents an effective input capacity Cin . Thus, the voltage in node VX is given by the circuit of Fig. 8, where C X = Cin + C S /2. As previously shown, the device will enter its
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in each case are shown in Fig. 9. The analysis of these circuits is simple and results in: ½ 0≤t ≤T VDD (1 − e−t/τ ) VX (t) = (2) VDD (1 − e−T /τ ) t>T where τ = Reff C X . If we define TC1 and TC2 as the time points in which VX = VTIL and VX = VTIH respectively, and we call tr 0 the normal resolution time for a normal (non-marginal) triggering, we can consider four regions with different behavior depending on the value of T : 1) T < TC1 (VX (T ) < VTIL ): There is no metastability. The logic state at the output is kept. tr = 0. 2) TC1 < T < TC2 (VTIL < VX (T ) < VTIH ): The output is placed in a non-defined logic state. tr = ∞. 3) TC2 < T < tr 0 (VTIH < VX (T )): The output changes its logic state after a time tr ≥ tr 0 . 4) tr 0 < T (VTIH < VX (T )): The output switches to the opposite logic state before the falling edge of C K . It corresponds to a normal propagation. tr = tr 0 . Fig. 10 shows waveforms corresponding to the described behavior for the four different regions. The metastable behavior of the latch will be fully characterized when the parameters TC1 , TC2 , tr 0 and the curve tr (T ) in region 3 are completely known. Although the curve in this region is unknown, some basic characteristics can be established: for continuity between regions 2 and 3, the resolution time near TC2 must tend to infinite; and for continuity between regions 3 and 4, the resolution time must be tr 0 in the boundary. Taking into account the four regions defined, Fig. 11 shows a proposed representation of resolution time versus T .
Regarding TC1 and TC2 , a first approach can be obtained from our proposed simplified model. Considering (2) and definitions for TC1 and TC2 , we have that: µ ¶ VTIL TC1 = −τ log 1 − VD D µ ¶ VTIH (3) TC2 = −τ log 1 − VD D These expressions, although extracted from a simplified model, state their linear dependence on Reff and C X , as well as a strong dependence on VTIL and VTIH . Precise values of TC1 and TC2 can be calculated through electrical simulation as will be shown in the next section. The parameter tr 0 represents the pure delay of the switch-inverter system and can be calculated by electrical simulation. Concerning resolution time in region 3, the latch shows a more complex behavior. Especially, tr is continuously decreasing for T ≥ TC2 from infinite (when T = TC2 ) down to the normal resolution time (T = tr 0 ). In this way, the metastability window width, 1T , presents two different regions, depending on the value of tr : the first is a constant 1T1 = TC2 − TC1 , corresponding to region 2, and the second is variable, corresponding to the region 3. Thus, we have that: 1T (tr ) = 1T1 + 1T2 (tr ) = TC2 − TC1 + 1T2 (tr ) (4) Taking into account the basic characteristics of the r t versus T curve for region 3, we propose an exponential adjustment expression for 1T2 (tr ): 1T2 (tr ) = Ae− τ
tr
(5)
where A and τ are the adjustment parameters of this curve. Thus, the width of the metastability window for the dynamic latch is described by the following equation: 1T (tr ) = TC2 − TC1 + Ae− τ
tr
Fig. 9. Equivalent circuits to calculate VX (t) for (a) 0 ≤ t ≤ T , (b) t > T .
(6)
Comparing this expression with that of the static latches (1), it can be observed how both expressions have a similar exponential term, while the main difference lies in the constant term TC2 − TC1 in the dynamic latch, so that, when tr goes to infiniti, the metastability window width tends to such a constant value, instead of 0, as it happens in the static latch.
Analysis of Metastable Operation
Fig. 10. Time evolution of signal VX (t) and Vq 0 (t) for different values of the timing parameter T .
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Fig. 11. Proposed shape for tr (T ) curve, characterizing the metastable behavior of the dynamic D-latch.
Table 1. Geometric parameters of transistors used for simulations.
WN WP
4.
INV latch
Switch
INV Switch
2 µm 1 µm
1 µm 1 µm
1 µm 3.6 µm
Simulation Results
In this section, we are going to verify the qualitative analysis performed in the previous section, as well as the ability of the adjustment expression (6) for fitting results of precise electrical simulation. The circuit so simulated is shown in Fig. 12. In this circuit, the length of channels are the minimum for all the MOS transistors (L = 0.8µm) for the technology used (ES2 CMOS 0.7µm). The channel widths are shown in Table 1. For the geometries of the inverter in the latch, we have chosen the optimum regarding the metastable behavior of a static latch with those inverters. The criterion used is the minimum area and the geometry calculation method is the single-pole method [31]. This criterion allows a further comparative analysis with the static latch in next sections.
Fig. 12. Dynamic D-latch circuit used for electrical simulation with HSPICE.
Analysis of Metastable Operation The transistors considered in the switch have the minimum area for the used technology. The inversion of the clock signal has been performed with an inverter with approximately symmetrical transfer characteristic. An a-type marginal triggering, i.e. almost simultaneous change of D: 0 → 1 and C K : 1 → 0, has been simulated. This simulation has been carried out with the electrical simulator HSPICE, using level 6 models provided by the foundry. The criterion for the selection of the logical threshold is a variation of 10% in the supply rails: VTOL = 0.1VDD 4.1.
VTOH = 0.9VDD
(7)
Transient Analysis
Fig. 10 shows how different values of T place VX in the regions mentioned in the previous section, resulting in the behavior foreseen by the theoretical model. It is very important to notice how similar values of T can produce very different behavior when the bistable operates in a zone very close to TC2 (Fig. 10, curves 2 and 3), as well as a considerable increase in the resolution time for triggering with TC1 < T < TC2 (Fig. 10, curve 3). 4.2.
tr Versus T Curve
Simulating the circuit of Fig. 12 for different values of T and evaluating the time points when the Vq 0 (t) signal intersects the thresholds VTOH and VTOL for the case under analysis of a falling transition in q 0 ; we have obtained the resolution time (tr ) as a function of the parameter describing the marginal triggering T . The curve so obtained is shown in the Fig. 13, where tr = 0 means that there was no logic switching in output node (T < TC1 ). It can be seen how the expected behavior of the previous section is reproduced (Fig. 11). By using this graphical representation, we have obtained the values for 1T2 , showed in Fig. 14a. In this curve, the exponential relation between 1T2 and tr can be clearly observed, as was proposed in the previous section. From the curves in Fig. 13 and Fig. 14, we can obtain the value for the parameters characterizing the metastability window: TC1 , TC2 , A and τ , resulting in: TC1 = 0.05722 ns TC2 = 0.11655 ns
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tr 0 = 0.306 ns A = 0.59903 ns τ = 0.15014 ns
(8)
Fig. 14a also shows the fitting provided by the adjustment expression (6), as well as the value of adjustment parameters. Fig. 14b shows the relative error in the measurement of 1T for every point in the curve. It can be seen how the proposed expression accurately and precisely describes the metastable behavior with a maximum error below 4%. 5.
Comparison of Metastable Behavior in Static and Dynamic Latches
Once we have obtained an expression to evaluate the metastability window of a dynamic latch (6), we are going to make a comparison with its equivalent static latch. More precisely, the static latch considered here is that of Fig. 3, with the same inverter and switch geometries that we used for the dynamic latch (Table 1). In the previous section we gave a model for the metastable behavior of the dynamic latch, and a complete set of parameters was calculated (8). In a similar manner, the static latch must be modelled and its parameters calculated. As mentioned in Section 2, the metastability window of this latch responds to equation (1), that we reproduce here for convenience: 1T (tr ) = T0 e− τ
tr
(9)
The characteristic parameters for the static latch metastable behavior are, then, T0 and τ . As we did for the dynamic latch, the tr versus T curve for the static latch has been obtained from HSPICE simulations. Then, T0 and τ have been adjusted to match simulation results, yielding: T0 = 3.9576 ns τ = 0.18392 ns
(10)
The comparison regarding metastability between latches will be carried out by means of the MTBF (Mean Time Between Failures) calculation. It is well known that this function can be evaluated as [1, 8, 15, 28]: MTBF =
1 f D f C K 1T (tr )
(11)
where f D is the average data signal frequency, f C K the clock frequency and 1T the metastability window
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Fig. 13. tr versus T curve obtained by electric simulation.
width for a given tr . It is clear, from Fig. 15, that tr depends on f C K in the following manner: tr =
TC K 1 − t S + T (12) − tS + T = 2 2 fC K
where t S is the minimum time needed for the signal to be stable previous to the rising edge of the C K signal (setup time). In our case, we have estimated a value of t S = 0.5 ns. On the other hand, T is the parameter measuring the input marginal triggering. The operating frequency is considered to be between 20 and 200MHz. Taking into account equation (11) and the expressions of the metastability window width for both the static (8) and dynamic latch (6), the following expressions for MTBF are obtained for each latch: !−1 Ã 1 MTBF S = " MTBF D =
f D f C K T0 e− Ã
f D fC K
1T1 + Ae
−
2 fC K
−t S +T
(13)
τ
1 −t +T s 2 fC K τ
being MTBF S the value for the static latch and MTBF D for the dynamic one. Taking into account the considered frequency margins, we are going to do some approximations in the MTBF expressions for better handling. Thus, for the static latch, we are going to consider that T is approximately equal to T c, being T c the value indicating the center of the metastability window. The error introduced by this approximation is bound by 1T /2. The maximum value of 1T takes place for the minimum value of tr , that in our case is: tr =
1 − 0.5 ns = 2 ns 2 · 200MHz
The value of 1T for this value of tr is about 10−5 ns. Thus, the relative error committed in the evaluation of MTBF is: 1T 1(MTBF S ) = 2 = 0.02% MTBF S τ
!#−1 (14)
(15)
validating the approximation previously done.
(16)
Analysis of Metastable Operation
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Fig. 14. a) 1T2 versus tr curve. b) Relative error respecting to the adjustment expression.
With respect to the dynamic latch, the metastability window (4) presents two components: 1T1 which is constant and 1T2 which is exponential. Thus, for tr > 1 ns (this always happens in our operating frequency range), it is verified that 1T2 (tr > 1 ns) <
1T1 100
(17)
and hence, 1T2 is negligible in comparison with 1T1 . In this way, we can simplify the expression in equation (13), giving: MTBF D = ( f D f C K 1T1 )−1
(18)
With the purpose of obtaining a graphical representation of MTBF functions, we are going to consider a
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Fig. 15. tr calculation for a given f C K .
value of f D closely related to f C K in the following way: f D = α fC K
(19)
where α represents the average number of oscillations of the data signal within every clock cycle. As a typical value, we will use 1/16. Taking into account all the above-mentioned data and considerations, we have represented in Fig. 16 the MTBF functions versus f C K . This representation shows very prominent results: First, we can observe the incapacity of the dynamic latch to reach a MTBF value within the security margin considered (1000 years, 3×1010 s. approx.). This is due to the limiting character of 1T1 in the metastability window for this latch, yielding a large range of marginal triggering (from TC1 to TC2 ) for every tr , even when tr → ∞. The existence of 1T1 is unavoidable and is produced by the non-existence of a supply path to node VX in the dynamic latch of Fig. 2, when C K is inactive. For the static case, when C K is inactive, a positive feedback loop exists, so that the output evolves rapidly into a stable state. This fact always results in a finite resolution time (tr ) and therefore, generating 1T values rapidly tending to 0 as higher values of tr are allowed. Finally, analyzing Fig. 16, it is observed that the static latch operates within the security margin established for the MTBF function up to a working frequency close to 70 MHz. 6.
Conclusions
In this paper we have analyzed the metastable behavior of a CMOS dynamic latch (Fig. 2) under different input marginal triggering.
We have stated the existence of an input timing interval providing a resolution time higher than the normal resolution time (tr > tr 0 ). For this reason and based on the analogy with the static case, this anomalous behavior is called metastability in dynamic latches. This interval determines the existence of a metastability window, similar to the one existing in the static latches, due to their metastable behavior. A theoretical analysis has been performed and verified by electrical simulation. From this analysis, the shape and location of the metastability window for the dynamic latch has also been obtained. The most prominent feature of this window is that, unlike metastability windows in static latches, a clearly defined input interval exists producing tr = ∞. As result of the theoretical analysis, we have obtained expressions allowing the calculation of the width of that interval. On the other hand, there exists a region where tr is higher than tr 0 but finite. For this region, we propose an adjustment expression. Once the curve is adjusted, we have shown that the proposed expression accurately and precisely describes the behavior within this region with a maximum deviation below 4%, obtained by electrical simulation. Finally, once the metastable behavior in dynamic latches was characterized, we have compared this latch with its static counterpart in terms of metastability. To do this, we have previously characterized the static latch, obtaining the values for the characteristic parameters and, after that, we have evaluated the MTBF as a function of the clock frequency (Fig. 16). The obtained result has been very conclusive in the sense that the dynamic latch presents a very low MTBF (below 1 second) even at a relatively low operating frequency (20 MHz), while the static one shows an exponential variation giving a very high value of MTBF (1050 seconds) for those low frequencies, and is decreasing in such a way that for frequencies of about 200 MHz, the MTBF is below 1 second. Considering a security margin for the MTBF of 1000 years, the static latch operates correctly up to a frequency of 70 MHz. The reason for this result lies in the shape of the 1T vs. tr plot. In the static latch, the metastability window width is decreasing down to 0 as the resolution time increases (decreasing frequency), while for the dynamic latch there is a minimum metastability window width, different from 0, for every tr . In conclusion, these results show that dynamic latches should not be used in those circuits where the risk of asynchronism between clock and data signals is
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Fig. 16. MTBF curves versus f C K .
not negligible. This situation occurs in synchronizers or in those points in synchronous circuits where clock skew and delays in data signals are probable. Acknowledgment This work has been sponsored in part by the CICYT under Project TIC-95-0094. References 1. L. Kleeman and A. Cantoni, “Metastable behavior in digital systems.” IEEE Design and Test of Computers 4, pp. 4–19, December 1987. 2. T. J. Chaney, S. M. Ornstein and W. M. Littlefield, “Beware the synchronizer,” in IEEE COMPCON-72, San Francisco, California, Sept. 1972. 3. T. J. Chaney and C. E. Molnar, “Anomalous behavior of synchronizer and arbiter circuits.” IEEE Trans. on Computers 22(4), pp. 421–422, April 1973. 4. W. Fleischhammer and O. Dortok, “The anomalous behavior of flip-flops in synchronizer circuits.” IEEE Trans. on Computers 28(3), Mar. 1979. 5. M. Hurtado, “Structure and performance of asymptotically bistable dynamical systems.” Ph.D. dissertation, Sever Institute of Technology, Washington Univ., St. Louis., 1975.
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Jorge Juan-Chico received the B.Sc. degree in Electronic Physics in 1994 from the University of Seville,
Spain. Since 1995 he is a Ph. D. student with the Institute of Microelectronics of Seville (CNM-CSIC) and also with the Department of Electronic Technology of the University of Seville, supported by a grant from the government. His current research activities are in the field of CMOS Digital VLSI Design, timing problems and synchronization in VLSI digital systems and logic level delay modelling for high speed digital circuits.
´ Bellido-D´ıaz received the B. Sc. deManuel Jesus gree in 1987, the M. Sc. degree in 1989 and the Ph. D. degree in 1994 in Electronic Physics, from the University of Seville, Spain. He is currently with the Institute of Microelectronics of Seville (CNM-CSIC) and also with the Department of Electronic Technology of the University of Seville, where he is employed as Associate Professor since 1996. His current research interests are in the areas of CMOS Digital VLSI Design, timing problems and metastability in VLSI digital systems and logic level delay modelling for high speed digital circuits.
Antonio Jos´e Acosta-Jim´enez received the B. Sc. degree in 1989, the M. Sc. degree in 1991 and the Ph. D. degree in 1995 in Electronic Physics, from the University of Seville, Spain. He is currently with the Institute of Microelectronics of Seville (CNM-CSIC) and also with the Department of Electronics and Electromagnetism of the University of Seville, where he is employed as Assistant Professor since 1992. His current research interests are in the areas of CMOS Digital VLSI Design, VHDL description and modeling, description of timing phenomena in VLSI
Analysis of Metastable Operation
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digital system, asynchronous and self-timed circuits and multiple-valued circuits.
metastability problems and related issues and asynchronous and self-timed circuits.
Manuel Valencia-Barrero received the B. Sc. degree in 1976, the M. Sc. degree in 1977 and the Ph. D. degree in 1986 in Electronic Physics, from the University of Seville, Spain. He is currently with the Institute of Microelectronics of Seville (CNM-CSIC) and also with the Department of Electronic Technology of the University of Seville, where he is employed as Associate Professor since 1987. His current research interests are in the areas of CMOS Digital VLSI Design, description of timing phenomena in VLSI digital system with emphasis in
Jos´e Luis Huertas-D´ıaz received the B. Sc. and the Ph. D. degree in Physics in 1969 and 1973, respectively, both from the University of Seville, Spain. From 1970 to 1971, he was with the Philips International Institute, Eindhoven, The Netherlands, as a postgraduate student. Since 1971, he has been with the Department of Electronics and Electromagnetism of the University of Seville, where he is a Full Professor. He is also the Director of the Institute of Microelectronics of Seville, CNM-CSIC. His current interests include the design and testing of analog/digital integrated circuits, computer-aided IC analysis and design, fuzzy logic, nonlinear microelectronics and neural networks.