Microelectronic Processing Overview

Copper Interconnects for Semiconductor Devices Sailesh M. Merchant, Seung H. Kang, Mahesh Sanganeria, Bart van Schravendijk, and Tom Mountsier Copper/low-k dielectric materials have been rapidly replacing conventional aluminum-alloy/SiO 2-based interconnects in today’s semiconductor devices. This paper reviews the advantages of transitioning to copper/low-k interconnects. Materials and process challenges during the fabrication of devices with copper/low-k interconnects are discussed. Reliability concerns associated with such devices are highlighted. INTRODUCTION For the last thirty years, aluminum alloy metallization has remained the workhorse of the semiconductor industry in fabricating interconnects for the production of integrated circuits. Aluminum alloys have low resistivity (3.0– 5.0 mW-cm) and are amenable to lowcost, high-throughput fabrication processes. Because these alloys are able to form a passivating oxide film, they can be easily patterned and etched. Moreover, aluminum alloys show good adhesion to most dielectrics used in the industry. While early devices were made with an all-aluminum-alloy metallization scheme, much of the industry migrated to tungsten plugs for contact and via fill at the 0.5 mm technology node, and aluminum alloys served only as interconnects. When used in conjunction with refractory cladding materials such as titanium and titanium nitride (TiN), aluminum alloys exhibit enhanced reliability such as resistance to stress-induced voiding and electromigration. Therefore, the industry has opted to stay with aluminum alloy metallization and has extended the life of aluminum alloys to the 0.25 mm technology node. With ever-increasing demands to shrink dimensions of microelectronic devices, interconnect scaling has made limited advances in high-performance integrated circuits.1–3 Interconnect resistance and capacitance (also known as RC-product) have become important parameters in determining integrated circuit design, design rules, packing density, and device performance. For sub0.25 mm technology, the interconnect RCproduct, not the intrinsic gate delay, has become dominant in determining overall device performance. Interconnect delays must be minimized due to everincreasing needs for faster devices with low power consumption.4 2001 June • JOM

Increasing RC values have prompted a flurry of activity in the design and process communities. To lower the capacitance, new insulators and methods of processing with materials having lower dielectric constants (k < 4) have shown promise. To lower the resistance of metal lines, the industry turned to a material of lower resistivity, namely copper, with a resistivity less than 2 mW-cm. Reductions in both the dielectric constant and metal resistivity have helped reduce the number of metal layers required for optimal chip performance. Circuit-design models have helped identify critical path interconnects, provide optimal layouts, and avoid over-design. Nowhere have improvements in the RCproduct been more useful than in highperformance devices such as microprocessors. The requirements of such devices have necessitated drastic changes in interconnect materials and, in response, the industry has been quick to adopt copper as an alternative to aluminum alloys. Copper was first reported to be an alternative to aluminum alloy metallization in the fabrication of integrated circuits in 19975,6. Since then, knowledge of process requirements and reliability issues associated with copper interconnects has grown significantly. This paper reviews process and materials issues associated with the fabrication of silicon semiconductor devices containing copper interconnects. FABRICATION PROCESSES FOR COPPER INTERCONNECTS With the introduction of copper metallization, new fabrication processes

Figure 2. A general dielectric stack used in dual damascene process flow.

have been introduced in the manufacturing line. For example, metal etch processes, critical for aluminum alloy interconnects, have been completely eliminated. However, newer processes such as damascene and dual damascene fabrication and electroplating have created new challenges for the process engineer. The most common process integration steps to form copper interconnects are5,12,13 • Deposit the damascene or dual damascene interlevel or intermetal dielectric. This dielectric may be multi-layered and may include etch stops such as silicon nitride. The dielectric may require a planarization step using CMP. • Pattern and etch the damascene or dual damascene structure into the dielectric. • Fill the openings with electrodeposited copper. A barrier/seed stack is deposited prior to electrodeposition. • Anneal the wafers to stabilize the microstructure and avoid secondary recrystallization effects. • Polish the excess copper and barrier away using CMP. • Repeat steps 1 through 5 for multilayered interconnects. • Passivate the final Copper layer, and prepare the chip for packaging and assembly. Successful integration of copper into a dual damascene structure requires several critical steps that will be discussed in the next sections. DIELECTRIC FILM DEPOSITION

Figure 1. Relationship between dielectric constant and hardness of dielectric materials.

The most commonly used dielectric material in multilevel metallization is undoped silicate glass (USG) with a nominal dielectric constant of 4.1. As the industry moves from the 0.25 mm technology node to 0.18 mm, some semicon43

Figure 4. Illustration of effect of substrate type on resist profile.

a

b Figure 3. Normalized effective dielectric constant as a function of diffusion barrier thickness (a) with etch stop, and (b) without etch stop.

ductor manufacturers have used fluorinated silicate glass (FSG) films to reduce the dielectric constant to between 3.6 and 3.8. FSG presents serious integration challenges due to its susceptibility to moisture absorption, however, the mechanical strength of FSG is sufficient to enable successful integration. Also, FSG can be deposited in a conventional plasma-enhanced chemical vapor deposition (PECVD) reactor or in a high density plasma chemical vapor deposition reactor with minor modifications. For the 0.13 mm technology node, a dielectric material with a bulk dielectric constant of 2.7 is required.14 The preferred material to meet this requirement has been organo-silicate glass (OSG) or carbon-doped silicate glass. This material, however, is markedly different from USG. OSG can be deposited to give a wide range of dielectric constant values, but as the dielectric constant decreases, hardness decreases concomitantly. Lower hardness films present serious integration challenges as a result of lower adhesion to other films, CMP incompatibility, dimensional instability, and problems in packaging. Figure 1 shows the relationship between hardness and dielectric constant of some known dielectric materials being used or evaluated for multilevel metallization. The challenge in determining the film of choice is maximizing hardness for a given dielectric constant. Two main factors determine the hardness of low-k material: the precursor for deposition and the deposition method. As seen in Figure 1, a commercially avail44

able OSG film produced using a proprietary precursor, SiCOH A (CORALTM), provides a harder film compared to films prepared using tetra-methyl silane (4MS)/tri-methyl silane (3MS) as a precursor. For the same dielectric constant, film deposited using the proprietary precursor has less carbon compared to film deposited using 4MS/3MS. As a result, higher hardness is achieved for the proprietary precursor at the same value of dielectric constant. On the other hand, as shown in Figure 1, the hardness of a polymeric film produced using spinon technique is substantially lower than the films produced by PECVD. DIELECTRIC FILM STACK

1,000 Å. The diffusion barrier and etchstop material was assumed to be Si3N4 with a dielectric constant of 7.0. The simulations were performed with via and trench dielectric materials with dielectric constants 2.2, 2.7, 3.5 and 4.1 representing four nodes of technology. As shown in Figure 3a–b, the effective dielectric constant increases as the diffusion barrier and etch-stop thickness is increased. Also, the increase in effective dielectric constant is substantially more when the etch-stop layer is present. For example, for a material with a dielectric constant of 2.2, the increase in effective dielectric constant is 47% when both etch stop and diffusion barrier layers are present, however, the increase is only 23% when the etch-stop layer is not present. Also, it is clear from Figure 3a that the effect of diffusion barrier and etch stop is more pronounced when the dielectric constant of the trench and via dielectric is lower. The fourth layer in the dielectric stack shown in Figure 2 is the trench dielectric. The dielectric constant of this material is the most important parameter in determining the RC delay of the circuit. As deposited film dielectric constant and any modification during subsequent processing should be carefully controlled to achieve the desired device speed. The final and the topmost layer is the cap layer. It may be used in the stack for several reasons—as an anti reflective coating, as a stop layer for metal CMP, and/or as an etch-stop layer during via etch to counter resist consumption. Again, all efforts are being made to avoid using a cap layer, or remove it before the deposition of subsequent layers to reduce the effective dielectric constant of the film stack.

Figure 2 shows a general dielectric stack used in the dual damascene process flow. The bottom layer is used both as a copper-diffusion barrier and as an etch-stop layer for via etch. Materials being used for this application are PECVD silicon nitride (Si3N4) and silicon carbide (SiC). The Si3N4 can be deposited with a dielectric constant in the range of 6.5 to 7.0 whereas much lower dielectric constants in the range of 4.0 to 4.5 can be achieved for SiC. The next layer from the bottom is the via dielectric layer. The third layer is used as trench etch stop (ES). Usually the same material is used for the diffusion barrier and the etch stop. This etch-stop layer provides a good trench bottom profile. Efforts are being made to eliminate ES layer to obPATTERNING OF DUAL tain lower effective dielectric constant. DAMASCENE STRUCTURES Elimination of the ES layer will require The formation of dual damascene improving the trench etch process to structure requires two lithography steps: provide a flat bottom profile without the defining via and defining the trench. ES layer. The significance of eliminating Dual damascene structures have been a the trench etch stop layer is illustrated in Figure 3, which shows the normalized effective dielectric constant as a Unexposed Pad Area function of the diffusion barrier layer and/or ES film thickness embedded in materials with different dielectric constants. Exposed Pad Area The effective dielectric constants were calculated using the Raphael simulation software package.15 The total dielectric stack thickness ▲ was maintained at 1.0 mm for all cases. The diffuPoisoned Photoresist 26 mm sion barrier and etch-stop layer thickness used Figure 5. Plan view SEM illustrating poisoned resist in via after trench lithography. were 0, 500 Å, 700 Å, and JOM • June 2001

key enabling technology for advancement of the use of optical lithography for today’s semiconductor devices.16–18 To address depth-of-focus issues, optical proximity correction and phase-shifting masks are being increasingly utilized in extending the present lithography tool capabilities. The industry is now working on the next generation 193 nm and 157 nm tools that will allow printing down to the 0.07 mm node using optical lithography.19 Deep ultra violet (UV) photoresist is being used for 0.13 mm technology node where low k dielectric material is being introduced. Deep UV photoresist uses chemical amplification which makes it very sensitive to the substrate. Chemical amplification requires the right amount of photo-generated acid atoms. A basic substrate can cause resist footing by depleting photogenerated acid, whereas an acidic substrate can result in resist pinch-off by supplying more acid than needed, as illustrated in Figure 4.20 This problem is exacerbated during trench lithography, where the photoresist fills via holes. Basic contaminants, primarily amines in the as-deposited film or incorporated in the film during subsequent processing, diffuse into the photoresist and neutralize the photo-generated acids necessary for resist development. This neutralization of photo-generated acids, also known as resist poisoning, Results in resist caps remaining in via holes even after the resist development process. Figure 5 shows a top view scanning electron micrograph of an array of vias in the pad area after trench lithography. The hemispherical shaped resist remaining in vias after trench lithography is the result of resist poisoning.

The consequence of resist poisoning during trench lithography is illustrated schematically in Figure 6. Figure 6 shows a cross-section through a via chain link at three stages of dual damascene process flow: after trench lithography, after trench etch, and after resist strip. Figure 6a represents the case when resist poisoning is present. In this case, the poisoned resist looks like a mushroom in the cross-section. The mushroom-shaped photoresist will mask the dielectric during trench etch. Figure 6b shows the desired resist profile for a via chain link without the resist poisoning. It is clear from the previous illustration that resist poisoning must be eliminated for the formation of a successful dual damascene structure. It should be noted that low-k materials are prone to resist poisoning because of their porous nature. They tend to absorb contaminants during various processing steps that subsequently poison the deep UV photoresist. Copper metallization and low dielectric constant materials have created numerous challenges for plasma-etch process engineers.21,22 A plethora of new interconnect integration schemes and new dielectric materials must be etched. Furthermore, as the new interconnect systems are applied to advanced technology nodes with ultra-high packing density, these systems often require etch processes to perform at unprecedented feature-aspect ratios and degree of dimensional control. When copper metallization is applied in conjunction with a conventional SiO2 dielectric in a dualdamascene scheme, there are several key challenges. Often, Si3N4 is used as a barrier over the copper interconnect to which the etched vias will connect, and is also

used as a trench etch-stop layer in some schemes. As the dielectric constant of Si3N4 is significantly higher than SiO2, or low k, materials, the Si3N4 layers should be made as thin as possible. Thus, etch processes must, in general, possess quite high selectivity with respect to Si3N4. Furthermore, while removing the barrier Si3N4, great care must be taken to avoid oxidizing and/or sputtering the copper underneath. When other materials are used for etch-stop and barrier layers, the above constraints on the dielectric etches still apply. Besides OSG materials, polymeric materials are also candidates for advanced interconnect systems with low dielectric constants. In these materials, carbonaceous material in the film must be volatilized in order to effect the etch process. This requirement typically reduces selectivity with respect to photoresist. In the case of polymeric materials, the solution is to utilize a hard mask (typically SiO2) alone or in conjunction with a resist mask. Chemistries typically used to etch polymeric films include nitrogen mixed with hydrogen or oxygen. Often, a passivant gas is added as well, typically in the form of CxHy, which aids in producing an anisotropic etch. Etch chemistries for OSG materials are generally based on an oxide etch recipe, which utilizes fluorocarbons and hydrofluorocarbons as the primary etchants, with an extra gas added to form volatile compounds with carbon. This carbon-volatilizing additive is chosen so that it will not attack the sidewall passivation in the etched feature. Such an attack would render the etch process isotropic. A common practice to remove photoresist after etch is to subject the wafer to

BACKGROUND ON COPPER INTERCONNECTS Because copper’s resistivity is lower than that of aluminum alloys, it allows higher current densities, even for reduced cross-sections of conductors. More importantly, copper metallization has shown a dramatic improvement (10 –100X) in resistance to electromigration5– 8 and stress-induced voiding.6 A new approach to create inlaid structures of copper using damascene or dual damascene methods9 has made fabrication of devices with copper feasible. The availability of low cost, highthroughput processes such as electroplating has permitted the fabrication of these in-laid structures. Moreover, once the industry completely migrates to copper, fabricating devices with copper will likely be cheaper than ones with the conventional W/Al alloy metallization. However, selecting copper as an interconnect metal is difficult for the following reasons: ∑ Copper diffuses very rapidly in silicon and conventional dielectrics, and if not checked, can cause severe threshold-voltage shifts and junction leakage. Because copper can cause inter- and intralevel shorts, it must be encapsulated on all sides with barrier layers. The encapsulation has to be repeated for all levels of copper metallization. ∑ Copper lines cannot be easily patterned like those made of aluminum alloys. The lack of volatile byproducts does not allow easy etching of copper lines using conventional (subtractive) reactive ion

2001 June • JOM

etch techniques. Therefore, damascene or dual damascene fabrication techniques have become mandatory for fabricating devices with copper. ∑ Unlike aluminum, copper does not form a selfpassivating oxide, so it readily oxidizes (and corrodes) even in the clean room ambient at low temperatures. Thus copper exposed at the top of vias or trenches needs to be protected. This oxide must be removed (or at least reduced) prior to making connections to other metal layers. ∑ Copper is an aquatic toxin and therefore, several environmental, health, and safety issues need to be addressed.10 Copper-containing liquids such as slurry from chemical-mechanical polishing (CMP), consumed electroplating solution, and rinse water must be properly handled during waste disposal and suitable effluent treatment equipment is required.

Copper Protocol and Contamination Another potential drawback of copper metallization is contamination. A device-fabrication line should be dedicated to copper processing; aluminum-alloy metallization should be conducted in a separate line. Otherwise, manufacturing protocol will have to be re-engineered to control copper contamination in the line.11 Although front-end tools may be shared for both conventional

aluminum-alloy processing and copper, copper-dedicated tools are recommended after damascene structures have been formed at the first dielectric level. All metrology tools that are used to measure coppercontaining wafers must be dedicated, and other tools in the line that do not process copper wafers must be monitored routinely for copper contamination. For example, routine monitoring of wet benches, gate oxide and diffusion furnaces, and associated front-end metrology tools becomes mandatory. To save money, some fabrication lines share lithography tools for copper and aluminum back-end metallization. Again, copper levels in these tools must be carefully monitored when switching between copper and non-copper processing modes. A wafer backside barrier material such as silicon nitride is recommended. Any thermal exposure of the wafer during routine processing may cause copper to migrate through the wafer backside into the active regions of devices. Copper-dedicated cassettes and boxes for copper-containing wafers are suggested. Analytical facilities need to be updated with tools that accurately measure copper contamination levels. Moreover, all fabrication line personnel must be trained, and an escalation procedure established, to cope with contamination. Information systems used for lot tracking and wafer management need to be modified to help minimize the risk of contaminating non-copper equipment.

45

a high pressure (approximately 1 torr) oxygen plasma in the etch tool. However, this technique cannot be used for OSG materials. Oxygen reacts with the carbon in OSG film and depletes the film of carbon, which may result in severe cracking of the film. Figure 7 shows a secondary ion mass spectroscopy (SIMS) profile of oxygen, carbon, and silicon through an OSG film subjected to an oxygen plasma treatment in an ashing reactor. The SIMS profile clearly shows substantial carbon depletion in the top 0.2 mm OSG film. These results suggest that conventional ashing technique cannot be used for OSG material. BARRIER AND SEED LAYERS The barrier materials for copper that have been reported are generally refractory metals or refractory metal nitrides. Early studies used TiN as a barrier stack,5,23 but now most companies have settled on tantalum-based barriers. Of these, tantalum24 and TaN25,26 are the most common materials used today and are typically deposited using hollow cathode magnetron27 or ionized metal plasma (IMP) deposition.26 Other materials such as tungsten nitride and ternary refractory barriers such as Ta-Si-N have also been investigated.28 A comparison of tantalum, TaN, and Ta-Si-N barriers for copper interconnects has been recently reported.29 A listing of various barriers for copper from previous studies is discussed in Reference 30. Although the resistivity of copper is significantly lower than that of aluminum alloys, the effective resistance of a copper line is determined by the actual cross-section of the line itself. Therefore, barriers used for encapsulating copper must be as thin as possible and those with high resistivity should be avoided.

An ideal barrier must be free of defects, smooth, continuous, and conformal at minimal thickness. The barrier must have good adhesion and show no interaction with dielectrics and the seed layer. In some cases, an adhesion layer may be deposited prior to barrier-layer deposition. The barrier must be CMP-compatible and should not delaminate or crack because of mechanical stresses during processing. A dense, amorphous barrier is preferred to avoid fast diffusion paths for copper, such as grain boundaries. The barrier behavior of TaN to copper interdiffusion has been studied.26 The authors show that TaN resistivity and composition can be tailored by adjusting the nitrogen flow introduced into the plasma during deposition. Barrier behavior of TaN films was studied by fabricating capacitor structures with copper and tested at 2MV/cm at temperatures between 200–275∞C. TaN films show good barrier performance in these test conditions. The importance of adequate seed conformality and coverage cannot be overemphasized. If the seed coverage in a dual damascene structure is discontinuous, then feature fill during copper electroplating becomes difficult and voids will typically be observed along the feature sidewalls. As the industry migrates towards high aspect-ratio openings, conventional barrier/seed deposition techniques such as IMP will likely be inadequate to provide conformal coverage in features. Therefore, process engineers are trying to use chemical vapor deposition (CVD) methods for barrier and seed layer formation. A recent study31 has shown complete feature fill using CVD-WN and CVDcopper prior to copper electroplating in 0.18 mm diameter features with an aspect ratio of 9:1. Recently, chemical vapor deposition techniques have been used to deposit TiSi-N as a barrier material to allow conformal coverage in dual damascene structures. ELECTROPLATED COPPER

a

b Figure 6. Schematic cross section of a via chain link after trench lithography, trench etch and resist strip: (a) with resist poisoning and (b) without resist poisoning.

46

Copper sulfate-based electrolytes are used to electrodeposit copper in damascene or dual damascene features.31 A variety of chemicals such as inhibitors, accelerants, and brighteners, added to the bath for improved and consistent fill, make understanding feature fill mechanisms difficult. Moreover, control of these additives, including the copper concen-

Figure 7. SIMS profile of oxygen, silicon, and carbon of an OSG film exposed to high pressure oxygen ashing chemistry showing carbon depletion.

tration of the bath, becomes critical. Onboard closed-loop analysis and chemical replenishment systems are now commercially available that make bath chemistry control a routine operation.31 Feature-fill mechanisms have been reviewed.32 Of these, superfilling, or filling of vias or trenches from the bottom up rather than from the sidewall, is defined to be the ideal fill technique. Significant improvements in the fill capability have been reported by optimizing plating waveform and custom additive chemistry.33 It was shown that fill in high aspect-ratio via was limited due to the formation of bottom and center void defects. These defects were eliminated by improving the bottom-up selectivity of the plating process. Electrodeposited copper films are unique in that a dramatic evolution of film microstructure is observed at room temperature immediately following deposition. This microstructural change, referred to as secondary recrystallization,34 includes an increase in grain size, a decrease in resistivity and hardness, and changes in stress, with a high degree of twinning. Moreover, changes in preferred crystallographic texture (orientation) of the deposited film have been observed. 35 Texture in damascene trenches has been investigated.34,36,37 These changes in microstructure have been attributed to high stress and dislocations in the film, which in turn are related to additives in the electroplating process.34–37 It is advisable to include an intermediate anneal step to present a consistent microstructure for CMP processing after electroplating copper. RELIABILITY It has been recognized that copper is superior to aluminum against electromigration (current-induced diffusion), which has been a major reliability concern in the manufacturing of microelectronic interconnects. Copper, with lower resistivity than aluminum, in principle can provide higher electric currents for a given voltage, leading to a faster inteJOM • June 2001

grated circuit (IC) without sacrificing its reliability against electromigration. However, this anticipated electromigration reliability is often difficult to achieve as the industry migrates to sub-0.2 mm wide copper lines integrated with ultrathin diffusion barriers and low-k dielectric materials. In addition, the useful lifetime of the IC can be limited by other reliability concerns, such as copper diffusion in surrounding dielectrics, mechanical instability, corrosion, and Joule heating. This paper addresses some of the reliability issues related to electromigration and time-dependent dielectric breakdown under bias-temperature stress (BTS). Prior work reported that the mean time-to-failure for copper interconnects (used for 0.25 mm technology) was about two orders of magnitude longer than that for aluminum alloy when they were tested at current density, J = 2.5 MA/cm2 and temperature, T = 295∞C.6 This result

Time to Failure (h)

a

Time to Breakdown (s)

b Figure 8. Cumulative probability plot for electromigration failure and bias temperature stress failure showing early failures.

2001 June • JOM

is encouraging and may justify a higher current operation at chip-use conditions (T approximately 110∞C) provided that the following criteria are satisfied. First, the activation energy and the currentdensity acceleration factor for copper electromigration are comparable with those for aluminum alloys. Second, the failure-time distribution (described by a log-normal curve) for copper is as narrow as that for aluminum alloy, that is, the deviation in time-to-failure (known as s) for copper is comparable with that for aluminum alloy. These criteria necessitate an identification of a primary electromigration failure mechanism and an understanding of its sensitivity to microstructural and process variations. However, the electromigration mechanism for damascene copper interconnects is not clearly understood. Recently, Hu et al.38 have reported that, in the case of narrow copper interconnects, surface diffusion (e.g., along the copper-SiN overlayer interface), rather than grainboundary diffusion or intermetallic interface diffusion (e.g., along the copperdiffusion barrier interface), acts as a dominant electromigration mechanism.38 They have also reported that the activation energy of surface diffusion is 0.9 electron-volt (eV). This activation energy is larger than the activation energy of aluminum alloy for grain-boundary diffusion (0.7 eV), comparable to that for interface diffusion (0.9–1.0 eV), but smaller than that for lattice diffusion (1.2 eV). It follows that, for bamboo lines where grain boundaries are not active diffusion pathways, copper does not have an advantage over Al(Cu) from the activation-energy perspective. Furthermore, the activation energy for copper electro-migration can even be lower than 0.9 eV if the quality of the copper surface with respect to surrounding materials is poor.39 For aluminum-based interconnects, it is well recognized that a refractory layer like TiN and titanium is incorporated to conduct electricity in the presence of a void (known as a current-shunting effect). This film is about 30–50 nm thick and coats the top and bottom surfaces of the aluminum line. To improve electromigration reliability, it is critical to control the sheet resistance and the thickness of the refractory film since the rate of resistance increase due to voiding is greatly affected by the architecture and physical properties of the film.40 In addition, this refractory film must be defect-free since any discontinuity, for example, a micro crack, will lead to a catastrophic resistance increase in the presence of a void. Similarly, the sidewall and bottom surfaces of the copper line are coated with a barrier film like Ta or TaN to prevent copper diffusion through dielectric films. This diffusion barrier also serves as a current-shunting layer.

However, this diffusion barrier is much thinner than the films used for aluminum; its actual thickness along the sidewall and bottom of the copper trench is often less than 10 nm. Hence, its current-shunting effect is rather limited so that the rate of resistance increase due to voiding for copper interconnects is larger than the rate for aluminum. Consequently, the size of a void that causes failure is substantially smaller for copper interconnects than that for aluminum interconnects. It is expected that this will become a more serious problem for ICs with smaller feature sizes. Copper metallization must also be reliable against time-dependent dielectric breakdown under bias-temperature stress (BTS). It has been well recognized that copper ions can rapidly diffuse through dielectrics to cause a short circuit. This is a concern particularly with an integration of low-k dielectric materials since their dielectric breakdown strength appears to be lower than that of SiO2. To prevent copper diffusion under BTS, the diffusion barrier must maintain its functional integrity throughout the useful lifetime of the IC. It seems that, however, incorporating only a diffusion barrier is not sufficient to ensure the metallization reliability against timedependent dielectric breakdown. Prior work reported that a preferable path for copper diffusion is along the interface between the intra-level dielectric (ILD) surface and the passivation layer (capping layer).41 Therefore, it is critical to achieve a defect-free copper and ILD surface particularly through chemicalmechanical polishing and the passivation-layer deposition. It is also essential to maintain good adhesion between these layers, even under BTS. Finally, one of the most difficult reliability challenges in copper interconnect manufacturing is to control early failures. The existence of early failures is sensitive to process stability and variations. As illustrated in Figure 8, in some cases, electromigration and BTS failure distributions are bimodal due to the existence of early failures. Note that the reliability of a chip against electromigration or BTS failure is determined by the time at which the first failure in a large set of lines occurs. The reliability margin is then usually set to 0.01% or 0.1% cumulative failures. Hence, an increase in mean time-to-failure does not necessarily reflect a reliability improvement. To ensure a high value of the time to first failure, a method to improve the reliability must be one that not only eliminates early failures, but also promotes a narrow failure distribution. CONCLUSION The future of copper interconnects for semiconductor devices is promising, but some difficulties will have to be over47

come. With decreasing dimensions and increasing aspect ratios of dual damascene structures, the barrier/seed coverage will be an issue. Therefore, ultrathin, low resistivity amorphous barrier layers, compatible with low-k dielectrics, will be required. Minimal contact resistance requirements will drive equipment trends toward increasing in-situ methods of deposition. Significant advances in electroplating tool chemistry and the use of seed repair techniques are envisioned for the immediate future, as are plating tools with multi-step recipes. On-board bath monitoring and replenishment techniques will be commonplace. The selection of low-k materials will most likely be based on process integration issues rather than material properties, facilitated by the advent of newer etch chemistries. Newer CMP slurry formulations and pad designs to minimize topography effects, dishing and erosion will be required. Optical lithography techniques are envisioned to serve till at least the 0.10 mm technology node, with phase-shift masks and optical proximity correction schemes being routine. The system-on-a-chip concept will allow integration of other devices, not just

stand-alone microprocessors, where copper/low-k materials will be mandatory. Copper metallization will become routine for application-specific integrated circuit applications and will be introduced in dynamic random access memory. All these advancements will be feasible only with decreased tool and consumable costs, as copper enters the manufacturing mainstream for advanced technologies and completely replaces aluminum alloys. ACKNOWLEDGEMENTS The authors would like to acknowledge the efforts of colleagues, peers and management at Agere Systems and Novellus Systems, Inc. Novellus authors would like to acknowledge the Customer Integration Center at Novellus Systems, Inc. for help with copper/ low-k integration work. References 1. M. Bohr, Solid State Technology, 39 (9) (1996), p. 105. 2. C.S. Chang et al., Proc. IEEE-IITC (1998), p. 3. 3. X.W. Lin and D. Pramanik, Solid State Technology, 41 (10) (1998), p. 63. 4. S.C. Sun, Proc. IEEE-IEDM (1997), p. 765. 5. S. Ventakesan et al., Proc. IEEE-IEDM (1997), p. 769. 6. D. Edelstein et al., Proc. IEEE-IEDM (1997), p. 773. 7. J. Slattery et al., Future Fab, 6 (1998), p. 155. 8. C.K. Hu et al., Mater. Chem. Phys., 52 (1998), p. 5. 9. C.W. Kaanta et al., Proc. VMIC, 144 (1991). 10. L. Mendicino and P.T. Brown, Semicond. Int., 21 (6) (1998), p. 105.

11. T. Cacouris, Micro, 43 (July/August 1999). 12. P. Singer, Semicond. Int., 20 (9) (1997), p. 79. 13. P. Singer, Semicond. Int., 21 (6) (1998), p. 91. 14. Int. Technology Roadmap for Semiconductors, 2000 update (San Jose, CA: Semiconductor Industry Association, 2000). 15. RaphaelTM, Interconnect Analysis Software (Fremont, CA: Avant! Corp., 1998). 16. P.J. Silverman, Future Fab Int., 7 (1999), p. 127. 17. J.A. McClay and J.J. Shamaly, in Ref. 16, p. 135. 18. A.M. Goethals and K. Ronse, in Ref. 16, p. 143. 19. J.A. McClay and A.S.L. McIntyre, Solid State Technology, 42 (6) (1999), p. 57. 20. C.P. Soo et al., IEEE Trans. Semiconductor Manufacturing, 12 (4) (1999), p. 462. 21. P. Singer, Semiconductor International, 22 (9) (1999), p. 68. 22. I. Morey and A. Asthana, Solid State Technology, 42 (6) (1999), p. 71. 23. K. Park et al., J. Appl. Phys., 80 (1996), p. 5674. 24. I. Hashim et al., Proc. SPIE, 3508 (1998), p. 58. 25. T. Oku et al., Appl. Surf. Sci., 99 (1996), p. 265. 26. B. Chin et al., Solid State Technology, 41 (7) (1998), p. 141. 27. K.A. Ashtiani et al., Proc. IEEE-IITC (2000), p. 37. 28. M. Nicolet et al., Appl. Surf. Sci., 91 (1995), p. 269. 29. Q-T. Jiang et al., Proc. IEEE-IITC (1999), p. 125. 30. C. Ryu et al., Solid State Technology, 42 (4) (1999), p. 53. 31. A.E. Braun, Semiconductor Int., 22 (4) (1999), p. 58. 32. P.C. Andricacos, Interface, 8 (1) (1999), p. 32. 33. J. Reid et al., Proc. Adv. Metall. Conf., 99 (1999), p. 284. 34. C. Lingk et al., J. Appl. Phys., 84 (10) (1998), p. 5547. 35. J.M.E. Harper et al., J. Appl. Phys., 86 (5) (1999), p. 2516. 36. C. Lingk et al., Appl. Phys. Lett., 74 (5) (1999), p. 682. 37. M.E. Gross et al., Solid State Technology, 42 (8) (1999), p. 47. 38. C.-K Hu et al., Appl. Phys. Lett., 74 (1999), p. 2945. 39. J.R. Lloyd et al., Microelectronics Reliab., 39 (1999), p. 1595. 40. S.H. Kang et al., Solid-State Electronics, 45 (2) (2001), p. 342. 41. S.U. Kim et al., Proc. IEEE-IRPS. (1999), p. 277.

Sailesh M. Merchant and Seung H. Kang are with Agere Systems in Orlando, Florida. Mahesh Sanganeria, Bart van Schravendijk, and Tom Mountsier are with Novellus Systems in San Jose, California. For more information, contact S.M. Merchant, Agere Systems, Orlando, Florida 32819; (407) 371-7538; agere.com.

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Surface Mail Outside U.S.

$115.00

$204.00

Surface Mail Outside U.S.

$134.00

$241.00

Air Mail Outside U.S.

$135.00

$224.00

Air Mail Outside U.S.

$154.00

$261.00

$95.00

$184.00

Electronic Only Subscription Name

Method of Payment ❑ Check or Money Order Enclosed

Organization Dept./Bldg. Street Address

❑ Bank Transfer (wire payment to PNC, routing number 043000096, for the account of TMS, number 1008259767. For reference, include your name and transfer date.) Charge my: ❑ VISA

❑ Master Card ❑ American Express ❑ Diners Club

City Cardholder’s Name State/Province Zip/Postal Code Country Telephone Fax E-Mail

48

Account Number Signature

Expiration Date

Orders should be sent to: TMS Customer Service 184 Thorn Hill Road Warrendale, PA 15086 U.S.A. Telephone: 1-800-759-4867 (U.S.A. only) or (724) 776-9000, ext. 270 Fax: (724) 776-3770 E-mail: [email protected] or order via the World Wide Web at http://www.tms.org

JOM • June 2001