Analog Integrated Circuits and Signal Processing 4, 65-74 (1993) © 1993 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

Design of Concurrent Error Detectable Current-Mode A/D Converters for Real-Time Applications CHIN-LONG WEY, SHOBA KRISHNAN, AND SONDES SAHLI Department of Electrical Engineering, Michigan State University, East Lansing, MI 48824 Received February 4, 1992; Revised September 16, 1992

Abstract. Analog MOS circuits are becoming increasingly sophisticated in terms of checking and correcting themselves. Self-correcting, self-compensating, or self-calibrating techniques eliminate errors traditionally associated with analog circuits. For real-time applications, however, it is rather difficult to achieve validation of the data generated from analog-to-digital (A/D) converters in the presence of faulty switching element(s). Conventionally, the validation is accomplished by using a high resolution and high accuracy D/A converter and a window comparator; i.e., the validation must highly depend on the reliability of both the D/A converter and the window comparator. In this paper, a novel current-mode A/D converter design with concurrent error detection (CED) capability is presented. The A/D converter does not need well-matched components and high-gain amplifiers. Results show that the proposed design can detect all the transient faults and most of the permanent faults. The proposed design allows users to easily swilch to the normal operation mode where CED capability is not used, without causing any performance degradation.

1. Introduction Amdog Currcn ]nput

,

Analog MOS circuits are becoming increasingly sophistica~ed in terms of checking and correcting themselves [1]. Self-correcting, self-compensating, or selfcalibrating techniques eliminate errors traditionally associated with analog circuits. They eliminate offset and low frequency noise, and cancel the error effect [2]. Self-compensating techniques can be used to cancel nonlinearities [3, 4]. For real-time applications, however, it is rather difficult to achieve validation of the data generated from analog-to-digital (A/D) converters in tile presence of faulty switching element(s). In general, the validation is accomplished by using an extra D/A converter and an analog window comparator, as shown in figure 1, where a high resolution and high accuracy digital-to-analog (D/A) converter is needed [5] and the comparison is performed in an analog manner. Therefore, the validation must highly depend upon the reliability of both the D/A converter and the window comparator. Although their reliability may be improved by using sophisticated testing schemes to weed out faulty components [6], such off-line or static tests cannot identify the transient faults that occur during online operation. It would be preferable for the circuits to be designed such that they will indicate malfunction during normal operation and will not produce an erro-

Digital ol]tpul

Fig. 1. Testing the A/D converter.

neous result without an error indication. Therefore, it is obvious that a mechanism for c o n c u r r e n t error detection (CED) must be installed to detect such faults before they cause undesirable results. All CED schemes detect errors through conflicting results generated from operations on the same operands. CED can be achieved through space or time redundancy, or space/time hybrid redundancy [7-13]. Time redundancy employs only a single set of hardware to carry out repeated operations. Since the same hardware is used, the repeated operation, in the presence of faults, is liable to produce the same erroneous result as that of the first step. To avoid this problem, the operand must be coded in the repeated cycle, and the result thus obtained must be decoded back to the appropriate form for meaningful comparison.

66

Wey, Krishnan, and Sahli

Time In input~

~

Ti,nc t I input x ~

~

~-~

Reg tel

Fig. 2. The conceptof time redundancy. Consider a time redundancy technique shown in figure 2 [7]. Let x be the input of the computation unit f, and letfp(X) andf(x) be the outputs with and without encoding-decoding operations, respectively. Two fundamental requirements must be satisfied in these operations. First, the coding function c must not interfere with the original function f In other words, for a selected coding function c, there must exist a decoding function c -1 such that fp(X) = c - l ( f ( e ( x ) ) ) = f ( x ) in the absence of faults. This is the concept of mappable correct output [10]. Secondly, for the purpose of fault detection, the coding operation c must transform the input operand(s) x in such a way that when subjected to the same faulty conditions, the output in the repeated step, though still erroneous will be different from the first step. This is the concept of disjoint error sets [10]. Two simple time redundancy techniques have been reported: RESO (recomputing with shifted operands) [7, 10, 11] and AL (alternating logic)[12, 13]. Among existing CED techniques, both RESO and AL have unique features of transient fault detection and require only a moderate increase in hardware. AL implementation uses the complementation operator as the encoding function, i.e., the application of an input x followed by the complemented input 2, produces outputs that are bitwise complements. Any noncomplemented bit indicates an error. As pressures increase on VLSI designers to use a lower supply voltage of 3.3 V rather than the present 5 V, current mode signal processing techniques will surely become increasingly important and attractive [14]. Current-mode circuits offer two potential advantages: improved dynamic range and improved operating speed [15]. Recently, an algorithmic A/D converter that combines current-mode and dynamic techniques, as shown in figure 3, has been presented [15]. The converter does not rely on high gain amplifiers or wellmatched components to achieve high resolution and is inherently insensitive to the amplifier's offset voltage. The objective of this paper is to implement time redundancy techniques in analog circuit design for reliability enhancement. In this study, an alternative current-

mode A/D converter with CED capability is proposed in which the AL technique is implemented. The fault model considered here is the single stuck-at fault at the switching elements. Results will show that the proposed A/D converter is capable of detecting all transient faults and most of the permanent faults. In the next section, the current-mode A/D converter design using dynamic techniques [15] is briefly discussed. Based on the same dynamic techniques, Section 3 presents the proposed current-mode A/D converter, the CED operation, and its fault coverage. Finally, conclusions and future research direction are given in Section 4.

2. Current-Mode A/D Converter with Dynamic Techniques The current-mode A/D converter in [15] implements a multiply-by-2 scheme. The A/D converter starts converting for the most significant bit (MSB) of an input current. IIN is multiplied by two using transistors N1 and N2. 211Nis stored in el by switching on $6 and $7. After P1 is set, $2, $4, and $7 are turned off while $8 is turned on, thus allowing the comparator to sense the current imbalance and to determine if the signal, 21~N, is greater then Iref in which case the MSB will be a 1; otherwise it will be a 0. This completes the conversion for the MSB. The remaining (N - 1) bits are then converted in the same manner. The signal held in P1 is loaded to N1 by turning on $6, $2, and $3. If the preceding bit was a 1, Iref is subtracted from the signal in P1. Otherwise, the signal remains unchanged. The signal is then doubled, stored in P1, and compared with the reference. This sequence is repeated until the desired resolution has been achieved and an end of conversion pulse is then generated. As the switching sequence illustrates in figure 3b, an N-bit data conversion requires 4N clock cycles. The prototype circuit has been fabricated using a 3-/xm CMOS technology and achieved a resolution of 10 bits with a maximal sampling rate of 25 kHz, or 40/zs conversion time. The power supply was +5 V and the reference current was 100/zA. As seen in the switching sequence, the input current is needed during the first two periods of the conversion cycle, a sample-and-hold (S/H) circuit is thus required [15]. In practice, however, the S/H circuit may be omitted by holding the input in P1, where the polarity of the input current is changed as shown in

Design of Concurrent Error Detectable Current-Mode A/D Converters for Real-Time Applications

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previous bit = 1

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figure 4. /IN is sampled in P1 by turning on switches $1, $6, and S7. Once P1 is set, the remaining switching sequences are the same as those in figure 3b. In other words, the converter needs 5 cycles to determine the MSB. Therefore, there exists a trade-off between hardware (a sample-and-hold circuit) and speed (an additional cycle).

3. Proposed Current-Mode A/D Converter with CED Capability Figure 5 illustrates a CED scheme with the AL implementation. First, the input current It1 = /IN is converted during the first time step (or normal operation phase) and the resulting digital data is stored in a

68

Wey, Krishnan, and Sahli

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Fig. 4. Modifed current-mode A / D converter.

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Iref

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Digital Output

( I t l ~ A/D Converter Shift Register

LI lip

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1-out-of-2 checker

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(It2~ A/D Converter

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Totally Self-Checking (TSC) Comparator

Fig. 5. CED structure with A L implementation.

digital shift register. Then, the complemented current Ia = Iref - /IN is converted during the second time step (or recomputing phase). The digital data resulting from both phases are compared to identify an error, if it exists. If the converter is fault-free, the converted data resulting from both phases must be bitwise complements of each other. For example, with the reference current suggested in [15], i.e., Iref = 100 pA,

the input current 27 pA and its complement 73 pA are converted to the D-bit data O 1 = (0100010100) and D2 = (1011101011), respectively, where both D 1 and D2 are bitwise complements. Since the comparison is in a digital manner, a totally self-checking (TSC) checker can be used to identify the error and also to ensure the correctness of the checker circuit. Therefore, a reliably converted data can be attained.

Design of Concurrent Error Detectable Current-Mode A/D Converters for Real-Time Applications 3.L Proposed A/D Converter

PMOS current copier is needed to hold the current at the beginning of the data conversion. The input current /IN is copied and stored in P1 by turning on switches S1, S6, and $7, while the current difference (/ref -- /IN) is loaded to P2 by turning off S1 and $7 and turning on $8, $9, and $i0. Once both currents are stored, the

Figure 6 shows the proposed current-mode A/D converter with the CED capability. The input current/IN is sampled only once and the current is stored in Pp In order to store the current (Iref - /IN), an additional

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69

Proposed current-modeA/D converter with CED design: (a) schematicdiagram; (b) switchingsequence.

70

Wey, Krishnan, and Sahli

current held in P1 and the current held in P2 are converted. The results from both conversions are compared to identify an error, if it exists. The data conversion process is exactly the same as presented previously. Figure 6b illustrates the switching sequence.

3.2. Fault Models Since the proposed current-mode A/D converter implements a ratio-independent algorithm for conversion, any mismatched components do not affect the converted data. However, any faulty switching elements may affect the converted data. A single stuck-at fault model is considered in this study for all switching elements, i.e., only one faulty switch occurs at a time and a faulty switch may be permanently or temporarily stuck-at ON state (S/ON) or OFF (S/OFF) state. By temporary faults, or transient faults, we mean that the duration of fault behavior is sufficiently short. Transient faults have been very common in today's digital VLSI design. Since all switches in the A/D converter are controlled by the digital clock signals, a signal may temporarily change its value from 0 to 1 or from 1 to 0 and cause the switching elements to temporarily malfunction. By permanent faults we mean the duration of the fault behavior is sufficiently long. In general, the permanent faults may be caused by either a malfunctioning clock generator, i.e., one bit may be permanently stuck-at-1 (or 0) causing the controlled switch to be S/ON (or S/OFF), or by malfunctioning transistor switches. For a reliable circuit design, the permanently faulty switches can be tested by an off-line test process [16]. The chance that permanent faults occur during normal operation is rare, however, the proposed design can still detect most of the permanently faulty switches.

3.3. Fauh Coverage In general, the duration of a transient fault is sufficiently short. It is most likely shorter than the conversion time

for the converter, i.e., 4N clock cycles. Here, a fault may occur during the first time step, or during the second time step, or overlap in both time steps (but the duration is shorter than 4N). If the fault occurs only during the first time step, i.e., the fault disappears during the second time step, then the converted data D2 is reliable and can be used to check D 1 for identifying an error, if it exists. Thus, the fault is detectable. Similarly, the fault that occurs only during the second time step is also detectable. Now, if the fault occurs after the rth bit of D 1 is being converted and disappears after the (r - 1)th of the D2, for any integer r, then at least the first (r - 1) bits of D1 are reliable and can be used to identify the fault. Thus, the fault is detectable and the proposed design can detect all transient faults. If the duration of fault behavior is longer than the time required to complete the first time step and the second time redundancy CED schemes will no longer possess the property of disjoint error sets, and the errors, thus, cannot be detected. This implies that not all permanent faults are detectable. It would be preferable for the circuits to be designed such that they will indicate malfunction during normal operation and will not produce an erroneous result without an error indication [17]. In these circuits, any failures will cause a detectable erroneous output during normal operation, and each fault must not cause an erroneous output without also producing an error signal. The circuits that possess this property are referred to as fault secure circuits. In the presence of single stuck-at faults at the switching elements in the proposed A/D converter design, the following four types of errors may be identified.

3.3.1. Type 1 Errors. Type 1 error c a u s e s D 1 ;~ /)2 for all possible input currents. These errors are definitely detected by the CED scheme. Such errors are the results of S/ON faults at $2, $3, $4, and $5 and S/OFF faults at $2 and $4. Table 1 lists the faults and fault effects of Type 1 errors. Consider the S/ON faulty switch S 3. During the first time step, the currents /IN and (Iref - /IN) are respectively held in Pt and P2. When the current held

Table 1. Type 1 errors. Fault

Analysis

Fault Effects

Sz ($4) S/OFF

Zero current held in NI (N2). Current not doubled.

D1 = D2 = (00...00)

Sz ($4) S/ON

N~ (N2) cancels current from/'1 or P2. N2 (N1) holds zero current. Current not doubled.

D1 = D2 = (00...00)

$3 ($5) S/ON

Output depends on the CMOS structure P~/N~ (P1/N2).

One bit of D~ equals the respective of D2.

Design of Concurrent Error Detectable Current-Mode A/D Converters for Real-Time Applications in P1 is converted, the current is first copied to N 1 and then to N2. Now, when the current is copied to N2, the fault causes the gate-source voltages of both N1 and N 2 to be the same. If both/71 and N2 are well-matched, the currents held in both N1 and N2 will be the same. However, if both N 1 and N2 are mismatched, the curren~: held in N1 is overwritten. When the currents held in N1 and N2 are copied back to P1, due to the S/ON faulty switch $3, the operation is equivalent to copying the current held in N2 to a CMOS current copier consisting of PMOS P1 and NMOS Ni [16]. Experimental results have shown that D1 = (00..0) and D 2 = (10..0) for a sufficiently low input /IN; D1 = (10..0) and D 2 = (00..0) for a sufficiently high input /IN; and D1 = (00..010..0) and/)2 = (00..010..0) for the others. Obviously, the error can be detected for either case. Thus, it is a Type 1 error. Similarly, the S/ON fault of $5 has the same fault effect as that of $3.

3.3.2. Type 2 Errors. Type 2 errors cause D 1 = /)2 for all possible input currents. These errors are caused by either not reading the input current (S/OFF fault at S1), or not reading the reference current (S/OFF fault at $10), or the equivalent fault effects (S/OFF fault at $6 and S/ON fault at $10), as shown in table 2. In

71

general, these errors are not detectable by the CED scheme. Consider a S/OFF fault at $10. The fault is equivalent to the A/D converter using a zero reference current. First, the input current IlN is copied to P1- T h e n , / ' 2 was expected to source a current equal to (Iref - / I N ) . However, the zero reference current results in a negative current, -IIN, being copied to P2 and causes a breakdown in transistor P2 [18]. Since, during the first time step, P1 holds the current/IN and the reference current Iref = 0, the resultant data D l = (11.. 1). On the other hand, the breakdown of transistor P2 may result in D2 = (00..0). Thus, D t = /)2 for all possible input currents and it is a Type 2 error. Similarly, a S/ON fault at $10 has the same fault effect. Thus, it is also a Type 2 error.

3.3.3. Type 3 Errors. In some cases D 1 ¢ /~)2 for all possible input_currents except a few. For these few where Da = D2, if the resulting data D 1 is reliable even in the presence of faults(s), then the circuit is fault secure and such an error is referred to as Type 3 error. Table 3 illustrates the fault effects of Type 3 errors. The faults include S/ON faults at $6, $7, $8, and $9; S/OFF faults at $8 and S9.

Table 2. Type 2 errors. Fault

Analysis

Fault Effects

$I S/OFF

Equivalent t o / I N = 0. PI holds zero and P2 holds Iref'

D 1 = /v)2 = ( 0 0 . . .

$6 S/OFF

P1 never copies current. P2 holds Iref"

D1 = b2 = (00... 00)

00)

$i0 S/OFF

Equivalent to Iref = 0. --/IN forced into £'2.

DI = /)2 = (11.., 11.)

Slo S/ON

Iref always added to the current copied into P~. --/IN forced into Pz.

DI = /)2 = (11... 11.)

Table 3. Type 3 errors. Fault $6 S/ON

Analysis Normal operation phase not altered. Residual current in PI always sourced during recornputation phase.

Fault Effects D 1: correct

D2: random

$7 S/ON

During comparison P1 initially copies Iref and then gets compared. Recomputation phase always converts approximately Iref/2.

D~ = ( 1 1 . . . 1 I ) D2: approximately the digital output of lref/2

$8 S/ON

Residual current in P2 always sourced during normal operation phase. Recomputation phase not altered.

D l : random O2: correct

$9 S/ON

Normal operation phase not altered. During comparison P2 initially copies Iref and then gets compared.

Ol: correct D2 = (11...11)

Ss S/OFF

Normal operation phase not altered. P2 never copies current.

O1: correct D 2 = (00...00)

$9 S/OFF

Normal operation phase not altered. Residual current in 1°2 always compared with lref'

O~: correct

Dz: random

72

Wey, Krishnan, and Sahli

Consider a S/ON fault at $6. According to the switching sequence shown in figure 6b, $6 is on for the entire conversion cycle during the first time step. Thus, the resultant data is still correct even in the presence of such a fault. On the other hand, at the end of the first time step, the current held in P1 is Ix, where Ix is less than 1 LSB if the last bit of D 1 is 1; otherwise Ix is greater than 1 LSB. Due to the faulty switch $6, the current, Ix, held in PI is always available during the second time step. This is equivalent to converting the sum of Ix and the current held in P2 for each bit conversion. If DI ~ D2, then the checker will indicate an error. On the other hand, if D 1 =/)2, the converted data D1 is reliable. Thus, the circuit is fault secure and the error is of Type 3.

rent held inN1 is Ix. Experimental results have shown thatD1 = D2 only if Ix is very close to Iref/2, and D1 D 2 otherwise [18]. For a reliable design, the chance that the fault occurs when the current held in N 1 is Iref/2 is rare. Due to the analog nature, this error is of Type 4. Since the fault of S/OFF switch $5 has the same fault effect as $3, the error is also a Type 4. Based on the above discussion, table 5 summarizes the status of error detection of the proposed A/D converter with CED capability. There exist eight Type 1 errors, four Type 2 errors, five Type 3 errors, and three Type 4 errors. If the fault coverage is defined as the total number of Types 1, 3, and 4 errors over all possible errors, the fault coverage of permanent faults is 80 %. Table 5. Error detection.

3.3.4. Type 4 Errors. If the resulting data D1 is not reliable in the presence of fault(s), then the fault cannot be detected for the application of such input currents and this error is referred to as Type 4 error. The fault effects of such error types are listed in table 4. The faults include S/ON fault at $1; S/OFF faults at $3, $5, and $7. Consider the S/ON faulty switch $1. It is assumed that the input current will be varying for real-time applications. The fault implies that the data is converted in the environment where the noise is equivalent to the varied input currents. Thus, D 1 and D2 can be any random results. Statistically speaking, the probability of having two random data D 1 and D2 as complements to each other is very low. Thus, this is a Type 4 error. Due to the S/OFF fault switch $7, the current copier with P1 cannot copy any current. Thus, the current, Ix, held in P1 is the one remaining from the previous operation. This results in D1 = (00..0) if Ix < Iref, or D1 = (11.. 1) otherwise. Since P1 can still source the current Ix, the current held in P2 is (Iref - Ix) and the resultant data D2 is reliable. Therefore, D 1 = / ) 2 only if either I x or (I~ef - Ix) is less than 1 LSB, D1 ~ /)2 otherwise. This is a Type 4 error. Similarly, the S/OFF faulty switch $3 causes the current copier with N1 cannot copy any current. Assume that the cur-

Type Switches

S/ON

S/OFF

$1 $2 $3

4 1 1

2 1 4

$4

1

1

$5 $6 $7 $8 $9 S~o

1 3 3 3 3 2

4 2 4 3 3 2

4. Conclusions This paper presents a novel current-mode A/D converter design with CED capability, where a time redundant CED scheme is implemented. The original A/D converter [15] is modified by adding an extra PMOS current copier to provide the CED capability, thus making the validation of the converted data more reliable. Results have shown that the proposed design can detect all transient faults that occur at the switching elements and most of the permanent faults. Some permanent faults cannot be detected due to the unavailability of

Table 4. Type 4 errors. Fault

Analysis

Fault Effects

$I S/ON

Varying /IN always sourced to the circuit.

DI & D2: random

$3 ($5) S/OFF

NI (N2) do not copy any current but its residual current is sourced.

Dl & Dz: random

$7 S/OFF

Residual current in P1 always compared with Iref- Recomputation phase converts the complement of this residual current.

D~ & Dz: random

D e s i g n of C o n c u r r e n t E r r o r Detectable C u r r e n t - M o d e A / D Converters for Real-Time Applications

test patterns for real-time applications. However, the s a m e structure can be tested off-line w i t h only two test patterns [18]. T h e d r a w b a c k of the p r o p o s e d design with C E D capability is a p p r o x i m a t e l y 100% overhead in time w h i c h is inherent in all time redundancy schemes. Judging f r o m the V L S I p e r f o r m a n c e m e a s u r e o f A T 2 (where A is the chip area and T is the operation cycle time), this is rather a high price to pay. However, the p e r f o r m a n c e penalty associated with t i m e redundancy can be a b s o r b e d by the inherent idleness of the processing e l e m e n t [11]. T h e p r o p o s e d design is perfectly applied to those systems or subsystems in w h i c h the t i m e to process the converted data is as m u c h as t w i c e the conversion time. T h e other salient feature is that the p r o p o s e d design allows users to easily switch between an A / D converter with and without C E D capability without causing any p e r f o r m a n c e degradation [18].

73

13. C.L. Wey, "Concurrent error detection in array dividers by alternating input data" in Proc. Int. Conf. Computer Design: VLSl in Computers and Processors (ICCD '91), pp. 114-117, Oct. 1991. 14. B. Wilson, "Recent developments in current conveyors and current-mode circuits," lEE Proe., Vol. 137, Part G, No. 2, pp. 63-77, April 1990. 15. D.G. Nairn and C.S. Salama, 'N ratio-independent algorithmic analog-to-digital converter combining current mode and dynamic techniques," IEEE Trans. Circuits Systems, Vol. 37, No. 3, pp. 319-325, March 1990. 16. C.L. Wey and S. Krishnan, "Current-mode divide-B-two circuit," Electron. Lett., Vol. 28, No. 9, pp. 820-822, April 1992. 17. T.R.N. Rao and E. Fujiwara, Error-Control Coding for Computer Systems, Prentice-Hall: Englewood Cliffs, NJ, 1989. 18. S. Sahli, M.S. thesis, Department of Electrical Engineering, Michigan State University.

Rel~rences

1. Y.P. Tisividis, "Analog MOS integrated circuits--certain new ideas, trends, and obstacles, 1EEE J. Solid-State Circuits, Vol. SC-22, pp. 317-321, June 1987. 2. R. Poujois, B. Baylac, D. Barbier, and J.M. Ittel, "Low-level MOS transistor amplifier using storage elements," IEEE ISSCC Dig. Tech. Papers, pp. 152-153, 1973. 3. Y.P. Tisvidis, M. Banu, and J.F. Khoury, "Continuous-time MOSFET-C filters in VLSI;' IEEEJ. Solid-State Circuits, Vol. SC-21, pp. 15-30, Feb. 1986. 4. H.T. Yung and K.S. Chao, 'Nn error-compensation A/D conversion technique," IEEE Trans. Circuits Systems, Vol. 38, pp. 187-195, Feb. 1991. 5. Analog Devices, Analog-Digital Conversion Handbook, PrenticeHall: Englewood Cliffs, NJ, 1986. 6. J.A. Abraham and V.K. Agarwal, "Test generation for digital systems," in Fault-Tolerant Computing, Theory and Techniques (D.K. Pradhan, ed.), Prentice-Hall: Englewood Cliffs, NJ, 1986. 7. J.H. Patel and L.Y. Fung, "Concurrent error detection in ALUs by recomputing with shifted operands," 1EEE Trans. Comput., Vol. C-31, pp. 589-595, July 1982. 8. Y.H. Choi, S.H. Han, and M. Malek, "Fauk diagnosis ofreconfigurable systolic arrays," in Proc. Conf. Computer Design: VLSI in Computers and Processors (ICCD '84), pp. 451-455, 1984. 9. R.K. Gulati and S.M. Reddy, "Concurrent error detection VLSI structures," in Proc. Int. Conf. Computer Design: VLSI in Computers and Processors (ICCD '86), pp. 488-491, 1986. 10. S.-W. Chan, S.S. Leung, and C.L. Wey, "Systematic design strategy for concurrent error diagnosable iterative logic arrays," tEE Proc. E, Vol. 135, No. 2, pp. 87-94, March 1988. 1 l. S.-W.Chart and C.L. Wey, "The design of concurrent error diagnosable systolic arrays for band-matrix multiplication," IEEE Trans. CAD Integrated Circuits Systems, Vol. CAD-7, No. 1, pp. 21-37, Jan. 1988. 12. D.A. Reynolds and G. Metze, "Fault detection capabilities of alternating logics," IEEE Trans. Comput., Vol. C-27, pp. 10931098, Dec. 1978.

Chin-Long Wey received the Ph. D. degree from the Department of Electrical Engineering, Texas Tech University,Lubbock, TX, in 1983. He joined the Department of Electrical Engineering at Michigan State University in 1983, where he is currently an associate professor. His current research interests include analog circuit fault diagnosis, current-mode A/D and D/A converters, VLSI design and test, asynchronous sequential circuit design and synthesis. He organized the first workshop on VLSI testing in 1990, Taiwan, sponsored by National Science Council, Taiwan, Republic of China.

Shoba Krishnan was born in Behrampur, Orissa, India, on

September 19, 1966. She received her B. Tech degree in electronics and communications from Jawaharlal Nehru Technological University, Hyderabad, India, in 1987 and her M.S. degree from the Department of Electrical Engineering at Michigan State University in 1990. She is currently working toward her Ph.D. degree at Michigan State University. Her research interests include built-in self-test structures, current-mode A/D and D/A converter design, and smart sensors. Ms. Krishnan recieved the 1989 outstanding teaching assistant award at the Department of Electrical Engineering.

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Wey, Krishnan, and Sahli

Sondes Sahli was born in Nabeul, Tunisia, on April 29, 1967. She received her B.S. and M.S. from the Department of Electrical Engineering at Michigan State University in 1990 and 1992, respectively. She is currently working toward her Ph.D. degree. Her research interests include current mode signal processing circuit design. Ms. Sahli recieved the Academic Achievement Awards from the Department of Electrical Engineering and from the Society of Women Engineers at Michigan State University. Her study is supported by a scholarhsip from University Mission of Tunisia, Technology Transfer Program.