J Electron Test (2008) 24:567–576 DOI 10.1007/s10836-008-5071-5

Linearity Testing of A/D Converters Using Selective Code Measurement Shalabh Goyal & Abhijit Chatterjee

Received: 3 December 2007 / Accepted: 2 April 2008 / Published online: 25 June 2008 # Springer Science + Business Media, LLC 2008

Abstract Measurement of integral non-linearity (INL) and differential non-linearity (DNL) of an A/D converter using the histogram method incurs large test time. This test time can be a significant percentage of the total test time, especially for high resolution and low sampling-speed A/D converters. This paper describes a test methodology for measuring the INL and DNL specifications of A/D converters by measuring a subset of the total set of code widths. This methodology is based on the fact that manufacturing variations in the electronic components of an A/D converter affect specific sets of codes in a similar manner. The proposed methodology measures code width parameters across such different sets of codes and estimates the A/D converter transfer function from the resulting information. A novel test generation methodology is presented for measuring the relevant code widths using a piecewise linear ramp that is designed to extract test information accurately from test data in minimal test time. The test procedure has been applied to different A/D converters and test time reduction of more than 75% has been achieved. Keywords Analog–digital conversion . Manufacturing test . Non-linearity . Testing

Responsible Editor: V. Champac S. Goyal (*) Test Development-Data Converter Systems, National Semiconductor Corporation, Mail Stop D3/597, 2900 Semiconductor Drive, Santa Clara, CA 95051, USA e-mail: [email protected] A. Chatterjee Georgia Institute of Technology, Atlanta, GA 30332, USA

1 Introduction The static specifications of A/D converters, such as integral nonlinearity (INL), differential nonlinearity (DNL), offset error and gain error [14], are a measure of the nonlinearity of the converter transfer function. DNL is a measure of deviation of a code width from its ideal value of one least significant bit (LSB). INL is a measure of deviation of an A/D converter transfer function from the ideal linear transfer function. The DNL and INL specifications are measured for all the codes of an A/D converter (except for the first and last code). The DNL and INL for an A/D converter are given by Eqs. 1 and 2 respectively, where Mi is the code width for code ‘i’ measured in LSBs and ‘n’ is the A/D converter resolution. DNLi ¼ Mi
1

INLi ¼

j¼i P

DNLj

0 < i < 2n
1

ð1Þ

0 < i < 2n
1

ð2Þ

j¼i

The test time for DNL and INL testing constitutes a significant percentage of the total test time for A/D converters. As the resolution of an A/D converter increases, the number of measurement samples (test data) and the corresponding test time required to accurately estimate these specifications increases exponentially. This is a major test problem [12], especially for low sampling speed A/D converters. In this paper, a methodology for reducing the static specification test time of A/D converters is described. The proposed methodology identifies specific codes that are directly affected by deviations in A/D converter component specifications due to manufacturing variations. A novel test

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generation algorithm generates a piecewise linear ramp test stimulus to measure these specific code widths. This significantly reduces the test time for linearity testing of A/D converters. The most significant contribution of this research is the development of a test methodology that can be easily used in production environment for linearity testing of different A/D converters with a significant test time reduction. The histogram test methodology and prior research is described in the rest of the section. 1.1 Histogram Test Methodology The conventional histogram method [3, 15] is used to measure the DNL and INL specifications of an A/D converter. In this methodology, a low-frequency test stimulus, with a known ideal output distribution, is applied to an A/D converter and the digital codes are binned at the output. A histogram of the output codes is obtained (Fig. 1). The histogram shows the number of times each digital code word appears at the A/D converter output (called hits per code) through the duration of the test. The low-frequency test stimulus applied to the A/D converter is generally a triangular ramp or a sinusoidal wave [3, 15]. The ideal output code distribution for a triangular ramp test stimulus is a flat distribution with equal hits per code. The deviation of the observed output code distribution from this ideal distribution is a measure of the nonlinearity of the device. There is usually random noise present at the code transition edges of an A/D converter. This noise causes inaccuracy in code width measurement. The histogram method averages out this random code edge noise by effectively averaging it over a large number of samples. The number of samples depends on the resolution of the A/D converter and the desired accuracy in the specification (DNL, INL) measurement. As explained earlier, measurement of all the codes and the requirement of achieving a large number of hits per code results in a significant test time. Thus, there is a need for developing a test methodology to reduce the test time for measuring the INL and DNL specifications of high-resolution and low-speed A/D converters.

Or

DUT INL/DNL Test stimulus

Output code histogram

Fig. 1 Histogram testing methodology

1.2 Previous Work Linearity testing of A/D converters is a widely researched topic. Generation of precise test signals and reduction of test time has been the focus of past research. The issues with histogram testing are discussed in [2, 3, 5, 10, 13]. The authors present a statistical technique for characterizing an A/D converter using Gaussian noise as the test stimulus for the histogram test set-up of [16]. However, the results show a significant error in the measurement of maximum INL. Also, the number of samples needed for the test procedure is large. A different methodology that uses noise as the test stimulus is presented in [8]. A methodology for testing the INL and DNL specifications of data converters using nonlinear signals is proposed in [9]. Past research has also focused on INL estimation using frequency domain methods. In [18], the authors filter noise from the output frequency spectrum of an A/D converter and perform the inverse FFT of this signal to reconstruct the input signal. This reconstructed signal is then compared against the original input signal to measure the INL. In [1], the A/D converter transfer function is approximated by a polynomial and the INL is estimated from the FFT spectrum. Frequency domain methods reduce test time significantly but they are inaccurate for measurement of specifications such as maximum INL and DNL [1, 18]. Testing of A/D converters based on a linear model has been proposed in [6, 7, 20, 21]. These test methodologies are based on exploiting correlations between the code widths of different codes of an A/D converter. A linear model that relates all the code transition edges to a few set of independent parameters is constructed through a set of statistical measurements across a large number of devices. The number of parameters used to model the A/D converter is significantly smaller than the number of converter output codes. Thus, static non-linearity testing of the A/D converter requires measurement of fewer numbers of unknowns and the test time is significantly reduced. Another model based technique is presented in [17]. Here the authors model INL of an A/D converter as a superposition of low-frequency and high-frequency components. Identification of low-frequency components is done using the spectral analysis and they reveal general INL plot shape. Identification of high-frequency components reveals the major discontinuities in the INL plot and this is done by measuring the DNL of specific codes. The results shown in the Fig. 2 in [17] indicate that the proposed method can track the shape of the INL plot but a significant error in the estimation of INL exists. However, these methods do not exploit the circuit topology for test time reduction, the core subject of this paper. In [4], the authors indicate that in a data converter it is possible to reduce the linearity test time by measuring a subset of all code widths. However, they do not give a detailed

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I/P

Stage 2

Stage 1 R1

+

R2

569 Stage N +

Stage 1

Stage N

Stage 2

O/P

RN

b1 b2… bR1 | b(R1+1) … b(R1+R2) | … |b(R1+…R(N-1)+1)… b(R1+…RN) Fig. 3 Digital bit output

R = R1 + R2 +…….RN

Fig. 2 Generic A/D converter architecture

methodology and do not explain how this could be achieved for data converters having different architectures. Also, they do not mention how this could be achieved in a production testing environment. In this research, we present a test methodology for INL and DNL testing of A/D converters. This methodology takes into account various A/D converter architectures and can be easily implemented in a production testing environment. The proposed methodology measures the converter specifications as accurately as the histogram methodology, but reduces test time by one-fourth. The rest of the paper is organized as follows. The proposed test methodology is described in “Section 2”. The implementation of the proposed methodology for different A/D converters is described in “Section 3”. The limitation of the proposed methodology and the comparison with Histogram methodology is discussed in “Section 4”.

2 Proposed Test Methodology The architecture of an A/D converter depends on the converter resolution and sampling speed. In this work, we consider A/D converters with a generic architecture as shown in Fig. 2. The A/D converter is divided into multiple stages. Each stage is a low-resolution, ‘flash-type’ A/D converter having a resolution Ri (where, ‘i’ is the stage number). In general, there is additional inter-stage circuitry not shown in Fig. 2. An extreme case of this generic architecture is a flash A/D converter where the number of stages is one and all the bits are contributed by that stage. The other extreme case is an N stage, N-bit pipelined A/D converter where each stage contributes one bit to the output word. The total resolution of an A/D converter (number of bits) is the sum of the effective resolution of all its stages. Each stage contributes a fixed number of bits, equal to its resolution, to the output. Further, we assume that the first stage is the most significant stage (i.e. it contributes the most significant bits) and the last stage is the least significant stage (i.e. it contributes the least significant bits) as shown in Fig. 3. 2.1 The Concept of Selective Code Measurement The proposed test methodology is based on the premise that code width variations result primarily from manufacturing variations in the values of components from the nominal

values in each stage of an A/D converter. Since each stage computes only a subset of the total number of bits generated by the converter, the non-idealities in the value of components of a stage impact specific codes. Further, the codes that are affected by a particular stage can be divided into sets, such that, each set of codes is affected in a similar way. Thus, if the DNL of one such set of codes is measured, the DNL of all the other sets of codes that are affected by that particular stage can be determined. The performance of the A/D converter across its entire output code space can then be determined by measuring one such set of codes for every stage. Once the DNL of all the codes is obtained using the proposed methodology, the transfer function of the A/D converter is obtained by summing the respective code widths. The INL values for each code can be computed by comparing the obtained transfer function from the ideal A/ D converter transfer function. To identify sets of codes that have similar DNL values, consider the 4-bit converter example shown in Fig. 4. The A/D converter in this example consists of two stages, each contributing 2 bits in the A/D converter output.

Stage 1

Stage 2

code: 0 code: 1 code: 2 code: 3

0 0 0 0

0 0 0 0

0 0 1 1

0 1 0 1

Set 1

code: 4 code: 5 code: 6 code: 7

0 0 0 0

1 1 1 1

0 0 1 1

0 1 0 1

Set 2

code: 8 code: 9 code: 10 code: 11

1 1 1 1

0 0 0 0

0 0 1 1

0 1 0 1

code: 12 code: 13 code: 14 code: 15

1 1 1 1

1 1 1 1

0 0 1 1

0 1 0 1

Fig. 4 Four-bit, two-stage A/D converter

Set 3

Set 4

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In this example, width of codes {0, 1, 2} corresponds to Set 1, {4, 5, 6} corresponds to Set 2, {8, 9, 10} corresponds to Set 3 and {12, 13, 14} corresponds to Set 4. For the codes present in Set 1 the logic state of bits contributed by Stage 1 remains the same (‘00’). Similarly for Set 2, 3 and 4 the logic state of bits contributed by Stage 1 remains the same (‘01’, ‘10’ and ‘11’ respectively). It is observed that the code transitions within a set occur only due to the change of logic state of Stage 2 bits. Hence, the DNL of the codes present in these four sets occur only due to the non-ideal components present in Stage 2. Also, the non-ideality in the code widths (DNL) of all the four sets should be equal as it is caused by the same underlying electronics components (Stage 2 components). Thus, if the DNL of one of the four set of codes is measured, the DNL of the other three set of codes can be directly calculated from the measurements. In this example, the code widths that need to be measured for A/D converter static characterization are {0, 1, 2, 3, 7, 11 and 15}. As the DNL of the codes present in Set 2, 3 and 4 is equal to that of Set 1, the A/D converter transfer function can be constructed by adding the measured code widths. Generalization for a multistage A/D converter is shown in Fig. 5. In this example A/D converter has N stages and Stage N contributes RN least significant bits. The codes transitions that occur due to the change of logic state of these RN bits (logic state of all the higher order bits remains unchanged) are governed only by the components of Stage N. Hence, the non-ideality in the width of such codes is only due to the non-ideal components used in Stage N. Codes that are affected by Stage N are divided in different sets as shown in Fig. 5. As shown in Fig. 5, Set 1 corresponds to the codes from 0 to (x−2), and Set 2 corresponds to the codes from x to (2x–1). More such sets can be obtained by varying the logic state of the ‘more significant bits’. The widths of all the codes present in these sets are governed by the components in Stage N. If

More Significant Stages

code: 0

code: x-2 code: x-1 code: x

code: 2x-1 code: 2x

Stage N

00…00 0…00 00…00 0…01 ……………..……… 00…00 1…10 00…00 1…11 00…01 0…00 00…01 0…01 ……………..……… 00…01 1…10 00…01 1…11 …………………….

Set1

Set2

x = 2R N Fig. 5 Identification of similar sets of codes for stage N

the code widths (or DNL) of one set are measured, the code widths of similar sets can be computed. Same concept can be extended to other stages and one set of codes for each stage is measured. Thus, by measuring specific code widths, transfer function of the A/D converter can be obtained. 2.2 Reduction in Test Time As illustrated in the previous section, to measure the effect of non-ideal components in Stage N, it is necessary to measure the width of 2RN A/D output codes. The total number of code widths (or DNL) that need to be measured for estimating the non-ideality of all the components in an A/D converter is given by Eq. 3. This is significantly less than the number of code widths that need to be measured if the histogram method is used to measure the INL and DNL of an A/D converter Eq. 4. CWsel ¼ 2R1 þ2R2 þ . . . 2RN

ð3Þ

CWhist ¼ 2R1 þR2 þ...RN

ð4Þ

An algorithm for identifying the codes that need to be measured to capture the effect of non-ideal component values in all the stages 1, 2, …, N of an A/D converter on its output code widths is described in the following section. 2.3 Generation of Test Stimulus For generating the test stimulus, the codes that need to be measured are identified first. Next, a piecewise linear ramp is programmed such that its slope is low (slow ramp) when it crosses over the codes whose widths are to be measured and its slope is high (fast ramp) when it crosses over all other codes. The non-linearity in the A/D transfer function may cause the code that we desire to measure to be displaced from its ideal position. In order to ensure that the slow ramp covers the desired code, the length (time duration) of the each slow section of the ramp is at 7 least significant bits (LSBs). The desired slope for the fast ramp is infinite (the most aggressive ramp that can be applied by the test system is used). The algorithm for identification of codes and generation of test stimulus is given below. Piecewise Linear Ramp Generation Algorithm N Ri H LSB

Number of stages of the converter. Number of bits corresponding to Stage i. Desired number of hits/code for selected codes Value of a least significant bit.

Input: (N, Ri, H, LSB) 1. Choose the least significant stage. 2. While the chosen stage is not the most significant stage.

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3. Search for the codes C such that for transition from C to C +1, only the bits that are contributed by the chosen stage change logic state AND all the bits of the stages more significant than the chosen stage have logic state ‘0’. 4. Add C to the list L. 5. Choose the next more significant stage. 6. End while. 7. Search for codes C such that for the transition from C to C+1, only the bits that are contributed by the chosen stage change the logic state. 8. Add C to the list L. 9. Program a piecewise linear ramp from (L-3)*LSB to (L+4) *LSB for all the codes in the list L having a slope adjusted to obtain the specified number of hits per code. Output:(Piecewise linear ramp test stimulus). 2.4 Calibration The proposed method is based on the concept that the DNL (or code width) of different set of codes is equal because it is caused by non-idealities in the same components. Thus, the DNL of a few codes is measured and the DNL (or the code width) of rest of the codes is estimated from them. The transfer function is then obtained by adding the code widths cumulatively. Due to the inherent noise in an A/D converter, and the external noise in the measurement system, edge noise appears near code transitions. This noise can be as high as 200 m LSB, and it causes error in the measurement of the code widths of the desired codes. The error in measurement of these code widths is small (20–30 milliLSB). But, when these code widths are added to obtain the overall A/D converter transfer function, the error adds up cumulatively and results in a deviation of the transfer function from the actual transfer function. To

571

4 bits

8 bits

Stage 1

Stage 2

+

S/H

A

+

Out

-

In A/D

D/A

Fig. 7 Simulated pipelined A/D converter architecture

eliminate this inaccuracy in measurement due to edge noise, calibration is necessary. In this process, the estimated transfer function is calibrated such that it is close to the actual transfer function of the device. The last slow ramp section of the test stimulus is used for calibration. This is shown in Fig. 6. The output of the A/ D converter for this section determines the code position of the device-under-test at the applied voltage. For this code position, the estimated transfer function gives the estimated voltage. The difference between the applied voltage and the estimated voltage gives the voltage error at that code position. The estimated transfer function is then corrected for the error by linearly scaling the observed voltage error to give a calibrated transfer function (TFcal). Let the last slow ramp section of the test stimulus have the following characteristics. Starting Voltage: Vi Slope: M hits/code. Let the lowest output code of the converter corresponding to this section be x, having P hits. The actual transfer function (TFact) at the code x is given by Eq. 5. is the estimated transfer function. VE(x) is the voltage error in the estimated transfer function at the codex and is given by Eq. 6. The calibrated transfer functionTFcal is given by Eq. 7 where N is the resolution of the A/D converter.
 P TFact ð xÞ ¼ Vi
1
 lsb ð5Þ M VE ð xÞ ¼ TFact ð xÞ
TFest ð xÞ

TFcal ðiÞ ¼ TFest ðiÞ þ iVExð xÞ

ð6Þ

0  i  2N

ð7Þ

3 Implementation of the Proposed Methodology

Fig. 6 Example of a piecewise linear ramp test stimulus

The proposed test methodology was implemented on three cases for validation. The case studies are described next.

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J Electron Test (2008) 24:567–576 Table 1 Comparison of error in estimation of specifications for case study I Histogram method

Selective code measurement method

96.0 33.3

87.8 29.0

82.2 19.9

87.0 28.8

+ve INL Max. error Mean error –ve INL Max. error Mean error All values are in milliLSB.

Fig. 8 INL of a simulated A/D converter instance

2. Selective Code Measurement: The codes that need to be measured were determined using the piecewise linear ramp generation algorithm given in “Section 2.3”. The code widths that were measured are given by Eq. 8. Codes 2 f½0 254; 255 þ 256  ig

3.1 Case Study I: Simulated Pipelined A/D Converter A two stage, 12-bit, 80 Msps pipelined A/D converter was used as a test vehicle for this case. 1. Pipelined A/D Converter Architecture: A two-stage pipelined A/D converter was modeled using behavioral modeling technique and simulated using Matlab. Its architecture is shown in Fig. 7. The first stage was simulated as a 4-bit flash A/D converter and the second stage as a 8-bit flash A/D converter. The flash architecture of each stage was modeled by a ‘random transfer function model’. The random transfer function model was obtained by varying the code widths randomly from the ideal value by 0.2 LSB. Such a model takes into account the non-ideality in all the components.

0  i  14

A piecewise linear ramp was generated to measure these codes. The slope of the slow part of the ramp was set such that the number of hits per code was 64. The slope of the fast part of the ramp was infinitely large (DC offset was added). The transfer function of the A/D converter was obtained from the measured code widths. The calibration of the estimated transfer function was performed as explained in “Section 2.4”. 3. Simulation Results: Fifty simulation instances of pipelined A/D converter were generated. The total number of samples required by the proposed methodology was 22,158. The specifications calculated were maximum (+/−) INL. A comparison of the calculated specifications and the actual specifications is shown in Fig. 9.

To simulate the real device behavior, a random code edge noise (peak-to-peak value equal to 0.2 LSB) was added to the code transitions. INL plot of a simulated A/D converter instance is shown in Fig. 8.

Sample and Hold

I/P

Digital O/P

Comparator SAR

D/A Converter Control Logic Analog Output N

2 C MSB

2C

C LSB

C

Vref Ground

Fig. 9 Actual and estimated maximum (+/–) INL

ð8Þ

Fig. 10 SAR A/D converter architecture

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Table 2 Comparison of error in estimation of specifications for case study II Histogram method

+ve INL Max. error Mean error −ve INL Max. error Mean error

Selective code measurement method

119.0 42.1

45.5 13.9

117.4 65.2

92.3 16.5

All values are in milliLSB.

The specifications of the same simulated A/D converter instances were measured using the histogram method. A linear ramp having a slope such that the number of hits per code was 64 was used in this method. The total number of samples required by the histogram method was 262,144. A comparison of error in estimation of the specifications using the histogram method and the proposed method from the actual specifications is given in Table 1. It shows that the

proposed method produces results that are as accurate as the results obtained using the histogram method for maximum (+/−) INL. The number of samples required by the proposed methodology is ten times lesser than the number of samples required by the histogram methodology. 3.2 Case Study II: Simulated Successive Approximation Register A/D Converter In this case study, a 12-bit, 500 Ksps successive approximation register (SAR) A/D converter was used as a test vehicle. The A/D converter was modeled using a behavioral modeling technique in Matlab. The test set-up was also simulated in Matlab. 1. SAR A/D Converter Architecture: Unlike the pipelined architecture, the output bits are estimated serially in SAR architecture [19]. The SAR control logic sets the bits of D/A converter using a binary search algorithm. The objective is to set the bits of D/A converter such that the output of the D/A converter is as close to the

Fig. 11 a INL plot using the histogram approach. b INL plot using the proposed approach

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Table 3 Measured value of specifications using both methods case study III

+ve INL Device 1 Device 2 Device 3 Device 4 Device 5 −ve INL Device 1 Device 2 Device 3 Device 4 Device 5 +ve DNL Device 1 Device 2 Device 3 Device 4 Device 5 −ve DNL Device 1 Device 2 Device 3 Device 4 Device 5

Histogram method

Selective code measurement method

Deviation from histogram method

419.6 463.0 405.8 399.8 407.0

446.2 430.6 454.4 434.4 382.2

−26.8 33.6 −48.6 −34.6 24.8

−431.4 −432.4 −385.4 −387.6 −346.6

−436.2 −448.0 −482.4 −470.0 −420.2

4.8 15.6 97.0 82.4 73.6

545.0 558.0 585.2 540.2 557.8

529.8 549.2 543.0 542.2 528.8

15.2 8.8 42.2 −2.2 29.0

−289.6 −289.2 −301.4 −273.2 −288.0

−213.2 −253.0 −257.2 −250.6 −246.0

−76.4 −36.2 −44.2 −22.6 −42

3. Simulation Results: Ninety instances of the simulated A/D converter were generated. The total number of samples required by the proposed methodology was 34,816. The specifications measured were maximum (+/−) INL. The histogram method was used to measure the specification of the same simulated A/D converter instances using a linear ramp. The slope of the ramp was set such that number of hits per code was 64. The total number of samples taken using the histogram method was 262,144. A comparison of error in estimation of the specifications using the histogram method and the proposed method from the actual specifications is given in Table 2. The total number of samples is still considerably lower than the number of samples used by the histogram method.

Test time for histogram method was 1.22 s per device. Test time for the proposed method was 0.28 s per device. Seventy-six percent of test time reduction was achieved. All values are in milliLSB.

input signal as possible. D/A converter forms a major part of the SAR A/D converter as shown in Fig. 10. The D/A converter simulated in this research work consist of an array of weighted capacitors. The values of the capacitors in the D/A converter were randomly perturbed within 1–2% of the nominal value to generate different simulation instances of A/D converter. The transfer function of the A/D converter was obtained based on the D/A converter capacitor values. Code edge noise having a uniform distribution and peak-to-peak value equal to 0.2 LSB, was added to the code transitions. 2. Selective Code Measurement: The codes that need to be measured were determined using the piecewise linear ramp generation algorithm given in “Section 2.3”. The code widths that were measured are given by Eq. 9. Codes 2



2
1 i



A piecewise linear ramp was then generated to measure these codes. The slope of the slow part of the ramp was set such that the number of hits per code was 512. The slope of the fast part of the ramp was infinitely large (DC offset was added). The transfer function of the A/D converter was obtained from the measured code widths. The calibration of the estimated transfer function was done as explained in “Section 2.4”.

We proposed a methodology for test time reduction of SAR A/D converters in [11]. However, it was specific only to the SAR A/D converters and used an additional calibration ramp for calibration of transfer function. The current work presents a general approach that can be applied to any A/D converter having a multi-stage architecture without using a separate calibration ramp. 3.3 Case Study III: In-Production SAR A/D Converter An in-production, 12-bit, 500 Ksps SAR A/D converter was used as a test vehicle for this case study (data sheet of ADC78h89 http://www.national.com/ds/DC/ADC78H89. pdf.). The test platform was A580 tester from Teradyne. 1. Selective Code Measurement: The codes measured in this case study were same as the codes measured in Case Study II because the specifications (resolution and architecture) of the A/D converter-under-test are same. The slope of the slow part of the ramp was set such that the number of hits per code was 256. The slope of the Table 4 Repeatability analysis of histogram method case study III Maximum deviation for five runs +ve INL 63

0  i  11

ð9Þ

−ve INL

+ve DNL

−ve DNL

76

82

77

All values are in milliLSB.

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fast part of the ramp was set such that the number of hits per code was 0.5. The slope of the fast ramp was adjusted to minimize ringing and overshoot of the test stimulus. The ringing and overshoot occur due to the filter characteristics of the precision low-frequency source which was used to generate the ramp. The transfer function of the device-under-test was obtained from the measured code widths. The calibration of the estimated transfer function was performed as explained in “Section 2.4”. 2. Hardware Results: The proposed methodology was used to measure the maximum (+/−) INL and DNL of five devices. The total number of samples required by the proposed methodology for each device was 17,886. The histogram method was used to estimate the specifications of the same devices using a sinusoidal source. The frequency of the sinusoidal wave was chosen such that average number of hits per code was 64. The total number of samples required by the histogram method was 262,144. Table 3 shows the value of the specifications obtained by both the methods for different devices. Column 3 in the table shows the deviation of the results obtained using the proposed methodology from the results obtained using the histogram methodology. The INL plot of a device is shown in Fig. 11. The repeatability analysis of the histogram method was done to obtain the error margin from run-to-run. This was done by repeating measurements five times on all the devices. The maximum deviation in the values of the specifications is shown in Table 4. Comparing these values to the deviation in specifications measured using two methods (shown in Table 3 column 3), it can be concluded that the proposed method estimates the specifications which are within the histogram method repeatability limits. The test time to measure the specifications using the proposed method was 0.28 s as compared to 1.22 s using the histogram method.

4 Conclusion The proposed methodology is based on the fact that most of the A/D converters use Multistage architecture. This causes the non-linearity of one stage to effect many codes in the a/d converter transfer function in a similar way. Hence, the best candidates for the proposed methodology are a/d converters having pipelined or sar architecture. The proposed methodology does not offer a significant advantage when a/d converters having fully-parallel architecture such as “flash” are tested.

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In comparison with the histogram methodology, the proposed methodology incurs a significantly less test time. However, the proposed methodology uses a piecewise linear ramp and hence needs an Arbitrary Waveform Generator (AWG) for generating such input signals. This requirement does not exist while using histogram testing methodology because it generally uses a sinusoidal waveform which can be generated using any Continuous Waveform Generator (CWG). Acknowledgment S. Goyal thanks the Data Conversion System Test Development group of National Semiconductor Corporation, Santa Clara for the providing the tester facility.

References 1. Adamo F et al. (2001) FFT test of A/D converters to determine the integral nonlinearity. In: Proceedings of Instrumentation and Measurement Technology Conference, 710–714 May 2. Alegria F, Arpaia P, de Cruz Serra AM, Daponte P (2002) Performance analysis of an ADC histogram test using small triangular waves. IEEE Trans Instrum Meas 51(4):723–729, Aug 3. Blair J (1994) Histogram measurement of ADC nonlinearities using sine waves. IEEE Trans Instrum Meas 43(3):373–383, June 4. Burns M, Roberts GW (2001) An introduction to mixed-signal IC test and measurement. Oxford University Press, Oxford, pp 423–424 5. Carbone P, Petri D (1998) Noise sensitivity of ADC histogram test. IEEE Trans Instrum Meas 47(3):1001–1004 6. Capofreddi PD, Wooley BA (1997) The use of linear models in A/D converter testing. IEEE Trans Circuits Syst I Fundam Theory Appl 44(12):1105–1113, Dec 7. Cherubal S, Chatterjee A (2003) Optimal linearity testing of analog-to-digital converters using a linear model. IEEE Trans Circuits Syst I Fundam Theory Appl 50(3):317–327, Mar 8. Flores MGC, Negreiros M, Carro L, Susin AA (2004) INL and DNL estimation based on noise for ADC test. IEEE Trans Instrum Meas 53(5):1391–1395 Oct 9. Jin L, Parthasarathy K, Kuyel T, Chen D, Geiger RL (2003) Linearity testing of precision analog-to-digital converters using stationary non-linear inputs. In: Proc Intl Test Conf, Sept, pp 218–227 10. Ginetti B, Jespers P (1991) Reliability of code density test for high resolution ADCs. Electron Lett 27:2231–2233, Nov 11. Goyal S, et al. (2005) Test time reduction of successive approximation A/D converters using selective code measurement. In: Proc. Intl. Test Conf, Nov, pp 218–225 12. Kuyel T (1999) Linearity testing issues of analog to digital converters. In Proc. International Test Conference, Sept, pp 747– 756 13. Max S (2001) IEEE Std 1241: Benefits and risks of ADC histogram testing. Proc. Instrum Meas Technol Conf 1:704–709 14. Maxim IC (2000) Application note 641, ADC and DAC glossary. http://www.maxim-ic.com/appnotes.cfm/appnote_number/641, Dec 15. Maxim IC (2003) Application note 2085, Histogram testing determines INL and DNL errors. http://www.maxim-ic.com/ appnotes.cfm/appnote_number/2085, May 16. Martins RC, de Cruz Serra AM (1999) Automated ADC characterization using the histogram test stimulated by Gaussian noise. IEEE Trans Instrum Meas 48(2):471–474 Apr

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Shalabh Goyal was born in Moradabad, India, in 1979. He received the Bachelor of Technology degree in electrical engineering from the Institute of Technology—Banaras Hindu University, Varanasi, India, in 2002 and the Ph.D. degree in electrical engineering from the Georgia Institute of Technology, Atlanta, USA, in 2007.

Currently, Dr. Goyal is working with the Data Conversion Division at National Semiconductor Corporation, Santa Clara, USA. His research interests include low-cost test development for mixed-signal systems.

Abhijit Chatterjee received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Kanpur, India, in 1981, the M.S. degree in electrical engineering and computer science

J Electron Test (2008) 24:567–576 from the University of Illinois at Chicago, in 1983, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign, in 1990.

From 1983 to 1992, he was with the General Electric Corporate Research and Development Center, Schenectady, NY, USA. Since 1993, he has been with the School of Electrical and Computer Engineering, Georgia Institute of Technology, where is currently a Professor. His research interests are in the fields of computer algorithms, reliable design and test of analog and mixed-signal integrated circuits (ICs)/systems-on-packages/printed wiring boards, and design of low-power ICs and systems. In 2000, he cofounded Ardext Technologies Inc., to commercialize rapid production test of mixed-signal ICs. He has authored or coauthored over 200 papers in refereed journals and conferences and is an IEEE fellow. Dr. Chatterjee serves on the program committees of several conferences. He was the recipient of the 1993 NSF Research Initiation Award, the 1995 NSF CAREER Award, four Best Paper Awards, and three Best Paper Award nominations. In 1996, he was the recipient of the Outstanding Faculty for Research Award presented by the Georgia Institute of Technology Packaging Research Center and the 2000 Outstanding Faculty for Technology Transfer Award.