Analog Integr Circ Sig Process (2013) 76:245–249 DOI 10.1007/s10470-013-0078-y

MIXED SIGNAL LETTER

A low-complexity digital background calibration of sample-time error in time-interleaved A/D converters Amir Bazrafshan • Mohammad Taherzadeh-Sani Frederic Nabki

•

Received: 15 January 2013 / Revised: 17 March 2013 / Accepted: 8 May 2013 / Published online: 23 May 2013 Ó Springer Science+Business Media New York 2013

Abstract A digital background calibration technique to estimate the sample-time error (timing-skew) in timeinterleaved ADCs is presented. Compared to the state-ofthe-art, this technique requires a simpler digital block and, hence, a lower power dissipation. The proposed technique detects timing skew for each channel by means of finding zero-crossing samples with respect to a reference comparator. Simulation results show that it can effectively correct timing errors for any type of input signal up to Nyquist, and achieves a high convergence speed with a very low computational complexity. Keywords Time-interleaved ADC  Sample-time error  Background calibration  Zero-crossing

1 Introduction Time-interleaved analog-to-digital converters (TI-ADCs) can achieve a very high sampling rate but suffer from mismatches in offset, gain and sampling times between channels [1, 2]. Among these errors, sampling-time mismatch between channels (also called timing skew) is the most challenging, particularly at high sampling rates [1]. In this letter, a background technique to estimate the timing skew between channels (sub-ADCs) of a TI-ADC is presented. To estimate the timing skew between channels,

A. Bazrafshan (&)  M. Taherzadeh-Sani Ferdowsi University of Mashhad, Mashhad, Iran e-mail: [email protected] F. Nabki Universite´ du Que´bec a` Montre´al, Montreal, Canada

the proposed technique involves the estimation of the timing skew between each channel and a reference ADC (in this case a 1-bit ADC implemented using a single comparator). The proposed background technique is based on zerocrossing detection between each sub-ADC and the reference comparator and requires a very simple hardware implementation. Previous timing-skew calibration techniques that are based on using a reference ADC either utilize a complex technique to maximize the correlation between channels [1], employ a common reference input for channels [2], or require a very accurate reference ADC [3]. The reference comparator is sequentially synchronized to one of the sub-ADCs every (M ? 1)Ts [1], where Ts and M are the overall sampling period and the number of channels of the TI-ADC, respectively. Figure 1 shows this architecture and the associated clock signals. Thus, the reference comparator is synchronized to the same sub-ADC in every Tcal where Tcal = M(M ? 1)Ts.

2 Proposed skew detection method A method based on zero-crossing detection between each sub-ADC and a reference 1-bit ADC (implemented using a comparator) is presented. This technique estimates the timing skew Dt between all the channels by estimating it between each channel and the reference comparator. Here, we assume that offset mismatch does not exist between channels. This can be realized using any offset calibration technique. Assume that one of the sub-ADCs is under calibration. When the reference ADC samples at time instant T = mTcal (where m is the sampling index), due to the timing skew Dt between the reference ADC and the subADC (which samples at time instant T ? Dt), the sign of

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Analog Integr Circ Sig Process (2013) 76:245–249

Fig. 1 a Time-Interleaved ADC with calibration system and, b timing of clock signals

Phase Generator

0

y0[n]

ADC0 Detection

1

x(t)

Digital Backend

0

t

1

t

2

t

ADC1 R

y1[n]

ADC_REF

t

R

ADC0

ADC1

(a)

ADC2

(b)

the sampled signal in the sub-ADC (X[m]) and reference ADC (R[m]) may be opposite for some samples. These samples are considered as ‘‘zero-crossing’’ samples [2, 4]. Figure 2 shows one example of zero-crossing samples when the input signal is ascending and Dt [ 0. In order to estimate the value of Dt, in the following analysis, a variable is defined such that its mean value is proportional to Dt. Consequently, this variable is used in a least-mean-square (LMS) loop which will eventually converge to an estimated value for Dt. Consider a zero-crossing condition as shown in Fig. 2 where Dt is the timing skew, Dt1 is the time difference between the reference ADC sampling time and when the input signal crosses zero, and Dt2 is the time difference between when the input signal crosses zero and sub-ADC sampling time (note that Dt1 ? Dt2 = Dt). For a small Dt, when a zero-crossing happens, since the input signal is around zero, the input signal can be approximated as (see Fig. 2):

where X0 [m] is the derivative of the input signal at the zerocrossing instant (note that, using (1), X0 [m] = a). Thus combining with (2):

XðtÞ ¼ a  ðt  T  Dt1 Þ

S½m ¼ sign½xððr þ 1ÞðTs þ Dta ÞÞ  sign½xððr  1ÞðTs þ Dtb ÞÞ

ð1Þ

where T = mTcal and a is the derivative of the input signal when it crosses zero. Therefore, considering Fig. 2, the sampled signal in the sub-ADC (X[m]) and reference ADC (R[m]) can be written as: X½m ¼ a  Dt2

ð2Þ

R½m ¼ a  Dt1

ð3Þ

E½m ¼ a2 Dt2

Moreover, since Dt1 ? Dt2 = Dt, and Dt1 and Dt2 are two similar random variables1, their means are equal such that: Dt1 ¼ Dt2 ¼ Dt=2

0

E½m ¼ X½m  X ½m

ð6Þ

Therefore, the mean value of E[m] is proportional to Dt and can be directly used in an LMS loop (Sect. 3) to estimate the value of Dt. However, in a sampled system, finding the value of X0 [m] is not straightforward and requires high-order digital filter. To avoid this complexity in the digital domain, X0 [m] is approximated by its sign value S[m] which can be directly estimated by subtracting the sign of previous and next sub-ADC outputs: ð7Þ

where r = M(M ? 1)m, Dta and Dtb are the clock skew errors corresponding of the next and previous channels, respectively. Note that, this estimation holds true only for input signals up to Nyquist. Thus, in the digital domain, using (4) and (7), E[m] can be eventually calculated from: E½m ¼ X½m  S½m

Here, we define an error signal

ð5Þ

ð8Þ

ð4Þ 3 Convergence-loop summary

t=m.Tcal

X [m] Δt1

R[m]

Δt2

t

Δt=Δt1+Δt2=constant Fig. 2 Zero-crossing of a sampled signal showing timing skew Dt [ 0 between a sub-ADC sample and reference ADC sample

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In order to use E[m], to estimate the value of Dt, it should be used in an LMS loop as follows. Initial Step. DT[1] = 0 1

When a zero-crossing occurs between the sampling instants of the reference ADC and the ADC channel, it can randomly happen any time between them. Thus, Dt1 and Dt2 are considered as similar random variables.

Analog Integr Circ Sig Process (2013) 76:245–249

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Fig. 3 Timing skew calibration architecture for an ADC channel

Phase Generator Accumulator

LOGIC

(-1)n

(-1)n S/H

ADC 0

X(t)

+

Σ

μ0 ADC REF 1-Bit

S/H

M+1

Zero-Crossing Detection

Acc.

μ Derivative sign Detection

Comparator Offset Calibration

Prev. channel

Next channel

Table 1 Timing skew and offset mismatches among the 8 ADC channels Ch.1

Ch.2

Ch.3

Ch.4

Ch.5

Ch.6

Ch.7

Ch.8

Offset (mV)

16

-12

14

19

-21

Clock skew (ps)

35

-30

18

27

-25

12

14

-18

16

-39

-21

Fig. 4 Convergence of algorithm for an 8-channel TI-ADC: a estimated sample-time error (clock skew), and b detected zero-crossing samples

Step 1. Correct the output based on the estimated DT Step 2. Update DT using the following update equation: 

DT½m þ 1 ¼ DT½m þ l  X½m  S½m when zero - crossing occurs DT½m þ 1 ¼ DT½m otherwise

ð9Þ where DT[m] is the estimated value for Dt and l is the update step size2 of the LMS loop. Step 3. Goto step 1. 2

This update step size controls the speed of the DT convergence. However, its value is normally very small to reduce the effect of E[m] variance on the estimation of DT.

This LMS loop will converge to DT = Dt, where zerocrossings will rarely happen after executing step 1. The architecture of the calibration system is shown in Fig. 3. For the correction block, analog delay elements can be used [1]. This figure also shows chopping-based offset calibration to enhance the operation of the algorithm. Removing the offset helps the algorithm to converge without fluctuations.

4 Simulation results In simulation, we consider an 8-Bit, 2 Gs/s TI-ADC with 8 channels (sub-ADCs). Table 1 shows the considered offset

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Fig. 5 Spectra of a 960 MHz signal sampled with a 8-channel TI-ADC with Timing skew and offset mismatches: a before calibration, and b after calibration Table 2 Comparison of the proposed method with that of [1] Computational operations (For channel 1)

Hardware for each channel

Convergence Time (ms)

Frequency range

*500,000 Add operations in a calibration cycle

1 calibratedcomparator

377

Non-limited, even over Nyquist

converged in 20 cycles

1 Adder (large)

Proposed technique without offset calibration

Converged in 60,000 calibration samples

1 divider 1 simple comparator

2.2

Up to Nyquist

2400 ZC found resulting in 2400 Add operations

Several logic gates

Proposed technique with offset calibration

Converged in 20,000 calibration samples

Added hardware for offset calibration:

\1

Up to Nyquist

Only 470 add operations needed

2 choppers

[1]

1 accumulator

1 first-order IIR filter with a signed shift 1 subtractor

and timing skew mismatches for all channels. Moreover, the reference comparator has a 10 mV offset which we did not calibrate in this simulation. A wide-band stationary signal with a frequency spectrum from zero to 1 GHz is applied as the input signal. A small value l = 2-5 was used for the LMS loop. Figure 4(a) shows the output of the accumulator (which is the estimated value for timing skew) for channel 1. In Fig. 4(b), the zero-crossing samples are shown. The algorithm converged in 20,000 samples, and only 470 zerocrossing samples were found. This means that only 470 add operations in the accumulator are needed to estimate each channel’s timing skew. Therefore, the proposed calibration technique is expected to require very low power consumption. In Fig. 5(a, b), the spectra of a 960 MHz

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sinusoidal input before and after calibration are shown. Before calibration, spurious components decrease the ENOB of the overall ADC to 2.9 bit. After calibration, the SNR increases and the ENOB reaches 7.2 bit.

5 Conclusion In this letter, a simple digital background calibration technique with simple hardware requirements and, thus, low power consumption was presented. Table 2 compares the presented method with a recently published efficient technique presented in [1]. The technique in [1] is based on correlation, whereas, our proposed technique is based on zero-crossing detection.

Analog Integr Circ Sig Process (2013) 76:245–249

References 1. El-Chammas, M., & Murmann, B. (2011). A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration. IEEE Journal of Solid-State Circuits, 46(4), 838–847. 2. Wang, C.-Y., & Wu, J.-T. (2009). A multiphase timing-skew calibration technique using zero-crossing detection. IEEE Transactions on Circuits and Systems I, 56(6), 1102–1114. 3. Liu, W., & Chiu, Y. (2012). Time-interleaved analog-to-digital conversion with online adaptive equalization. IEEE Transactions on Circuits and Systems I, 59(7), 1384–1395. 4. Barnett, J. T., & Kedem, B. (1991). Zero-crossing rates of functions of Gaussian processes. IEEE Transactions on Information Theory, 37(4), 1188–1194.

Amir Bazrafshan received his B.Sc. from University of Guilan, Iran, in 2008, and his M.Sc. from Ferdowsi University of Mashhad, Iran, in 2012. His research interests include Analog Integrated Circuits and Digital Signal Processing.

Mohammad Taherzadeh-Sani received his B.Sc. from Ferdowsi University of Mashhad, Iran, in 2001, his M.Sc. from the University of Tehran, Iran, in 2004, and his Ph.D. degree from McGill University, Montreal, Canada, in 2011. His Ph.D. research focused on the design of reconfigurable pipelined ADCs for multi-standard communications. He was awarded the J.W. McConnell Memorial Fellowship from McGill University for his doctoral research. Dr. Taherzadeh-Sani joined Ferdowsi University of Mashhad, Iran, in

249 2012, where he is currently an Assistant Professor in the Electrical Engineering Department. His research is on analog and mixed-signal ICs for communication systems and biomedical applications. Frederic Nabki (S’99–M’10) received the B.E. degree in electrical engineering with Honors from McGill University, Montreal, QC, Canada, in 2003, and the Ph.D. degree in electrical engineering from McGill University in 2010. In 2008, he joined the ‘‘Universite´ du Que´bec a` Montre´al’’ (UQAM), Montreal, QC, Canada, where he is currently an Associate Professor in microelectronics engineering. His research interests are mixedsignal and radiofrequency integrated circuits and microelectromechanical systems (MEMS) for various applications including sensing and communications. Some research projects include the design of novel low-power and high speed analog-to-digital converters, CMOS phase-locked loops, ultra-wideband transceivers, and wired communication channels. In addition, Dr. Nabki is active in research projects involving the creation of next generation MEMS fabrication processes using advanced materials, the integration of MEMS devices with CMOS systems, and the modeling of MEMS devices. Dr. Nabki is a member of the Quebec Order of Engineers, and is a recipient of the Governor General of Canada’s Academic Bronze Medal. He has received a mention of excellence in teaching, and has previously held scholarships from the Microsystems Strategic Alliance of Quebec (ReSMiQ), the Quebec Fund for Research in Nature and Technology (FQRNT), and the Natural Sciences and Engineering Research Council of Canada (NSERC).

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