Analog Integr Circ Sig Process DOI 10.1007/s10470-017-0966-7

Design and implementation of a 94 GHz CMOS down-conversion mixer with integrated miniature planar baluns for image radar sensors Yo-Sheng Lin1

•

Kai-Siang Lan1 • Chien-Chin Wang1 • Guo-Hao Li1

Received: 6 August 2015 / Revised: 25 June 2016 / Accepted: 28 March 2017 Ó Springer Science+Business Media New York 2017

Abstract A 94 GHz down-conversion mixer for image radar sensors using standard 90 nm CMOS technology is reported. The down-conversion mixer comprises a doublebalanced Gilbert cell with peaking inductors between RF transconductance stage and LO switching transistors for conversion gain (CG) enhancement and noise figure suppression, a miniature planar balun for converting the single RF input signals to differential signals, another miniature planar balun for converting the single LO input signals to differential signals, and an IF amplifier. The mixer consumes 22.5 mW and achieves excellent RF-port input reflection coefficient of -10 to -35.9 dB for frequencies of 87.6–104.4 GHz, and LO-port input reflection coefficient of -10 to -31.9 dB for frequencies of 88.2–110 GHz. In addition, the mixer achieves CG of 4.9–7.9 dB for frequencies of 81.8–105.8 GHz (the corresponding 3-dB CG bandwidth is 24 GHz) and LO–RF isolation of 37.7–47.5 dB for frequencies of 80–110 GHz, one of the best CG and LO–RF isolation results ever reported for a down-conversion mixer with operation frequency around 94 GHz. Furthermore, the mixer achieves an excellent input third-order intercept point of -3 dBm at 94 GHz. These results demonstrate the proposed downconversion mixer architecture is promising for 94 GHz image radar sensors. Keywords CMOS  94 GHz  Down-conversion mixer  Planar balun  Conversion gain  Noise figure  LO–RF isolation & Yo-Sheng Lin [email protected] 1

Department of Electrical Engineering, National Chi Nan University, Puli, Taiwan, ROC

1 Introduction In the past, III–V compound semiconductor and SiGe BiCMOS technologies were adopted in most W-band (75–110 GHz) communication systems [1–3], such as 76–77 GHz long range automotive radar system, 77–81 GHz short range automotive radar system, 81–86 GHz high-speed point-to-point wireless communication access system, and 94 GHz imaging radar sensor for autonomous vehicles. Recently, thanks to the rapid development of CMOS processes, it has become possible to use them to implement W-band radio-frequency integrated circuits (RFICs) [4, 5]. In transceiver design, down-conversion mixer (or demodulator) is a critical block that receives signals from LNA over the whole band of interest, and then amplifies and down-converts (or demodulates) the signals with a good signal to noise-plus-distortion ratio (SNDR) property. In addition to low power consumption, the basic requirements for a down-conversion mixer include good input and output impedance matching, high port-to-port isolation, low noise figure (NF), and high conversion gain (CG) over the band of interest. Recently, several excellent GaAs down-conversion mixers for operation frequencies around 94 GHz have been reported [6–8]. For example, in [6], a 90–112 GHz image reject down-conversion mixer with an improved Lange coupler in 0.15 lm GaAs PHEMT process is demonstrated. Though wide bandwidth of 22 GHz was achieved, its performances such as CG of -10 dB, LO–RF isolation of 30 dB, and chip area of 4 mm2 are not good enough. In [7], a 90–97 GHz single balanced down-conversion mixer using a rat-race hybrid ring with five ports and two GaAs Schottky diodes is reported. Though wide bandwidth of 7 GHz was achieved, its conversion gain of -12.6 is not satisfactory. In [8], a 94 GHz single balanced down-

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Analog Integr Circ Sig Process

conversion mixer using branch line couplers in 0.1 lm GaAs process is demonstrated. Similarly, its performances such as CG of -14.7 dB, LO–RF isolation of 34.2 dB, and chip area of 3.38 mm2 are not good enough. In this work, to demonstrate that low power dissipation (\25 mW), high CG ([4 dB), excellent LO–RF isolation ([35 dB) and small chip area (\1 mm2) can be achieved simultaneously for a CMOS down-conversion mixer with operation frequency around 94 GHz, we report a miniature low-power 94 GHz down-conversion mixer with excellent CG, 3-dB bandwidth and port-to-port isolation properties in 90 nm CMOS. The mixer comprises a double-balanced Gilbert cell with two Marchand baluns for converting the single RF and LO input signals to differential signals, and an IF amplifier. CG enhancement is achieved by optimizing the impedance matching between RF-port Marchand balun and RF transconductance stage, and by including peaking inductors between RF transconductance stage and LO switching transistors.

2 Circuit design The 94 GHz down-conversion mixer was designed and implemented in a 90 nm CMOS process provided by a commercial foundry. This technology offers 9 metal layers, named MT1 to MT9 from bottom to top. The interconnection lines as well as the microstrip-line (MSL) inductors were implemented with the 3.4-lm-thick topmost metal (MT9) to minimize the resistive loss. Figure 1 shows the block diagram of the proposed 94 GHz down-conversion mixer. The mixer comprises a double-balanced Gilbert cell, two Marchand baluns, and an IF amplifier. The design of the down-conversion mixer and its Marchand balun is described in the following. Figure 2(a) shows the schematic of the 94 GHz CMOS down-conversion mixer, in which the equivalent

inductance, capacitance and resistance of the adopted MSL inductors, MIM capacitors and polysilicon resistors, respectively, are also labelled. The mixer comprises a double-balanced Gilbert cell, a miniature planar Marchand balun for converting the single RF input signal to differential signal, another miniature planar Marchand balun for converting the single LO input signal to differential signal, and an IF amplifier (which constitutes a resistive sourcedegeneration differential amplifier followed by a sourcefollower buffer amplifier). Note that the double-balanced Gilbert cell has peaking inductors (TL7 and TL8) between the RF transconductance stage and the LO switching transistors for CG improvement and NF suppression. In addition, for wideband RF-port input impedance matching and CG enhancement, inductive source-degeneration (TL5 and TL6) technique (with low quality (Q) factor) is also used in RF transconductance stage [9–11]. With the addition of the tail current source which consists of transistor M7 and resistor R7, the RF transconductance stage operates as an elegant, yet robust differential pair. The current of the tail current source is also mirrored to the IF buffer amplifier constitutes transistors M10–M13 and resistors R11–R12. The driving current of the IF buffer amplifier can be tuned by varying the resistance of resistors R11–R12. All the transistors (M1–M13) have the same gate-length of 0.1 lm. The gate-width-per-finger of transistors M1–M6, M7–M9 and M10–M13 is 4 lm, 5 lm and 2 lm, respectively. The finger-number of transistors M1–M6, M7, M8–M11 and M12– M13 is 3, 20, 64 and 20, respectively. The down-conversion mixer is biased in the condition of VDD = 1.3 V, IDD = 18 mA, VG1 = 0.55 V, VG2 = 0.8 V and VG3 = 0.6 V. That is, the simulated power consumption of the downconversion mixer is 23.4 mW. The chip micrograph of the mixer is shown in Fig. 2(b). The chip area is only 0.6990.84 mm2 excluding the test pads. The reason why the gain-enhancement transconductance stage can effectively enhance CG and bandwidth, and

This Work (On-Chip) Gilbert-Cell Double-Balanced Down-Conversion Mixer

Antenna

LNA

RFin 90 ~ 100 GHz

IF Amp.

Marchand Balun

Marchand Balun

LOin 89.9 ~ 99.9 GHz

Fig. 1 Block diagram of the proposed 94 GHz down-conversion mixer

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IFout 0.1 GHz

Analog Integr Circ Sig Process

VDD = 1.3 V

R5 = 570 Ω

R6 = 570 Ω

R9 = 174 Ω

R8 = 174 Ω M8

VG3 = 0.6 V

C1 = 26.7 fF

LOin

TL1 = 47.6 pH RFin

C2 = 26.7 fF

TL2 = 47.6 pH

Marchand C3 = Balun 26.7 fF C4 = 26.7 fF C5 = 26.7 fF

R3 = 920 Ω

M11

M9 R10 = 26.6 Ω

IF+ IF−

R2 = 920 Ω

R1 = 920 Ω

Marchand C6 = Balun 26.7 fF

M10

M1

M3

M2

TL7 = 14.3 pH TL3 M5 23.9 pH

TL5

TL6

19.1 pH 19.1 pH

M4

TL8 = 14.3 pH M6 TL4

Wideband Matching & Gain Bandwidth

23.9 pH M12

R7 = R4 = 920 Ω 26.6 Ω VG2 = VG1 = 0.8 V 0.55 V

M7

Down-Comversion Mixer Core

R11 = 26.6 Ω

R12 = 26.6 Ω

M13

IF amplifier

(a)

(b) Fig. 2 (a) Schematic diagram, (b) chip micrograph of the 94 GHz CMOS down-conversion mixer

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reduce the power consumption of the down-conversion mixer is explained as follows. For simplicity, the degeneration inductors TL5/TL6 of the transconductance stage are assumed to be negligible, which is usually the case. Suppose the differential RF input voltages are vRF ðtÞ ¼ vRF cosðxRF tÞ, the differential output currents (originating from the RF transconductance stage) at the source terminals of the LO transistors are iRF ðtÞ, and the differential LO input signals are square-wave with 50% duty cycle. Then Iout? - Iout- is equal to the product of iRF and a square-wave toggling between -2 and 2. For the traditional RF transconductance stage without the seriespeaking inductors TL7/TL8, iRF ðtÞ ¼ gm5;6 VRF cosðxRF tÞ. So the fundamental component of the IF output signal can be written as vout;IF ðtÞ ¼ R5;6 ðIoutþ  IoutÞ   4 1 xRF  R5;6 ¼ gm5;6  vRF cos xIF t  tan p x0 1  rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  2ffi ; 1 þ xxRF0 ð1Þ in which gm5,6 is the transconductance of the RF input transistors M5/M6. x0 is the 3-dB corner frequency of the low-pass transfer function of the RF transconductance stage, which can be expressed as follows. Gm;LO þ 1=Rds5;6 x0  ; Cds5;6 þ CLO

ð2Þ

in which Gm,LO and CLO are the equivalent input conductance and the equivalent input capacitance, respectively, looking into the source terminals of the LO switching transistors M1/M2 (or M3/M4). Rds5,6 and Cds5,6 are drainsource resistance and drain-source capacitance, respectively, of the RF input transistors M5/M6. The magnitude of CG of the down-conversion mixer is given by 2 1 CG ¼ gm5;6  R5;6  rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  2ffi p 1 þ xxRF0

ð3Þ

Around the operation frequency of 94 GHz, xRF =x0  1 is normally satisfied. Then (3) can be simplified (to a oneorder monotonously decreasing function) as follows: 2 x0 2 CG ¼ gm5;6  R5;6   gm5;6  R5;6 p p xRF

ð4Þ

This means for millimeter-wave down-conversion mixers, parasitic capacitance at the output terminal of the RF transconductance stage may degrade CG to a large extent. On the other hand, for the transconductance stage in this work (with series-peaking inductors TL7/TL8), suppose

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CLO and L7,8 (the equivalent inductance of the transmission-line inductors TL7,8) are series resonant (i.e. short) around the operation frequency of 94 GHz (i.e. 1 þ s2 L7;8 CLO  0). Then the equivalent load of the RF transconductance stage is a parallel RLC network. The corresponding impedance is given by   1 1 1 þ ZL ¼ sCeff þ sLeff Reff !1 1 1  ¼ sCds5;6 þ þ sL7;8 ðL7;8 Gm;LO =CLO ÞRds5;6 ð5Þ Suppose L7,8 and Cds5;6 are parallel resonant (i.e. open) around the operation frequency of 94 GHz (i.e. 1 + s2 L7;8 Cds5;6  0), then (5) can be simplified as follows: L7;8 Gm;LO  Rds5;6  L7;8 Gm;LO ZL ¼ CLO   CLO L7;8 Gm;LO if Rds5;6  CLO

ð6Þ

The fundamental component of the IF output signal around the operation frequency of 94 GHz can be written as vout;IF ðt) ¼ R5;6 ðIoutþ  Iout Þ 4  gm5;6  vRF cos(xIF t)  R5;6 ; p

ð7Þ

The CG of the down-conversion mixer is given by 2 CG  gm5;6  R5;6 p

ð8Þ

Compare Eqs. (4) and (8), it is clear that CG and bandwidth can be improved by including the series-peaking gain enhancement inductors TL7/TL8 in the RF transconductance stage. In addition, for a specific CG specification, this work corresponds to a smaller gm5,6 value, which leads to a smaller power consumption. Figure 3(a) shows the schematic diagram of the miniature planar Marchand balun used in the mixer. It is designed based on the ‘‘lumped-element’’ Marchand balun structure proposed in [12]. Such a balun structure is advantageous because of its excellent amplitude/phase match and broadband response when compared with the traditional single-to-differential transformers [13, 14]. The traditional straight-line or U-shaped MSL Marchand balun structure adopts whole or dense MT1 ground plane underneath and around the balun. Hence, it normally occupies large chip area and suffers high loss (mainly due to the eddy current loss on MT1 plane). To minimize the chip area, spiral coil MSL structure is used to implement the inductors in the Marchand balun. To minimize the overall eddy current loss on the MT1 ground plane and the silicon substrate, EM simulation is done to find the optimal density

Analog Integr Circ Sig Process

Patterned MT-1 Ground Plane (MT1 Density ~ 56%) 10 μm

2 μm

6.3 μm

7.7 μm

88 μm O.C.

MT9 Port 3 MT8 (50 Ω)

14.8 μm

19.6 μm

MT9

MT8

Patterned MT1 GND Plane

2 μm

259 μm

GND

Port 2 MT8 (50 Ω)

10.6 μm

214 μm

Port 1 (50 Ω) 178 μm

(a)

(b)

Marchand Balun C

Port 3 (Out+) L

2C

O.C. L

50 Ω L Port 2 (Out−)

C

λ/4

Port 1 Port 3

L

(c) Port-1 50 Ω VS

T

C

I λ/4

50 Ω

VS

Port 1 (In)

IN

Port 2 Port 4

50 Ω

50 Ω

(d) λ/4

λ/4

IN

T

T II Port 2

C λ/4

50 Ω

Port 3 50 Ω

IN

I

C λ/4

(e) Fig. 3 (a) Schematic diagram, (b) metal-1 patterned ground plane, (c) lump-element equivalent circuit of the proposed 94-GHz-band Marchand balun. (d) Four-port k/4 coupled line network, (e) planar Marchand balun network with two back-to-back k/4 coupled line

of the MT1 patterned ground shield (PGS) [15]. The result shows MT1 PGS density of 56% corresponds to the maximal coupling S21 and S31 (i.e. minimal loss). This explains why MT1 PGS density of 56%, as shown in Fig. 3(b), is used in this work. The metal width and space are 4 lm and 2 lm, respectively. The balun consists of an unbalanced input (Port 1) with 50 X terminal impedance, an open terminal (O.C.), two short terminals (GND) and two

balanced outputs (Port 2 and Port 3) with 50 X terminal impedance. Note that the coils of the balun are implemented by the 3.4-lm-thick topmost metal (MT9) to minimize the resistive loss. Only the underpass interconnection lines are realized by MT8. Compared with the traditional Marchand balun structure using the whole or dense MT1 ground plane, simulation shows 0.7 dB improvement in S21 and S31 can be achieved in this work.

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Analog Integr Circ Sig Process

Figure 3(c) shows the lump-element balun equivalent circuit [12]. The spiral coil couple-line is modeled by the lump inductor L, and the capacitor C models the coupling capacitance effect produced from the spiral coil coupleline. That is, the capacitors are realized as the parasitic components of the inductors. Port 1 is the unbalanced RF input port (or LO input port), and port 2 and port 3 are the balanced RF? and RF- output port (or LO? and LOoutput port), respectively. In a network, this lump-element balun can be regarded as an out-of-phase power splitter, including a parallel-connected high-pass filter and a bandpass filter. The signals through the output ports of the ideal balun have equal power but are 180° out-of-phase; all ports (except the O.C. port) have an input impedance of 50 X (i.e. Z0). The Marchand balun can also be analyzed as follow: the planar Marchard balun in Fig. 3(a) is equivalent to two quarter-wavelength (k/4) coupled lines [composed of two coupled transmission lines, as shown in Fig. 3(d)] connected back-to-back, as shown in Fig. 3(e). There are four ports for coupled line, i.e. input (IN), through (T), coupled (C), and isolation (I). For the two coupled ports, they both connected with short terminal. The two through ports are connected directly. For the two input ports, one is the unbalanced input of the Marchand balun, and the other is connected with an open terminal. For simplicity, suppose the coupled lines are lossless, which is usually close to this case for a planar Marchand balun on a silicon substrate with medium or high resistivity. Under the matching condition of Z0eZ0o = Z20, where Z0 is the terminal impedance (50 X), and Z0e and Z0o are even-mode and odd-mode characteristic impedance of the transmission lines in the coupled lines. At the center frequency of 94 GHz, the scattering parameter matrix of the coupled line can be expressed as follows: 2 3 0 T C 0 ½ S ¼ 4 T 0 0 C 5 2 0 C T 0 pffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3 0 j 1  C 2 C 0 pffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ 4 j 1  C2 0 0 C 5; pffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 0 C j 1  C 0 ð9Þ where C¼

Z0e  Z0o ; Z0e þ Z0o

ð10Þ

According to (9) and (10) and the configuration of the planar Marchand balun shown in Fig. 3(e), the scattering parameter matrix of the planar Marchand balun can be expressed as follows:

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3 T4 CT 3 CT 3 2 þ CTþ CT  C 6 1 þ C2 1 þ C2 1 þ C2 7 7 6 3 2 2 6 CT C T C2 T 2 7 2 2 7 6 ½S ¼ 6 CTþ T þ C  1 þ C2 1 þ C2 1 þ C2 7 7 6 4 CT 3 C2 T 2 C2 T 2 5 2 2 CT  C  T þ 1 þ C2 þ C2 þ C2 3 p1ffiffiffiffiffiffiffiffiffiffiffiffiffiffi p1ffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 2 2 1  3C 2C 1  C 2C 1  C 2 j j 6 2 2 1p þffiffiffiffiffiffiffiffiffiffiffiffiffiffi C 1þC 1 þ C2 7 7 6 2 7 6 2C 1  C2 1C 2C2 7 ¼6 j 7 6 j 1 þ C2 1 þ C2 1p þffiffiffiffiffiffiffiffiffiffiffiffiffiffi C2 7 6 5 4 2C 1  C 2 2 2 2C 1C j j 1 þ C2 1 þ C2 1 þ C2 ð11Þ 2

In this work, the coupled coefficient C is designed to be pffiffiffi equal to 1= 3. This in turn simplifies (11) as follows: 3 2 j j p ffiffi ffi p ffiffi ffi 0  6 2 27 7 6 7 6 j 7: p ffiffi ffi 0:5 j0:5 ½S ¼ 6 ð12Þ 7 6 2 7 6 5 4 j  pffiffiffi j0:5 0:5 2 From (12), it is clear that perfect input impedance matching at the input port (i.e. |S11| = 0) and ideal transmission (i.e. pffiffiffi jS21 j ¼ jS31 j ¼ 1= 2 and \S31  \S21 ¼ 180 ) at the center frequency of 94 GHz are achieved. However, the theoretical input reflection coefficient at port-2 and port-3 are only equal to -6 dB, a little away from perfect input impedance matching. This is acceptable since port 2 and port 3 of the balun are regarded as internal nodes in the design of the down-conversion mixer, they don’t have to be matched to 50 X, i.e. well below -10 dB. Figure 4(a) shows the simulated input reflection coefficients S11, S22 and S33 of the Marchand balun. S11 is equal to -11.2 dB at 94 GHz and smaller than -10 dB for frequencies of 90–110 GHz. S22 is equal to -4.66 dB at 94 GHz and smaller than -4.82 dB for frequencies of 90–100 GHz, close to the theoretical one of -6 dB (see 12). In addition, S33 is equal to -4.65 dB at 94 GHz and smaller than -4.82 dB for frequencies of 90–100 GHz, also close to the theoretical one of -6 dB (see 12). Figure 4(b) shows the simulated S21 and S31, and amplitude imbalance (AI) versus frequency characteristics of the Marchand balun. The simulated S21 is equal to -4.5 dB at 94 GHz and larger than -4.55 dB for frequencies of 90–100 GHz. The simulated S31 is equal to -4.24 dB at 94 GHz and larger than -4.29 dB for frequencies of 90–100 GHz. Besides, the simulated AI is 0.26 dB at 94 GHz and smaller than 0.3 dB for frequencies of 90–100 GHz. Figure 4(c) shows the simulated individ-

Analog Integr Circ Sig Process 0

10

Marchand Balun

Reflection Coefficient (dB)

S11 & S22 & S33 (dB)

-2 -4 -6

S11

-8

S22 S33

-10 -12 -14

90 92 94 96 98 100 102 104 106 108 110

5

RF-Port

0

LO-Port

-5

-10 dB

-10 -15 -20 -25 -30 -35

Simulation

Frequency (GHz) -40

S21 S31

5

0

4

-2

2 1 0

-1 90 92 94 96 98 100 102 104 106 108 110

(b)

105

110

IF-port

-6 -8 -10 -12 -14 -16

Simulation

-20

Marchand Balun

100

100

-4

-18

200

0.0

0.5

1.0

1.5

2.0

2.5

3.0

IF Frequency (GHz)

0

(b)

-100 230 220 S31 210 Phase Difference 200 190 180 170 90 92 94 96 98 100 102 104 106 108 110

Fig. 5 Simulated input reflection coefficients of the down-conversion mixer (a) at RF-port and LO-port and (b) at IF-port

S21

PD (degree)

Phase (Degree)

95

(a)

6

3

0 dB

90

Frequency (GHz)

Frequency (GHz)

-200

85

7

Marchand Balun

Reflection Coefficient (dB)

0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12

80

AI (dB)

S21 & S31 (dB)

(a)

Frequency (GHz)

(c) Fig. 4 Simulated (a) input reflection coefficients S11, S22 and S33, (b) coupling S21 and S31, and amplitude imbalance (AI), (c) individual phase and phase difference (PD) of S21 and S31 of the Marchand balun in Fig. 3

ual phase and phase difference (PD) of S21 and S31 of the Marchand balun. The simulated PD is 186.2° at 94 GHz and equal to 185.3°–187.5° for frequencies of 90–100 GHz. Figure 5(a) shows the simulated input reflection coefficients at RF-port (S11) versus RF frequency characteristics

of the down-conversion mixer. The mixer achieves minimal S11 of -25.1 dB at 93.3 GHz, and S11 smaller than -10 dB for RF frequencies of 83.8–105.8 GHz. That is, the -10 dB RF-port input matching bandwidth is 22 GHz. What is also shown in Fig. 5(a) is the simulated input reflection coefficients at LO-port (S22) versus LO frequency characteristics of the down-conversion mixer. The mixer achieves minimal S22 of -29 dB at 98.8 GHz, and S22 smaller than -10 dB for LO frequencies of 90–110 GHz. That is, the -10 dB LO-port input matching bandwidth is greater than 20 GHz. Figure 5(b) shows the simulated input reflection coefficients at IF-port (S33) versus IF frequency characteristics of the down-conversion mixer. The mixer achieves excellent S33 of -10.3 to - 15.3 dB for IF frequencies of 0–3 GHz.

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Analog Integr Circ Sig Process 20 This Work (w/i IF buffer Amplifier) w/o IF buffer Amplifier

Conversion Gain (dB)

15 10 5 0 -5 -10

Simulation -15 80

85

90

95

100

Frequency (GHz)

(a)

94 GHz. LO input power is 4 dBm. The corresponding input 1-dB compression point (P1dB) is -12.5 dBm. Figure 7(a) shows the simulated LO–RF isolation, LO– IF isolation and RF–IF isolation versus frequency characteristics of the down-conversion mixer. For frequencies of 90–100 GHz, the mixer achieves LO–RF isolation of 42.8–44.9 dB, LO–IF isolation of 67.3–81.2 dB and RF–IF isolation of 44.2–48.7 dB, one of the best port-to-port isolation results ever reported for a CMOS down-conversion mixer with operation frequency around 94 GHz. To characterize the non-linear behavior, two-tone signals with equal power levels and frequency difference of 1 MHz were applied to the down-conversion mixer. Twotone RF frequencies are 94 GHz and 94.001 GHz. The spectrum analyzer was set to a center frequency of 100.5 MHz and a span of 5 MHz to include the signals and

12

Simulation

140 LO-RF Isolation LO-IF Isolation RF-IF Isolation

120

8 100

Isolation (dB)

Conversion Gain (dB)

10

6 4

–12.5 dBm

2

80 60 40 20

0 -40

-35

-30

-25

-20

-15

-10

-5

Simulation

0

0

RF Input Power (dBm)

90

92

(b)

98

100

40 Pout

Output Power (dBm)

20

123

96

(a)

Fig. 6 Simulated (a) CG versus frequency characteristics, (b) CG versus RF input power characteristics at 94 GHz of the downconversion mixer

Figure 6(a) shows the simulated CG versus frequency characteristics of the down-conversion mixer both with and without the IF buffer amplifier. RF input power is -40 dBm and LO input power is 4 dBm. The mixer achieves maximal CG of 8.72 dB at 93 GHz, CG of 8.7 dB at 94 GHz, and CG of 7.82–8.72 dB for frequencies of 90–100 GHz, one of the best CG results ever reported for a down-conversion mixer with operation frequency around 94 GHz. The corresponding 3-dB bandwidth is larger than 21.8 GHz (78.2–100 GHz). In the case without the IF buffer amplifier, the mixer achieves inferior maximal CG of 0.85 dB at 95 GHz, CG of 0.84 dB at 94 GHz, and CG of 0.36–0.85 dB for frequencies of 90–100 GHz. The corresponding 3-dB bandwidth is larger than 21.1 GHz (78.9–100 GHz). Figure 6(b) shows the simulated CG versus RF input power characteristics of the down-conversion mixer at

94

Frequency (GHz)

Pout,IM3

0 -20 -40 -60

IIP3 = –1.5 dBm

-80 -100 -30

-25

-20

-15

-10

-5

0

5

10

RF Intput Power (dBm)

(b) Fig. 7 Simulated (a) LO–RF isolation, LO–IF isolation and RF–IF isolation versus frequency characteristics, (b) fundamental and thirdorder inter-modulation output power at 94 GHz of the downconversion mixer

Analog Integr Circ Sig Process 10

Reflection Coefficient (dB)

the responses induced by circuit non-linearity. Figure 7(b) shows the simulated fundamental (Pout) and thirdorder intermodulation output power (Pout,IM3) for RF input power of -30 to - 5 dBm. The simulated Pout and Pout,IM3 are -21.3 dBm and -78.3 dBm, respectively, for RF input power of -30 dBm. This means the corresponding input third-order intercept point (IIP3) is -12.5 dBm. Figure 8 shows the simulated NF versus frequency characteristics of the down-conversion mixer. The mixer achieves minimal NF of 23 dB at 94 GHz, and NF of 23–25.6 dB for frequencies of 80–100 GHz.

5

Measurement

0

Simulation

-5

–10 dB

-10 -15 -20 -25 -30 -35

RF-Port

-40

3 Results and discussion

80

85

90

95

100

105

110

105

110

Frequency (GHz)

(a) 10

Reflection Coefficient (dB)

On-wafer measurements were performed by an Agilent’s 110 GHz RFIC measurement system. Careful calibration has been done to make sure the measured results are reliable. The down-conversion mixer is biased in the condition of VDD = 1.3 V, IDD = 17.3 mA, VG1 = 0.55 V, VG2 = 0.8 V and VG3 = 0.6 V. That is, the simulated power consumption of the down-conversion mixer is 22.5 mW. Figure 9(a) shows the measured and simulated input reflection coefficients at RF-port (S11). The mixer achieves excellent measured minimal S11 of -35.9 dB at 95 GHz, and S11 lower than -10 dB for frequencies of 87.6–104.4 GHz (i.e. the -10 dB input matching bandwidth is 16.8 GHz). This is comparable to that of the simulated one, whose minimal S11 is -25.1 dB at 93.3 GHz, and S11 is lower than -10 dB for frequencies of 83.8–105.8 GHz (i.e. the -10 dB input matching bandwidth is 22 GHz). According to the theory in [9], the input matching bandwidth of S11 is inversely proportional to the equivalent input inductance at RF input port, and the minimal S11 occurs at the LC series resonant frequency of

5

Measurement

0

Simulation

-5

–10 dB

-10 -15 -20 -25 -30 -35

LO-Port -40 80

85

90

95

100

Frequency (GHz)

(b) Fig. 9 Measured and simulated (a) input reflection coefficients at RF-port, (b) input reflection coefficients at LO-port versus frequency characteristics of the down-conversion mixer

40 NF

35

NF (dB)

30 25 20 15 10 5

Simulation 0 80

85

90

95

100

Frequency (GHz)

Fig. 8 Simulated NF versus frequency characteristics of the downconversion mixer

the RLC series input network. The small discrepancy between the measured and simulated ones is due to the fact that the LC value estimated by the EM simulation tool and the ADS model provided by the foundry may not be accurate enough at high frequency around 94 GHz. Figure 9(b) shows the measured and simulated input reflection coefficients at LO-port (S22). The mixer achieves excellent measured minimal S22 of -31.9 dB at 101.5 GHz, and S22 lower than -10 dB for frequencies of 88.2–110 GHz (i.e. the -10 dB input matching bandwidth is greater than 21.8 GHz). This is comparable to that of the simulated one, whose minimal S22 is -29 dB at 98.8 GHz, and S22 is lower than -10 dB for frequencies of 90–110 GHz (i.e. the -10 dB input matching bandwidth is greater than 20 GHz). According to the theory in [9], the input matching bandwidth of S22 is inversely proportional

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Analog Integr Circ Sig Process

FOM [1] =

CG½1  BW½GHz  IIP3½mW ; ðNF  1Þ½1  PDC ½mW  f T ½GHz

Measurement

25

Conversion Gain (dB)

Simulation 20 15 10 5 0 -5 -10 80

85

90

95

100

105

110

105

110

Frequency (GHz)

(a) 80 Measurement

70

LO-RF Isolation (dB)

Simulation 60 50 40 30 20 10 0 80

85

90

95

100

Frequency (GHz)

(b) 40 35 30 25 20 15 10 Simulation Measurement

5 0 80

82

84

86

88

90

92

94

96

98 100

Frequency (GHz)

ð13Þ

where CG [1] represents the average conversion gain in magnitude; BW[GHz] represents the 3 dB bandwidth in GHz; IIP3[mW] represents the input third-order intercept point in mW; (NF - 1) [1] represents the excess NF in magnitude; PDC[mW] represents power dissipation in mW;

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30

NF (dB)

to the equivalent input inductance at LO input port, and the minimal S22 occurs at the LC series resonant frequency of the RLC series input network. The small discrepancy between the measured and simulated ones is also due to the fact that the LC value estimated by the EM simulation tool and the ADS model provided by the foundry may not be accurate enough at high frequency around 94 GHz. Figure 10(a) shows the measured and simulated CG versus frequency characteristics of the down-conversion mixer with the IF amplifier. The measured result conforms with the simulated one well. The mixer achieves maximal CG of 7.9 dB at 91 GHz and CG of 4.9–7.9 dB for frequencies of 81.8–105.8 GHz, one of the best CG results ever reported for a down-conversion mixer with operation frequency around 94 GHz. The corresponding 3-dB bandwidth is 24 GHz (81.8–105.8 GHz). The small discrepancy between the measured and simulated ones can be explained as follows: as can be seen from Fig. 10(a), the shape of the measured CG curve is close to that of the simulated one except being a little shifted downward. Since the CG (especially the peak CG) of the mixer is mainly related to the equivalent transconductance (gm) of the transistors used, the small discrepancy is due to the fact that the ADS model provided by the foundry is not accurate enough at high frequency around 94 GHz. Figure 10(b) shows the measured and simulated LO–RF isolation versus frequency characteristics of the downconversion mixer. The mixer achieves excellent measured LO–RF isolation of 37.7–47.5 dB for frequencies of 80–110 GHz, one of the best LO–RF isolation results ever reported for a down-conversion mixer with operation frequency around 94 GHz. This is comparable to that of the simulated one (40.9–45.1 dB for frequencies of 80–110 GHz). Furthermore, the mixer achieves an excellent input third-order intercept point (IIP3) of -3 dBm at 94 GHz (not shown here). Figure 10(c) shows the measured and simulated NF versus frequency characteristics of the down-conversion mixer. The mixer achieves excellent measured NF of 22.3–24.7 dB for frequencies of 80–100 GHz, comparable to that of the simulated one (23–25.6 dB for frequencies of 80–100 GHz). A figure of merit (FOM) suitable for evaluating the performance of a wideband down-conversion mixer, a lownoise amplifier or a receiver front-end can be defined as below [9–12]:

(c) Fig. 10 Measured and simulated (a) CG versus RF frequency characteristics, (b) LO–RF isolation versus frequency characteristics, (c) NF versus frequency characteristics of the down-conversion mixer

and fT[GHz] represents the cut-off frequency of the technology used in GHz. This FOM includes the most relevant

NA

189/334 GaAs MHEMT (100) 3.38

GaAs Schottky Diode NA

34.2

0.5 94

94

Rat-race hybrid-ring with five ports and two diodes

Single-balanced using branch line couplers

[7] (2010 ICMMT)

[8] (2012 GSMM)

0.325

NA

NA -12.6

-14.7

NA

130/128

NA GaAs PHEMT (150)

CMOS (90) 0.58

4

22.5

NA

47.5

30

7.9

10

0.1

[6] (2011 MTT-S)

6

94

94

Gilbert-cell with source-follower output buffer

Image-reject with improved lange coupler

This work

fT/fmax (GHz) Technology (nm) Chip area (mm2) Power (mW) LO–RF isolation (dB) CG (dB) IF frequency (GHz) RF frequency (GHz) Topology References

Table 1 Summary of the implemented 94 GHz CMOS down-conversion mixer, and recently reported state-of-the-art down-conversion mixers with operation frequency around 94 GHz

Analog Integr Circ Sig Process

parameters for evaluating down-conversion mixers for low-power, high CG, low-noise, high linearity and wideband applications. The mixer achieves an excellent FOM of 6.05 9 10-5. Table 1 is a summary of the implemented 90–100 GHz CMOS down-conversion mixer, and recently reported state-of-the-art GaAs down-conversion mixers with operation frequency around 94 GHz. Compared with the 90–112 GHz image reject down-conversion mixer in [6], the proposed mixer exhibits better CG and LO–RF isolation, and smaller chip area. Compared with the 90–97 GHz single balanced GaAs down-conversion mixer in [7], the proposed mixer exhibits better CG. Compared with the 94 GHz single balanced GaAs down-conversion mixer in [8], the proposed mixer exhibits better CG and LO–RF isolation, and smaller chip area. These results indicate that our proposed down-conversion mixer with integrated Marchand baluns is suitable for W-band transceiver systems.

4 Conclusions In this work, we report a 90–100 GHz CMOS downconversion mixer comprises a double-balanced Gilbertcell, a miniature planar RF Marchand balun, a miniature planar LO Marchand balun, and an IF amplifier. The mixer consumes 22.5 mW and achieves excellent CG of 4.9–7.9 dB for frequencies of 81.8–105.8 GHz, that is, the corresponding 3-dB bandwidth of RF is 24 GHz. Moreover, excellent LO–RF isolation is also achieved. These results highlight the potential application of the proposed down-conversion mixer architecture in 94 GHz and even higher frequency communication systems. Acknowledgements This work is supported by the Ministry of Science and Technology (MOST) of the ROC under Contract MOST103-2221-E-260-027-MY3. The authors are very grateful for the support from CIC, Taiwan, for chip fabrication, and NDL, Taiwan, for RF measurements.

References 1. Hwang, Y. J., Wang, H., & Chu, T. H. (2004). A W-band subharmonically pumped monolithic GaAas-based HEMT gate mixer. IEEE Microwave and Wireless Components Letters, 14(7), 313–315. 2. Jain, V., Tzeng, F., Zhou, L., & Heydari, P. (2009). A singlechip dual-band 22–29-GHz/77–81-GHz BiCMOS transceiver for automotive radars. IEEE Journal of Solid-State Circuits, 44(12), 3469–3485. 3. Chen, A. Y. K., Baeyens, Y., Chen, Y. K., & Lin, J. (2010). A low-power linear SiGe BiCMOS low-noise amplifier for millimeter-wave active imaging. IEEE Microwave and Wireless Components Letters, 20(2), 103–105.

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Analog Integr Circ Sig Process 4. Lin, Y. S., Wen, W. C., & Wang, C. C. (2014). 13.6 mW 79 GHz CMOS up-conversion mixer with 2.1 dB gain and 35.9 dB LO– RF isolation. IEEE Microwave and Wireless Components Letters, 24(1), 495–497. 5. Zhang, N., Xu, H., Wu, H. T., & Kenneth, K. O. (2009). W-band active down-conversion mixer in bulk CMOS. IEEE Microwave and Wireless Components Letters, 19(2), 98–100. 6. Wu, Y. C., Lin, S. K., Chiong, C. C., Tsai, Z. M., & Wang, H. (2011). A W-band image reject mixer for astronomical observation system. In IEEE MTT-S international microwave symposium (pp. 1–4). 7. Zhao, W., Zhang, Y., & Zhan, M. Z. (2010). Design and performance of a W-band microstrip rat-race balanced mixer. In International conference on microwave and millimeter wave technology (pp. 713–716). 8. Lee, S. J., Baek, T. J., Han, M., Choi, S. G., Ko, D. S., & Rhee, J. K. (2012). 94 GHz MMIC single-balanced mixer for FMCW radar sensor application. In Global symposium on millimeter waves (pp. 351–354). 9. Wang, T., Chen, H. C., Chiu, H. W., Lin, Y. S., Huang, G. W., & Lu, S. S. (2006). Micromachined CMOS LNA and VCO by CMOS compatible ICP deep trench technology. IEEE Transactions on Microwave Theory and Techniques, 54(2), 580–588. 10. Chang, J. F., & Lin, Y. S. (2011). A high-performance distributed amplifier using multiple noise suppression techniques. IEEE Microwave and Wireless Components Letters, 21(9), 495–497. 11. Chiu, H. W., Lu, S. S., & Lin, Y. S. (2005). A 2.17 dB NF, 5 GHz band monolithic CMOS LNA with 10 mW DC power consumption on a thin (20 lm) substrate. IEEE Transactions on Microwave Theory and Techniques, 53(3), 813–824. 12. Yeh, P. C., Liu, W. C., & Chiou, H. K. (2005). Compact 28-GHz subharmonically pumped resistive mixer MMIC using a lumpedelement high-pass/band-pass balun. IEEE Microwave and Wireless Components Letters, 15(2), 62–64. 13. El-Gharniti, O., Kerherve´, E., & Be´gueret, J. B. (2007). Modeling and characterization of on-chip transformers for silicon RFIC. IEEE Transactions on Microwave Theory and Techniques, 55(4), 607–615. 14. Long, J. R. (2000). Monolithic transformers for silicon RFIC design. IEEE Journal Solid-State Circuits, 35(9), 1368–1382. 15. Lin, Y. S., Chen, C. Z., Liang, H. B., & Lu, S. S. (2007). Highperformance on-chip transformers with partial polysilicon patterned ground shields (PGS). IEEE Transactions on Electron Devices, 54(1), 157–160.

Yo-Sheng Lin (M’02-SM’06) was born in Puli, Taiwan, on Oct. 10, 1969. He received his Ph.D. in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1997. His Ph.D. thesis was on the fabrication and study of GaInP–InGaAs–GaAs doped-channel field-effect-transistors and their applications to monolithic microwave integrated circuits (MMICs). He joined Taiwan Semiconductor Manufacturing Company (TSMC) in 1997 as a Principle Engineer for 0.35/0.32 lm DRAM and 0.25 lm embedded DRAM technology development in the Integration Department of Fab-IV. Since 2000, he has been responsible for 0.18/0.15/0.13 lm CMOS low-power device technology development in the Department of Device Technology and Modeling, R&D, and was promoted to Technical Manager in 2001. In

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August 2001, he joined the department of Electrical Engineering, National Chi Nan University (NCNU), where he became a Full Professor in August 2006 and a Chair Professor in August 2014. He has been the Dean of Office of Research and Development since December 2012, and the Chair of Department of Electrical Engineering since August 2014. He is a fellow of IET. He was a recipient of the Outstanding Engineering Professor Award from Taichung Branch of Chinese Institute of Engineers in 2015, a recipient of the Excellent Research Award from NCNU in 2006 and 2014, a recipient of the Outstanding Young EE Engineer Award from Chinese Institute of Electrical Engineering in 2007, and a recipient of the Excellent Teaching Award from NCNU in 2011 and 2014. From June to September, 2004, he was a visiting researcher at the High-Speed Electronics Research Department, Bell Laboratories, Lucent Technologies, Murray Hill, NJ, USA. From February 2007 to January 2008, he was appointed as Visiting Professor at the department of Electrical Engineering, Stanford University, USA. His current research interests are in the areas of characterization and modeling of RF active and passive devices (especially 30–100 GHz interconnections, inductors and transformers for millimeter-wave (Bi) CMOS integrated circuits), and radiofrequency integrated circuits (RFICs)/monolithic microwave integrated circuits (MMICs). Kai-Siang Lan is currently pursuing Ph.D. degree in Electrical Engineering, National Chi Nan University, Nantou, Taiwan. His current research interests include the design, implementation and test of millimeter-wave CMOS VCOs, dividers, PLLs, and transceivers.

Chien-Chin Wang was born in I-Lan, Taiwan, ROC, on February 24, 1985. He received the B.S. and M.S. degrees in electrical engineering from National Chi Nan University, Puli, Taiwan, in 2008 and 2010, respectively, where he is currently working toward the Ph.D. degree. His master thesis was related to Ka-band and W-band frequency dividers. His current research interests focus on the BFSK transceiver, sigma-delta DAC and audio amplifier for wireless biomedical sensor network SOC.

Analog Integr Circ Sig Process Guo-Hao Li was born in Tainan, Taiwan, ROC, on November 29, 1989. He received the B.S. and M.S. degrees in electrical engineering from National Chi Nan University, Puli, Taiwan, in 2012 and 2014, respectively. His master thesis was related to W-band CMOS down-conversion mixer. His current research interests focus on the transceivers for W-band communication systems.

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