J Low Temp Phys (2016) 184:217–224 DOI 10.1007/s10909-016-1522-z

Development for Germanium Blocked Impurity Band Far-Infrared Image Sensors with Fully-Depleted Silicon-On-Insulator CMOS Readout Integrated Circuit T. Wada1 · Y. Arai2 · S. Baba1,3 · M. Hanaoka4 · Y. Hattori4 · H. Ikeda1 · H. Kaneda4 · C. Kochi1,3 · A. Miyachi1 · K. Nagase1,5 · H. Nakaya6 · M. Ohno7 · S. Oyabu4 · T. Suzuki1 · S. Ukai4 · K. Watanabe8 · K. Yamamoto1,5 Received: 21 September 2015 / Accepted: 21 January 2016 / Published online: 8 February 2016 © Springer Science+Business Media New York 2016

Abstract We are developing far-infrared (FIR) imaging sensors for low-background and high-sensitivity applications such as infrared astronomy. Previous FIR monolithic imaging sensors, such as an extrinsic germanium photo-conductor (Ge PC) with a PMOS readout integrated circuit (ROIC) hybridized by indium pixel-to-pixel interconnection, had three difficulties: (1) short cut-off wavelength (120 µm), (2) large power consumption (10 µW/pixel), and (3) large mismatch in thermal expansion between the Ge PC and the Si ROIC. In order to overcome these difficulties, we developed (1) a blocked impurity band detector fabricated by a surface- activated bond technology, whose cut-off wavelength is longer than 160 µm, (2) a fully-depleted silicon-on-insulator CMOS ROIC which works below 4 K with 1 µW/pixel operating power, and (3) a new concept, Si-supported Ge detector, which shows tolerance to

B

T. Wada [email protected]

1

Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa 252-5210, Japan

2

High Energy Accelerator Research Organization, Tsukuba, Ibaraki 305-0801, Japan

3

Department of Physics, The University of Tokyo, Bunkyo, Tokyo 113-0033, Japan

4

Department of Physics, Nagoya University, Nagoya, Aichi 464-8602, Japan

5

Department of Space and Astronautical Science, The Graduate University for Advanced Studies, Sagamihara, Kanagawa 252-5210, Japan

6

National Astronomical Observatory of Japan, Mitaka, Tokyo 181-8588, Japan

7

National Institute of Advanced Industrial Science and Technology, Tsukuba, Ibaraki 305-8568, Japan

8

Research Center for Advanced Science and Technology, The University of Tokyo, Meguro, Tokyo 153-8904, Japan

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thermal cycling down to 3 K. With these new techniques, we are now developing a 32 × 32 FIR imaging sensor. Keywords

Infrared astronomy · Infrared detectors · Cryogenic CMOS ROIC

1 Introduction Far-infrared (FIR) wavelengths (30–200 µm) provide important tools to study the formation of planets, stars, and galaxies. UV-to-optical light from young bright stars and active galactic nuclei (AGNs) is absorbed by inter-stellar dust and the energy is re-emitted in the FIR wavelength. Approximately 50 % of the energy is emitted in the FIR wavelength [1]. Gallium-doped germanium (Ge:Ga) extrinsic photo-conductors (PCs) and cryoPMOS readout integrated circuits (ROICs) were used in the previous space infrared astronomical observatories, such as AKARI [2], Spizer [3], and Herschel Space Observatory [4]. In AKARI, they developed an FIR image sensor with 3 × 20 pixels covering wavelengths of 50–100 µm [5]. Another FIR image sensor was on board for 100–200 µm but which was not a monolithic array of detectors because a stressing mechanism was required to extend the cut-off wavelength from that of Ge:Ga PC (120 µm) to 200 µm. The format (the number of pixels) was limited by large power consumption of the PMOS ROIC and a large mismatch in the thermal expansion between the Ge PC and the silicon (Si) ROIC. In this paper, we describe how we overcome these problems and develop a large format monolithic FIR image sensor. In Sect. 2, we describe our development of Ge:Ga blocked impurity band (BIB) detector which is the key to extend the cut-off wavelength beyond 120 µm without the stressing mechanism. In Sect. 3, we describe our development of fully-depleted silicon-on-insulator (FD-SOI) CMOS ROIC which is the key to realize a low-power ROIC. In Sect. 4, we propose a new approach to overcome the problem of the thermal expansion mismatch, “Si-supported Ge detector” and “microcone-shaped Au-bump hybridization,” and show the result of a cryogenic thermal test. Our goal is to develop a large format (32 × 32) FIR image sensor which can be used for natural background- limited observation with cryogenic cooled infrared space telescopes, such as SPICA [6]. Current status and future works for the development of the FIR image sensor are described in Sect. 5.

2 Development of Ge BIB Detector A BIB detector consists of a highly doped IR absorption layer and a pure blocking layer [7]. Higher doping (>1016 /cc) results in higher IR absorption and also results in faster relaxation by impurity band conduction (IBC) compared with those of the conventional PCs which have typically lower doping (2 × 1014 /cc). The formation of the impurity band reduces the band gap between the dopant state and the valence band and thus extends the cut-off wavelength. The pure layer reduces the dark current caused by the IBC.

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J Low Temp Phys (2016) 184:217–224 Table 1 Characteristics of the BIB devices fabricated by the SAB

Device width & length

219 1 mm × 1 mm

IR absorption layer Thickness

0.5 mm

Dopant concentration

1016 /cc (Ga)

Blocking layer Thickness

0.5 mm

Carrier concentration

< 4 × 1012 /cc (p-type)

Device performance Dark current [11]

< 5 fA

Responsivity [12]

2 A/W

Cut-off wavelength [12]

160 µm

NEP

√ < 2 × 10−17 W/ Hz

A high-quality crystal is required both for the IR absorption layer and the blocking layer. We have used room-temperature surface-activated bonding (SAB) technique [8] to fabricate the BIB structure because of the following reasons. First, we can choose the best wafers both for the IR absorption layer and the blocking layer. Second, we can avoid impurity migration by diffusion from the IR absorption layer to the blocking layer. High-temperature processes, such as chemical vapor deposition and liquid phase epitaxy, were improper ways in terms of the impurity migration. Table 1 shows the characteristics of our BIB devices fabricated by the SAB technique. The noise equivalent power (NEP) is calculated by taking account of shot noise of the dark current and the responsivity. The details of fabrication and characterization of the device are described elsewhere [9–12].

3 Development of FD-SOI CMOS ROIC The basic ROIC consists of a pixel amplifier with an integration capacitor, a pixel reset switch, row and column selectors, and an output amplifier (Fig. 1). ROICs in the previous missions used PMOS architecture [13] or CMOS architecture with strict constraint on the use of NMOS FETs [14] because NMOS FETs showed kink and hysteresis at the cryogenic temperature [15]. We found that both PMOS and NMOS FETs which were fabricated by FD-SOI CMOS process showed excellent performance at cryogenic temperature [16], and have started the development of CMOS ROIC. We fabricated CMOS OPAMP and confirmed superior performance compared with that of PMOS OPAMP [17–19], and have successfully demonstrated a capacitive transimpedance amplifier (CTIA) at 4.2 K with 1 µW power consumption. We measured the off-leakage current of an NMOS FET reset switch with a gate width/length ratio (W/L) of W/L = 5 µm/10 µm at 4.2 K and that was less than 1.5 × 10−16 A with |VDS | ∼ 1 V [18]. We also fabricated CMOS analog switches which were designed to be used for the row and column selectors [20]. Other elements which are necessary

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to configure the ROIC, such as digital logic circuits, have also been developed. One important point is that we have used FD-SOI CMOS process which is a commercial one without special modification.

4 Development of Si/Ge Hybridization The thermal expansion mismatch makes it difficult to fabricate a large Ge detector hybridized on an Si-based ROIC. In order to overcome this difficulty, we propose to fabricate thin Ge BIB detectors on an IR-transparent Si support wafer. Figure 2 shows the proposed architecture. Because the thin Ge detector is supported by the thick Si support wafer, thermal expansion mismatch against the Si ROIC becomes negligible. Without the Si support wafer, considering the coefficients of thermal expansion of Ge and Si (5.8 × 10−6 /K and 2.6 × 10−6 /K, respectively), cooling from 300 to 2 K leaves 0.1 % expansion mismatch, and this gives 3 µm shift between Ge detector and Si ROIC in case of the 32 × 32 array with 100 µm pitch. With the Si support wafer (500 µm in thickness), the mismatch between the thin (10 µm) Ge detector with Si support wafer and the ROIC is reduced by a factor of 100, considering Young’s modulus of Ge and Si (103 and 185 GPa, respectively). We fabricated the thin Ge detector with the Si support wafer

Reset integration capacitor

X selector

Y selector output buffer

pixel-to-pixel connection

unit-cell op-amp

detector Vbias

GND

Fig. 1 Simplified schematic diagram of ROIC sub-wavelength structure anti-reflection

FIR photon

transparent handle wafer (Si) IR photons reach IR active layer without absorption Metal via to common contact ROIC external PADs

~500μm

common transparent contact IR active layer (Ge:Ga) Blocking layer (Ge)

~10μm ~1μm

pixel ohmic contact micro-cone-shaped Au-bumps

~500μm

FD-SOI CMOS ROIC (Si)

Fig. 2 The proposed architecture of the FIR image sensor using Si-supported Ge BIB detector and FD-SOI CMOS ROIC hybridized by micro-cone-shaped Au-bumps (Color figure online)

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transparent handle wafer (Si) ROIC external bonding pad

IR active layer (Ge)

internal pad for bump

micro-cone-shaped Au-bump

221

500μm

10μm

300μm

FD-SOI CMOS ROIC (Si)

Fig. 3 Left Architecture of the demonstration FIR image sensor using Si-supported Ge photo-conductor and FD-SOI CMOS ROIC hybridized by micro-cone-shaped Au-bumps fabricated by the NpD technique. The pixel pitch is 200 µm. Among the 9×9 pixels, 41 pixels are directly connected to their own external bonding pads, of which 36 are used for the cryogenic thermal cycling test. Right Photograph of the demonstration device of the FIR image sensor. The size of ROIC is 3 mm × 6 mm × 0.3 mm and that of Si-supported Ge detector is 2 mm × 2 mm × 0.5 mm. The detector is in the front and the ROIC is behind (Color figure online)

by SAB technique, and have confirmed that the bonding interface between Ge and Si survives a thermal cycle between 300 and 4 K. We adopt a micro-cone-shaped Au-bump technology fabricated by nano-particle deposition (NpD) technique [21] to make pixel-to-pixel interconnection between the ROIC and the Ge detector. Au-bumps have higher chemical and mechanical tolerance compared with the conventional In bumps. Au-bumps fabricated by the NpD are easy to deform and have large margin in height compared with conventional Au-bump. Transparent/Ohmic contact on the Ge detector is fabricated by an MBE technique [22]. Anti-reflection is realized by sub-wavelength structure layer [23]. A demonstration device, which consists of the Si-supported Ge detector and a 9 × 9 pixel FD-SOI CMOS ROIC, has been fabricated by the micro-cone-shaped Au-bump hybridization in order to demonstrate the tolerance of this structure to the thermal expansion mismatch. The Si-supported Ge detector consists of a 9 × 9 pixel array with a pixel pitch of 200 µm. We employ conventional extrinsic germanium photo-conductor as Ge detector for simplicity. A Hall effect measurement at 4-300 K shows that the Ge material has two p-type impurities, one has band-gap energy of 10 meV and the other with 30 meV. The total impurity concentration is estimated to be ∼ 1 × 1013 /cc. The ROIC also has 9 × 9 pixels, of which 40 have a CTIA for each pixel and 41 have a direct connection to an external bonding pad for each pixel. We use 36 of the 41 pixels with the pads for a thermal cycle test described later. The architecture and photograph of the demonstration device are shown in Fig. 3. Note that ohmic contacts were not formed between the internal pads and the Ge detector. In order to demonstrate the tolerance of this structure to the thermal expansion mismatch, we have performed the thermal cycle test down to 3 K. The device is installed in a vacuum chamber with a pulse tube cryo cooler. The device is cooled down to 3 K in a day, and warmed up to 300 K in a week. In order to confirm that the device is not damaged by the thermal expansion mismatch, we measure resistance of the Ge pixels through the micro-cone-shaped Au-bumps via the external bonding pads.

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Fig. 4 Left Map of ratio of resistance before and after thermal cycle test. The average is 1.04 and the standard deviation is 0.01. The systematic measurement error is 5 %. Right Map of resistance at 3 K, normalized to the highest one (289 k, pixel 15th) (Color figure online)

1e+06

9x9Au-bump Ge pixel g(x) h(x)

800 1e+06 700

1e+05 1e+05

1e+03 1e+02

1e+03 1e+01 1e+00

1e+02

1e-01 1e+01

0

50

100

150

200

Temperature (K)

250

300

∫(αGe-αSi) dT (10-6)

1e+04

600

Resistivity (ohm cm)

Resistance (ohm)

1e+04

500

400

300

200

100

0

0

50

100

150

200

250

300

Temperature (K)

Fig. 5 Left Red crosses show resistance as a function of temperature during the thermal cycle (pixel 22nd). Blue x-marks show resistivity of the Ge material measured by Hall effect. The exponential curves, g(x) and h(x), are guides to the eye and correspond to thermal excitation of 30 and 10 meV band-gap energies, respectively. Right Integrated thermal expansion mismatch between Si and Ge [24]. Most of mismatch happens in temperature above 50 K, and there is no large mismatch below it. Our experiment is done at 3 K but the result can be extrapolated to the operation temperature of the Ge BIB device (2 K) (Color figure online)

We have measured the resistance of the Ge pixels for the 36 pixels with the pads before (300 K), at 3 K, and after the thermal cycle (300 K). The average and the standard deviation of the resistance are 995  and 41  (before) and 1033  and 45  (after the cycle), respectively. Figure 4 (left) shows the map of the ratio between the resistance at 300 K before and after the thermal cycle. The ratio is almost close to unity (the average is 1.04 and the standard deviation is 0.01) and this result shows that the device keeps good electrical connection even after the cryogenic thermal cycle. Figure 4 (right) shows the map of resistance at 3 K normalized to that of the maximum. No pixel shows disconnection. This result shows that the device keeps electrical connection even at 3 K. Large dispersion in the resistance at 3 K is due to carrier freeze-out of the Ge material and the absence of Ohmic contact.

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223

We have also monitored the resistance of a Ge pixel (number 22nd) during the cooling down to 3 K in order to confirm that the measured resistance is mainly due to the resistance of Ge detector, not leakage at the bump nor ROIC. Figure 5 (left) shows the results. No disconnection has been observed from 300 to 3 K. The resistance of the Ge detector as a function of temperature can be explained by the resistivity of the Ge material measured by Hall effect above 30 K. This confirms that the measured resistance is dominated by the resistance of the Ge detector, and that the Si-support Ge structure and the electrical connection via Au-bumps are not short-circuited nor disconnected. The structure and connection will not be destroyed below 50 K because most of the mismatch happens at temperatures above 50 K and there is no large mismatch below it (Fig. 5 right) [24]. Actually, we see clear feature of thermal excitation current by dopants in Ge (Fig. 5 left), and this shows that the Si-support Ge structure and the electrical connection via Au-bump are not broken during the thermal cycle down to 3 K. The above results show that the Si-support Ge structure and the electrical connection via Au-bumps have tolerance to the thermal cycle down to 3 K.

5 Development Plan of FIR Image Sensor As described in the previous sections, we have developed the basic technologies to fabricate large format monolithic array of detectors. We are now developing the 32×32 FIR image sensor for natural background-limited observations with cryogenic cooled infrared space telescopes, such as SPICA which is planned to be launched in 2028. In order to achieve background-limited performance in space FIR observations, the √ NEPs below 1 ×√10−18 W/ Hz (λ/δλ = 10) are required [25]. The current NEP (∼ 1 × 10−17 W/ Hz) of the Ge BIB detector is not low enough for this requirement. In order to meet the requirement, we plan to reduce the NEP by a factor of 10. The current NEP of the BIB detector is dominated by the shot noise of the dark current. Because the shot noise is proportional to the square root of the dark current, and because the dark current is proportional to the pixel area, the NEP is proportional to the detector pixel size. We plan to reduce the pixel size from 1 mm × 1 mm to 0.1 mm × 0.1 mm. A 32 × 32 FD-SOI CMOS CTIA ROIC with a pixel size of 0.1 mm × 0.1 mm has just been fabricated. The ROIC is designed to be operated with a power consumption of 1 mW at 2 K which satisfied the SPICA’s thermal requirement. The 32 × 32 Sisupported Ge BIB detector is planned to be fabricated in 2016, and hybridization with micro-cone-shaped Au-bump is planned in 2017.

6 Summary We are developing FIR imaging sensors employing the Ge BIB detector and the FD-SOI CMOS ROIC with pixel-to-pixel interconnection. We have successfully demonstrated Ge BIB detectors fabricated by the SAB technology whose cut-off wavelengths are longer than 160 µm without any stressing mechanism. We have also demonstrated CMOS OPAMPs with the FD-SOI technique, which work at 4 K with

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1 µW operating power. Other elements which are necessary to configure the ROIC, such as reset switch, digital logic and analog switch, have also been developed. We have proposed Si-supported Ge detector architecture in order to overcome the mismatch in thermal expansion between the Ge detector and the Si ROIC, and have demonstrated their tolerances by the thermal cycling test of the 9 × 9 FIR image sensor. Since the necessary technologies for the 32 × 32 FIR image sensor are now ready, we have started to develop it for future cryogenic cooled infrared space telescopes. Acknowledgments This work was supported by JSPS KAKENHI Grant Numbers 20244016, 23340053, and 25109005. The authors thank Mitsubishi Heavy Industry Co., Ltd. for their large effort in the fabrication of SAB BIB device. The authors also thank LAPIS Semiconductor Co., Ltd. for their large effort in the fabrication of the FD-SOI CMOS device. The authors thank TDY Inc. and Tohnic Inc. for their support on Ge detector development. The authors thank Tohoku-Microtec Co., Ltd. for their support on micro-cone-shaped Au-bump.

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