Journal of VLSI Signal Processing 21, 183–184 (1999) c 1999 Kluwer Academic Publishers. Manufactured in The Netherlands. °

Guest Editors’ Introduction The theme of this special issue reflects the importance given to System Level Design, which has been identified as a dominant research theme for the next decade. New visionary approaches at the system design level are needed to exploit the great opportunities created by the continuous advances in technology and miniaturization of the semiconductor devices. System design is converging on a paradigm which includes general purpose commodity chips (i.e., processors, memories, DSP) and full custom mixed analog and digital application specific integrated circuits (ASICs) glued together by programmable gate arrays on custom printed circuit boards, or complete silicon boards (system-on-a-chip). The impact has also been made by recent advances in silicon architectures, high throughput interfacing techniques, embedded memories, reconfigurable logic, and low power circuits and architectures. These hardware systems will be driven by custom, real time software that utilizes the latest software design paradigms (i.e., object oriented languages, browser interfaces) and wireless communications to provide users with unique functionality—either stand-alone or in collaboration with other distributed systems. To be effective, these systems must be optimized taking into account a variety of constraints including complexity, power consumption, heat dissipation, mechanical packaging, ergonomics, and design effort. Traditionally, design has followed a sequential water-fall model resulting in severely constrained design trade-offs. Only recently have multi-disciplinary teams begun concurrent design wherein the effect of interactions between trade-offs within disciplines is becoming apparent. Such trade-offs are not yet supported by CAD tools. Also, a much closer interaction between the components introduces a whole new set of constraints. The design industry is sending a strong message that innovation at the system design level is a necessity. This special issue on System Design includes the following eight articles: The first article, “Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management” by Verkest, da Silva, Ykman, Croes, Miranda, Wuytack, de Jong, Catthoor, and De Man, describes a design environment and support for applications that require manipulation of a large amount of dynamically allocated stored data. Matisse bridges the gap from a system specification, using a concurrent object oriented language, to an optimized embedded single chip hardware/software implementation. The authors have demonstrated the results of system design exploration using an industrial ATM application, and achieved significant improvements in area usage and power consumption. The second article, “Low-Power Parallel Video Compression Architecture for a Single-chip Digital CMOS Camera” by Hsieh and Meng, describes a large-scale parallel architecture which is designed to operate in an integrated environment. Namely, a low-power parallel video compression architecture for a single-chip digital CMOS camera is designed for highly computationally intensive image and video processing tasks. The authors present two designs of this architecture, an MPEG2 encoder and a DV encoder, and discuss performance tradeoffs. Integration technologies offer significant gains in power consumption and processing architecture flexibility. However, at the same time integration implies less flexibility in the process optimization of individual technologies. The third article, “Subsetting Behavioral Intellectual Property for Low Power ASIP Design” by Dougherty, Pursley, and Thomas, defines the notion of instruction subsetting and explores its use as a means of reducing power consumption from the system level of design. Key to this approach is the re-use of intellectual property (IP), specifically that of a general or DSP processor. The experiments have shown that using instruction subsetting to create application specific instruction set processors (ASIPs) from existing behavioral IP is a viable approach to low power system design through rapid design space exploration. This method of instruction subsetting provides an opportunity to re-use existing IP at both behavioral and RT levels.

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The fourth article, “Energy-Delay Efficient Data Storage and Transfer Architectures Methodologies” by Catthoor, characterizes the current state of system level memory management related methodologies in respect to energy efficiency. It indicates that novel methodology and architecture approaches are required for systems-on-a-chip with a heterogeneous mix of processors. The target domain includes all real-time data-dominated applications, which deal with large amounts of complex data types. The major steps of their data transfer and storage exploration (DTSE) methodology and important research results are discussed. The author argues that the use of appropriate data representation models is very important. The fifth article, “Hierarchical Mixed-Domain Circuit Simulation, Synthesis and Extraction Methodology for MEMS” by Mukherjee and Fedder, deals with three portions of the MEMS (microelectromechanical systems) design methodology. The mixed-domain circuit simulation, synthesis, and extraction tools form the core of a top-down integrated electronics/MEMS design methodology. The key questions addressed by the authors are: Is decoupling between technology people and physics on one hand and designers and electronics on the other hand possible with MEMS; how the system level design is to be done, i.e., the level of mixing electronics with MEMS cells; how is the mapping from system specifications to MEMS cells performed. The authors propose a hierarchical structured design methodology for integrated microsystems that is compatible with standard VLSI design. The sixth article, “System Level Design as Applied to CMU Wearable Computers” by Smailagic and Siewiorek, describes a system level design approach to the wearable computers project at CMU. The multidisciplinary design process and interactions among disciplines are described. A system level approach to power/performance optimization is emphasized. Energy efficiency must be considered in all phases of system design. A metric for comparison of wearable computers has been introduced, indicating almost five orders of magnitude improvement in performances of CMU wearable computers running speech recognition applications. This paper is giving us a look at the practical application of system level design as well. The seventh article, “Fault Detection and Automated Fault Diagnosis for Embedded Integrated Electrical Passives” by Yoon, Hou, Bhattacharya, Chatterjee, and Swaminathan, emphasizes the importance of embedded MCM passive components in the development of mixed-signal MCMs, and also the need for novel test techniques for fault detection and diagnosis. These embedded passives are used in the area of wireless communication systems. The development of embedded integrated passives is the key to develop highly integrated mixed-signal modules. Testing of these embedded integrated RF-passives is difficult due to the analog nature of passive components, the inaccessibility of internal circuit nodes, and the high frequency of circuit operation. The authors propose fault detection and automated fault diagnosis technique using pole/zero analysis in embedded integrated RF-passives. A practical example is presented to verify the pole/zero analysis using a fabricated embedded RC device. Finally, “High-Level Embedded System Specifications Based on Process Activation Conditions” by Bosung, Huss, and Klaus, presents a CoDesign Model (CDM) for specification of a high-level functional description of new hardware/software system. Path-cyclic graph structures with conditional input/output relations for description of iterative data manipulation have been introduced and evaluated. A digital image processing system has been used as a case study. We believe that the coming decade will be as revolutionary for the system level design, as the last ten years have been for the design of microprocessor-based systems, and the previous ten years had been for IC design. Asim Smailagic Carnegie Mellon University Hugo De Man IMEC, Belgium