J Electron Test (2015) 31:443–459 DOI 10.1007/s10836-015-5548-y

Phase Noise Testing of Analog/IF Signals Using Digital ATE: A New Post-Processing Algorithm for Extended Measurement Range Stéphane David-Grignot 1,2 & Florence Azaïs 1 & Laurent Latorre 1 & François Lefevre 2

Received: 26 March 2015 / Accepted: 30 October 2015 / Published online: 13 November 2015 # Springer Science+Business Media New York 2015

Abstract This paper deals with low-cost phase noise testing of sinusoidal analog/IF signals. The idea is to perform oversampled 1-bit signal acquisition using standard digital ATE and to apply dedicated post-processing in order to retrieve the phase noise level present in the analog/IF signal from the captured binary vector. A first algorithm has already been developed, which shows an excellent agreement with conventional phase noise measurements on a large range of injected noise but diverges from conventional method in case of very low phase noise level. In this paper, we present a new processing algorithm that permits to alleviate this limitation. Both simulations and hardware measurements are realized to validate the technique and results clearly demonstrate the improved performance of the new algorithm.

Keywords Analog signals . Digital ATE . Digital signal processing . Noise measurement . One bit acquisition . Phase noise . Analog/RF integrated circuits . Test cost reduction

Responsible Editor: K.- T. Cheng * Florence Azaïs [email protected] Stéphane David-Grignot [email protected] Laurent Latorre [email protected] François Lefevre [email protected] 1

LIRMM, CNRS / Université Montpellier, 161 rue Ada, 34095 Montpellier, Cedex 5, France

2

NXP Semiconductors, 2 Espl. Anton Phillips, 14000 Caen, France

1 Introduction Analog and RF devices are nowadays essential components of modern integrated systems and they are used in a number of application domains such as communication and multimedia, transportation, home automation, healthcare… The current industry practice for testing these devices is specificationbased testing, wherein the performances promised in the data sheet are measured and compared to their specification limits. This approach involves very high testing costs since it necessitates the use of dedicated high-performance analog/RF test instruments. In this context, researchers have searched for ways of eliminating the need to use expensive analog/RF resources during mass production testing and a promising approach is to develop all-digital test methods. A number of works can be found in the literature following this approach, in particular regarding phase noise and jitter measurement. Note that phase noise refers to the frequency domain representation of short-term random fluctuations in the phase of a periodic signal, caused by time-domain instabilities (Bjitter^) [22]. Generally speaking, radio frequency engineers speak of the phase noise of an analog signal, whereas digital system engineers work with the jitter of a clock. In this paper, we focus on phase noise measurement for complex RF devices, eg. silicon tuners, wireless microcontrollers, … For such devices, phase noise is usually measured on the analog output signal delivered at Intermediate Frequency (IF) and corresponds to the accumulated phase noise contribution of the various elements present along the signal path. Numerous works have been published related jitter measurement on clock signals [3, 4, 13, 16, 24, 25]. However the literature is less prolix regarding digital methods for phase noise measurements on analog signals. Some works rely on the use of Time Interval Analyzer (TIA) to acquire time-

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domain data related to crossing points of the analyzed signal; these data are then digitally processed to extract phase noise characteristics [5, 14]. The same approach is adopted in [9], which proposes detection of sinusoidal phase noise at a particular frequency, from the analysis of time-domain data captured by a Time-to-Digital Converter (TDC) and InfiniteImpulse Response (IIR) filtering. More recently, we have proposed solutions based on oversampled 1-bit signal acquisition associated with dedicated digital post-processing algorithm [6, 7, 17]. The major benefit of these techniques is that they do not require the use of TIA or TDC for precise timing measurements but just rely on the standard resources available in a digital ATE channel. However because they are based on oversampled acquisition, these techniques only target analog devices or complex RF devices that have an output in the intermediate frequency (IF) range. Finally note that another approach to reduce phase noise testing costs is to integrate the resources required to perform phase noise analysis within the circuit itself, and on-chip measurement solutions have been proposed [10, 15, 18, 19]. In this paper, we present an improved implementation of the digital method proposed in [7]. The paper is organized as follows. Section 2 presents both the conventional method and the low-cost digital method for phase noise measurement in production test environment; the limitation of the proposed digital method is also illustrated. Section 3 is devoted to the analysis of this limitation, through a number of simulation and hardware experiments. Development of the new processing algorithm is then detailed in section 4 and experimental results are presented in section 5. Finally, conclusions are drawn in section 6.

2 Background and Previous Work 2.1 Conventional Measurement Traditionally, phase noise measurement relies on analog methods in order to evaluate the frequency-domain characteristics of phase noise, using spectrum analyzers or dedicated analog measurement systems [11, 20]. In the context of high-

Fig. 1 Conventional industrial setup for phase noise measurement

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volume production test, this purely analog instrumentation is usually replaced by a DSP-based tester, which comprises waveform synthesizer and digitizer for the generation and capture of analog signals, interfaced with a powerful Digital Signal Processor (DSP). For phase noise production test, the Signal Under Test (SUT) is captured by the high-performance digitizer and the resulting digitized samples are stored in the ATE memory, as illustrated in Fig. 1. These data are then transferred to the DSP for further processing. In particular, the spectrum of the signal is computed from FFT applied on the digitized samples and phase noise is evaluated by subtracting the signal level to the noise level present in a 1 Hz bandwidth at a given frequency offset from the signal frequency. Note that alternative digital processing algorithms have also been proposed in the literature [1, 2, 12] to derive phase noise characteristics from digitized data. 2.2 Digital Technique In order to reduce the testing costs, the objective is to perform signal acquisition with a standard digital ATE instead of the expensive analog capture resources [21, 23], as required by the conventional method. As illustrated in Fig. 2, the SUT is oversampled and converted into a serial bitstream by means of the comparator and the latch comprised in a digital tester channel, and the resulting binary vector is stored in the ATE memory; a dedicated post-processing algorithm is then applied on recorded data to retrieve the phase noise characteristics of the analog signal. Using this approach, a first post-processing algorithm has been proposed in [6], which is based on a virtual analog signal generated from captured binary data; FFT is then applied on the virtual signal to perform phase noise measurement. The main drawbacks of this solution are that FFT is still required and that high oversampling ratio is necessary. To palliate these issues, another post-processing algorithm has been developed in [7], which is based on instantaneous frequency reconstruction and analysis of instantaneous frequency deviations. This algorithm constitutes the foundation of the work presented in this paper and is summarized hereafter.

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Fig. 2 Industrial setup for the proposed digital technique

Let us consider an analog sinusoidal signal s(t) affected with phase noise: sðt Þ ¼ A⋅sinð2π f o t þ ϕo þ Δϕðt ÞÞ

ð1Þ

where A and fo are nominal values of amplitude and signal frequency respectively, ϕo is the initial signal phase, and Δϕ(t)d is the time-varying phase instability called phase noise. This analog signal s(t) is passed through a 1-bit quantizer operating at a sampling rate fs =k⋅fo, where k is an integer value (preferably odd) corresponding to the oversampling ratio. The resulting signal is a binary vector V[n] expressed with:
1 if sðnT sÞ≥ V th V ð nÞ ¼ n ¼ 1…N ð2Þ 0 else where Ts =1/fs is the sampling clock period, N is the number of captured samples, and V th is the quantizer threshold voltage. As illustrated in Fig. 3, estimations of the instantaneous frequency fbo ðmÞ can be computed from the captured binary vector V[n], simply counting the number of samples Nb_samples between successive rising/falling transitions, which corresponds to the signal period: 2 3 transitionðm þ 2Þ count ðmÞ ¼ 4 N b samples 5 transition ðmÞ fbo ðmÞ ¼

fs m ¼ 1…2ðNper−1Þ count ðmÞ

ð4Þ

where Nper is the number of captured signal periods. With this process, 2(Nper−1) values of the instantaneous frequency are computed. In case of an ideal sinusoidal signal with no phase noise, the number of samples between successive rising/falling transitions should be constant and exactly equal to the oversampling ratio k, while in case of a sinusoidal signal affected with phase fluctuation, we expect to have some deviations from the ideal count: devðmÞ ¼ count ðmÞ−k

ð5Þ

In other words, we expect that phase noise present in the analog signal will result in a dispersion in the computed values of the estimated instantaneous frequency. We have identified that the Mean Absolute Deviation (MAD) of the estimated

instantaneous frequency is an estimator that permits a robust evaluation of the dispersion and that it can be related to the phase noise level σ present in the analog signal with: rffiffiffiffi   π ^f o σ ^¼ ⋅ MAD 2 rffiffiffiffi 2ðNper−1Þ   X  π 1  ⋅ ¼  ^f o ðmÞ− f o  ð6Þ 2 2ðNper−1Þ m¼1

rffiffiffiffi 2ðNper−1Þ X π fo ¼ ⋅ jdevðmÞj 2 2k ðNper−1Þ m¼1

where σ ^ is the estimated phase noise level and f o is the mean of the instantaneous frequency estimations which corresponds to the signal frequency fo. Moreover we have derived through a comprehensive simulation study an analytical expression that relates the phase noise level σ present in the time-domain signal to the phase noise level PN measured in the frequency domain by:    c  . ¼ maxðPN 1 ; PN 2 Þ PN ð7Þ dBc Hz  0 1 8 > > > B C > σ ^ > B C > . PN ¼ 20log 1 > 10 @ A > > > 1 2 < 0:81⋅ f o ⋅f offset 1 0 ð8Þ with > 2 > > > C B σ ^ > > C . > PN 2 ¼ 20log10 B > A @ > > 3 2 : 4:28 10−3 ⋅f o ⋅ f offset where foffset is the frequency offset at which phase noise measurement is performed. Based on these equations, we have defined the postprocessing algorithm that permits to perform phase noise estimation from the binary vector captured by a digital tester channel. The different steps of this algorithm are summarized in Fig. 4. 2.3 Limitation of the Digital Technique The previous technique has been validated in [12] on a practical case study, i.e., phase noise measurement on the IF output

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Fig. 3 1-bit acquisition of the signal under test. The transitions of the binary vector are used to estimate the instantaneous frequency

of a silicon tuner fabricated by NXP Semiconductors. This silicon tuner delivers a sinusoidal signal at about 1MHz with a phase noise level of −89.7dBc/Hz at a frequency offset of 25 kHz. Results show that correct estimation is achieved with an estimation error lower than 0.6 % and that the variability is not increased compared to the conventional measurement. The valid measuring range of the technique has also been explored by performing measurements on a synthesized signal affected with phase noise. The signal is generated through FMmodulation with white noise of a sinusoidal signal (see section 6 for the experimental setup), and phase noise level can be adjusted by means of the modulation depth fΔ. Both the conventional method and the proposed digital technique have been applied on this signal for different levels of injected noise. Results are summarized in Fig. 5 that reports the phase noise level estimated by the digital method with respect to the phase noise level measured by the conventional method, in case of a 3.04878MHz signal sampled at 125MHz (oversampling ratio k=41), with analysis of 30,487 signal periods and phase noise evaluation at a frequency offset offset=75kHz. A good correlation between the digital technique and the conventional method can be observed on a large range of phase noise values, from −40 to -85dBc/Hz. However for phase noise values below -85dBc/Hz, there is a kind of saturation of the digital technique that diverges from the conventional method.

phase noise level. For this, we have considered different sources of measurement inaccuracy and we have analyzed how these non-idealities affect instantaneous frequency reconstruction. Three main sources of measurement inaccuracy have been identified: & & &

Imperfect setting of the oversampling ratio k=fs/fo due to imprecise knowledge of the nominal signal frequency fo or imprecise control of the sampling frequency fs, Jitter in the sampling clock, Voltage noise coming either from the test equipment or from the circuit under test itself.

These sources of measurement inaccuracy have been modeled in the sampled analog signal. More precisely, imperfect setting of the oversampling ratio is modeled by considering an imprecision Δf (in Hz) in the nominal signal frequency. Jitter Δtj and voltage noise ΔV are modeled using random variables following a standard normal distribution: Δt j ðnÞ ¼ σR J ⋅x1 ðnÞ; with x1 ∼N ð0; 1Þ ΔV ðnÞ ¼ σRV N ⋅x2 ðnÞ; with x2 ∼N ð0; 1Þ

ð9Þ ð10Þ

The level of Random Jitter (RJ) and Random Voltage Noise (RVN) can be controlled by the value of the standard deviations σRJ (in seconds) and σRVN (in volts).

3 Identifying the Origin of Digital Technique Limitation 3.1 Unwanted Deviations Experiments have been conducted in order to understand the saturation of the digital technique observed in case of low

Fig. 4 Post-processing algorithm for phase noise estimation from digital capture

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Fig. 5 Comparison between PN estimation with digital technique and PN measurement with conventional method

The expression of the sampled analog signal s(nTs) that includes these three sources if measurement inaccuracy is then given by:     sðnT s Þ ¼ A⋅sin 2πð f o þ Δ f Þ nT s þ Δt j ðnÞ þ ϕ0 þ ΔϕðnÞ þ ΔV ðnÞ

ð11Þ Based on this model, simulations have been realized on at 3.04878 MHz sinusoidal signal sampled at 125 MHz (oversampling ratio k=41) without phase noise (Δϕ(n)=0,∀ n), which is an extreme case of low phase noise. Ideally the number of samples between successive rising/falling transitions should be constant and exactly equal to the oversampling ratio, which means that the deviation count should be equal to zero whatever the analyzed period of the signal: ∀m∈f1; …; 2ðNper−1Þg : devðmÞ ¼ 0

ð12Þ

First, we have analyzed the influence of imperfect setting of the oversampling ratio k=fs/(fo +Δf), without jitter and voltage noise (σRJ =0,σRVN =0). Results are illustrated in Fig. 6, for two different values of the imprecision in the nominal signal frequency Δf=6Hz and Δf=20Hz. It can be observed that there are indeed large regions where deviations remain at zero, however single unwanted deviations are generated at Fig. 6 Deviation of the estimated instantaneous frequency in case of a sinusoidal signal without phase noise (Hardware measurement). Regions with multiple unwanted deviations are observed at regular time intervals

regular time intervals. The smaller the frequency imprecision Δf is, the larger the time interval ΔTint between unwanted deviations. This time interval is actually related to frequency imprecision with: ΔT int ¼

1 2k⋅Δ f

ð13Þ

These simulation results have been confronted to hardware measurement results realized on a similar case study, i.e., analysis of a 3.04878MHz sinusoidal signal sampled at 125MHz without phase noise (signal directly delivered by an RF generator without frequency modulation). As illustrated in Fig. 7, hardware measurement results reveal that there are some regions where deviations remain at zero, but there are also some regions where deviations toggle between {−1, 0, +1}. Obviously, these unwanted deviations are interpreted by the algorithm as deviations induced by phase noise and cause overestimation of the phase noise level. They are, therefore, responsible of the digital technique saturation observed in case of low phase noise level. Analyzing more in detail these results, we can note that regions with unwanted deviations are located at regular time intervals, but contain a burst of deviations instead of a single

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Fig. 7 Deviation of the estimated instantaneous frequency in case of a sinusoidal signal without phase noise and imperfect setting of the oversampling ratio (Simulation). Single unwanted deviations are observed at regular time intervals

a

b

deviation as observed in the simulation experiment. Two main outcomes arise from these observations. First, because regions with unwanted deviations are located at regular time intervals, we can presume that there is an impairment between the signal frequency and the sampling frequency in the hardware experiment. Using equation (13) with ΔTint ≅1.2ms, this impairment corresponds to a frequency imprecision Δf≅10Hz in the model defined by equation (11). Second, because these regions contain multiple deviations, imperfect setting of the Fig. 8 Deviation of the estimated instantaneous frequency in case of a sinusoidal signal without phase noise, with imperfect setting of the oversampling ratio (Δf≅10Hz) and random jitter in the sampling clock (Simulation). Regions with multiple unwanted deviations are observed at regular time intervals

a

b

oversampling ratio is not the only source of measurement error but other sources are undoubtedly present in the hardware experiment. Further simulations have been carried out considering jitter and voltage noise in addition to imperfect setting of the oversampling ratio (simulations realized with Δf≅10Hz). Results are reported in Fig. 8 for two different values of injected random jitter σRJ =100ps and σRJ =500ps, and in Fig. 9 for two different values of injected random voltage noise σRVN =1mV

J Electron Test (2015) 31:443–459 Fig. 9 Deviation of the estimated instantaneous frequency in case of a sinusoidal signal without phase noise, with imperfect setting of the oversampling ratio (Δf≅10Hz) and random voltage noise (Simulation). Regions with multiple unwanted deviations are observed at regular time intervals

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a

(0.3% vvoltage noisse) b

(1% vvoltage noisee) and σRVN =3mV (on a sinewave of 300mV amplitude, which corresponds to 0.3 and 1 % voltage noise). In both cases, the behavior is similar to the one observed in the hardware experiments, i.e., regions with multiple unwanted deviations that occur at regular time intervals. The width of these regions depends on the level of injected random jitter or random voltage noise. For random jitter, the width observed in simulation with σRJ =100ps is smaller than the width observed in the hardware experiment, while it is larger with σRJ =500ps. A good correspondence between simulation and hardware measurement is actually obtained for σRJ ≅350ps. Similarly for random voltage noise, the width observed in simulation with σRVN =1mV is smaller than the width observed in the hardware experiment, while it is larger with σRVN =3mV. A good correspondence between simulation and hardware

measurement is actually obtained for σRVN ≅2.1mV, which corresponds to 0.7 % voltage noise. From these experiments, we can identify the origin of the limitation of the digital technique in case of low phase noise level, i.e., the presence of supplementary deviations resulting from imperfect setting of the oversampling ratio and either jitter in the sampling clock or voltage noise in the sampled signal. These supplementary deviations occur in distinct regions located at regular time intervals, and these regions actually correspond to regions where crossing events fall at the close vicinity of sampling points. Indeed as illustrated on the didactic example of Fig. 10, when the crossing event falls in the middle between two consecutive sampling, the signal voltage at the sampling points is far enough from the switching threshold so that the signal is

Fig. 10 A didactic example to illustrate the influence of jitter and voltage noise on the conversion of the analog signal: (a) crossing event in the middle between sampling points and, (b) crossing event close to the sampling point

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correctly converted into a logic B0^ or logic B1^. In contrast when the crossing event falls close to a sampling point, the signal voltage at the sampling point is close to the switching threshold and uncertainty in the sampling time or in the signal amplitude may result in an erroneous conversion of the signal. 3.2 Jitter or Voltage Noise Further investigations have been conducted in order to discriminate between jitter or voltage noise, and in particular we have investigated the sensitivity to jitter and voltage noise with respect to the signal frequency. Basically the technique relies on voltage-to-time conversion using level-crossings, i.e., the voltage information contained in the analog signal is converted into timing information in the binary signal. Voltage noise ΔV affecting the analog signal therefore produces timing noise ΔT in the binary signal. As stated in [10], in case of weak voltage noise ΔV≪A, we can use the derivative of the sine-wave signal at the zerocrossing point (dv/dt=A⋅2π)fo to establish the time/voltage relationship: ΔT ≅

ΔV A⋅2πf o

ð14Þ

This equation indicates that the timing noise introduced by voltage noise is linearly related on the level of voltage noise, but also depends on the signal frequency. In other words, it means that for the same value of voltage noise ΔV, a signal with low frequency produce a timing noise larger than a signal with high frequency, and therefore is more susceptible to generate unwanted deviations. On the other hand, it is clear that the timing noise induced by jitter does not depend on the signal characteristics but just on the value of the sampling clock jitter. We can therefore distinguish between the two types of noise by varying the signal frequency. In case of jitter, we expect that the number of unwanted deviations remains constant whatever the signal frequency while in case of amplitude noise, the number of unwanted deviations should increase for signal with a lower frequency. Experiments have been realized considering a sinusoidal signal without phase noise, both in simulation and hardware measurements. More specifically we have performed 1-bit signal acquisition with a fixed sampling rate fs=125MHz and we have computed the total number of deviations observed on 20,000 periods, for different values of the signal frequency from 1.29MHz up to 4.31MHz. Results are summarized in Fig. 11. As expected, the number of deviations is roughly constant for the simulation of the sinusoidal signal with jitter in the sampling clock, and decreases with the signal frequency for the simulation of the sinusoidal signal affected by voltage noise. Hardware measurement results exhibit

Fig. 11 Number of deviations w.r.t. signal frequency for 1-bit acquisition at 125MHz of a sinusoidal signal without phase noise

exactly the same behavior than simulation results with voltage noise, revealing the predominance of this type of noise in the experimental setup.

4 Improved Digital Technique In the previous section, we have established that the limitation of the proposed digital technique in case of low phase noise level comes from imperfect setting of the oversampling ratio and unwanted deviations of the instantaneous frequency generated by voltage noise in the analog signal. In this section, we present the development of a new post-processing algorithm that permits to alleviate this limitation. The main idea is to include an additional filtering step in order to discriminate deviations induced by voltage noise from deviations induced by phase noise. 4.1 Filtering Unwanted Deviations The objective is to develop a filter that permits to remove unwanted deviations generated by voltage noise while preserving the information related to phase noise. For this, we have analyzed the evolution over time of deviations generated by either voltage noise or phase noise. Simulations have been performed considering the phase noise model described in [8], which relies on a one-dimension Brownian motion. More precisely, phase fluctuations Δϕ(n) are defined based on the integration of a noisy frequency fn generated using a random variable with centered normal distribution: Xn   b⋅f n ðiÞ; with f ∼N 0; σ f n 2 ð15Þ ΔϕðnÞ ¼ 2πT s  i¼1 where σ f n (in Hertz) is the standard deviation of the noisy pffiffiffiffiffiffiffiffiffiffiffiffi frequency and b ¼ f s =f o is a normalizing factor that ensures independence of the noise level with respect to the sampling frequency.

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This model corresponds to 1/f2 phase noise characteristics, which is typical for complex RF devices where the measured phase noise corresponds to the accumulated contribution of the different elements present in the signal path. This model allows to control the phase noise level injected in the timedomain signal by adjusting the value of σ f n . A number of simulations have been performed on a 3.04878MHz sinusoidal signal sampled at 125MHz, considering a frequency imprecision Δf=10Hz and either voltage noise or phase noise. As an illustration, Fig. 12a reports an example of deviations observed in case of a simulated sinusoidal signal affected by 0.7 % voltage noise   σRV N =A ¼ 0:007; σR J ¼ 0; σ f n ¼ 0 and Fig. 12b reports an example of deviations observed in case of a simulated sinusoidal signal affected by 1.4 % phase noise (σfn/fo = 0.014,σRVN =0,σRJ =0). Results are displayed with a zoom on a small portion of the sequence to allow detailed analysis. A number of distinctive features can be highlighted for deviations generated by voltage noise: – – –

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to a voltage noise higher than 46mV (computed using equation 14), so more than 20 times the voltage noise level observed in the hardware experiments. Such a high voltage noise level cannot be considered as a non-ideality but corresponds to the case of a defective circuit or a problem in the test equipment. In contrast, deviations generated by phase noise do not exhibit any of the characteristic features observed for deviations generated by voltage noise: we can have deviations with amplitude higher than one, we can have a nonzero deviation immediately followed by another non-zero deviation, and we can have consecutive non-zero deviations of same sign. Our idea is to exploit this difference of behavior between deviations generated by phase noise and voltage noise. More precisely, the objective is to develop a filter that removes deviations exhibiting the characteristic features of deviations generated by voltage noise. Note that the first two distinctive

deviations only take +1, 0 or −1 values, a non-zero deviation is systematically followed by a zero deviation, consecutive non-zero deviations systematically exhibit opposite signs.

Note that these observations are valid for a large range of weak voltage noise. Indeed higher deviations, e.g., deviations with +2 or −2 values can occur only if the timing noise ΔT introduced by voltage noise ΔV exceeds the sampling period Ts, which corresponds to very high voltage noise level. For the practical case study considered in this paper, this corresponds

Fig. 12 Example of deviations observed in case of (a) a simulated sinusoidal signal affected by 0.7 % voltage noise, and (b) a simulated sinusoidal signal affected by 1.4 % phase noise

Fig. 13 Filter operation in case of (a) a simulated sinusoidal signal affected by 0.7 % voltage noise, and (b) a simulated sinusoidal signal affected by 1.4 % phase noise

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features are relatively simple to handle; however the third one is more complex because the interval that separates consecutive non-zero deviations is not constant but varies over time. Classical filters used in signal processing, usually Linear TimeInvariant (LTI) filters, are not able to handle this feature. We have therefore developed a custom-made time-varying filter. Practically, we have implemented a filter that removes consecutive non-zero deviations having differ-

ent signs and keep only non-zero deviations having the same sign or deviations with amplitude higher than one. f ðmÞ the deviations obtained after applicaWe denote dev tion of the filter. Note that since this filter is not a timeinvariant filter, conventional mathematical representation such as transfer function or impulse response cannot be used. For the sake of completeness, the Matlab code of the implemented filter is given below.

function [ F_Dev ] = filter( Dev ) % .......................................................... % FILTER: Time-Variant Filter % Input: Dev (Deviation Vector) % Output: F_Dev (Filtered Deviation Vector) % .......................................................... index_NZDev=find(Dev); NZDev=Dev(Dev~=0); D_NZDev=NaN(size(NZDev)); D_NZDev(2:end)=NZDev(1:end-1); index_KDev=find(D_NZDev==NZDev | abs(NZDev)>1); F_Dev=zeros(size(Dev)); F_Dev(index_NZDev(index_KDev))=Dev(index_NZDev(index_KDev)); end

The operation of the filter is illustrated Fig. 13 for the two cases of sinusoidal signal simulated in Fig. 12. Results are displayed on the complete sequence of 10,000 periods. The efficiency of the filter to remove unwanted deviations generated by voltage noise (cf. Fig. 13a) is clearly demonstrated: only 2 out of the 1085 deviations remains present after application of the filter, which corresponds to a filtering ratio of more than 99.8 %. In contrast regarding deviations induced by phase noise (cf. Fig. 13b), a significant number are still present after the filtering operation: 5302 out of the 9008 deviations are present after application of the filter, which corresponds to a filtering ratio of about 41 %. So even if some deviations generated by phase noise have been removed, we expect that preserved deviations still contain relevant information related to phase noise. This assumption can actually be verified by looking at the cumulative sum of deviations, which gives an image of the Brownian motion corresponding to the input signal phase

fluctuations. Figure 14 gives the evolution over time of this cumulative sum (zoom on a small portion of the sequence), in case of the simulated sinusoidal signal affected by phase noise, before and after application of the filter. We observe that both curves follow a similar trend, indicating that the proposed filter preserves the essential characteristics of phase noise. The difference between both curves can actually be quantified by computing the Normalized Root Mean Square Error (NRMSE) given by: vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ffi u X 2ðNper−1Þ  u f devðmÞ−devðmÞ t 1 m¼1 NRMSE ¼ ⋅ 2ðNper−1Þ devjmax −devjmin ð16Þ This error does not exceed 4 %, confirming that filtered deviations indeed contain meaningful information related to phase noise. However because some of the deviations induced by phase noise are removed by the filter, we cannot directly use the relationship defined in Eq.(6) between the phase noise level present in the analog signal and the cumulative sum of absolute deviations. We have to develop a new formulation that takes into account the impact of the filter on the number of deviations.

4.2 Correcting Filtered Deviations

Fig. 14 Evolution over time of the cumulative sum of deviations

Additional simulations have been carried out to evaluate the impact of the filter on the number of deviations induced by phase noise. Results are summarized in Fig. 15 which reports

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Note that the curve presented in Fig. 15 corresponds to a specific set of acquisition parameters {k, Nper}. In case of different values of these parameters, the shape of the curve remains the same but its location varies. A number of simulations have been performed varying these parameters in order to analyze their influence. Regarding the influence of the number of period Nper, simulations reveals that the sum of absolute deviations after application of the filter is directly proportional to this number, whatever the phase noise level. This influence can be included is the fitting models by considering equations of the form    β  f ∑dev ðmÞ ¼ Nper⋅α σ f =f . o

n

the sum of absolute deviations after application of the filter    f ∑dev ðmÞ with respect to the phase noise level σ f n =f o

Regarding the influence of the oversampling ratio k, simulations reveals that we should distinguish the cases of low and high phase noise levels: the sum of absolute deviations is directly proportional to the oversampling ratio in case of high phase noise level and proportional to the square of the oversampling ratio in case of low phase noise level. Consequently, the two fitting models corresponding to low and high phase noise levels should be derived based on:

injected in the analog signal (without any voltage noise). On this log-log graph, we can observe that the behavior slightly differs depending on the injected phase noise level:

 X  f ðmÞ ¼ k 2 ⋅Nper⋅α dev

Fig. 15 Sum of absolute deviations after application of the filter w.r.t. phase noise level injected in the analog signal (without voltage noise)

– –

in case of low phase noise level, the relationship between the sum of absolute deviations and the phase noise level can be approximated by a straight line with a slope of about 1.8, in case of high phase noise level, the relationship between the sum of absolute deviations and the phase noise level can be approximated by a straight line with a slope of about 1.3.

Consequently, the idea is to derive two fitting models corresponding to low and high phase noise levels, using mono   β  f mial equations of the form ∑dev ðmÞ ¼ α σ f n = f o .

a

 X  f ðmÞ ¼ k⋅Nper⋅α dev

LPN

HPN

σf n fo

σf n fo

βLPN

βH PN

ð18Þ

The last step is to determine the value of the fitting parameters αLPN,βLPN,αHPN andβHPN. This is accomplished through leastsquare regressions over the a number of different simulated scenarios (various values of σfn/fo, Nper and k). We obtain: αLPN ¼ 1:07; β LPN ¼ 1:80 αHPN ¼ 3:04; β HPN ¼ 1:28

b

Low PN levell

ð17Þ

High PN level

Fig. 16 Validation of the fitting models that relate the sum of absolute deviations observed after application of the filter to the phase noise level

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Figure 16 compares the sum of absolute deviations computed using the proposed models to the sum of absolute deviations observed in simulation, in case of a 3.04878MHz signal sampled at 125MHz with analysis of 30,487 signal periods. A very good agreement is observed for both models in their validity region. Finally based on these models, we can now establish novel expressions for the phase noise estimator that take into account the impact of the filter. In particular solving Eq.(17) and (18), we derive the following expressions that relates the phase noise level present in the analog signal to the cumulative sum of absolute filtered deviations :

σ ^fn

σ ^fn

.  11 βLPN  X  0 X   f f ðmÞ devðmÞ dev A < 0:004 ¼ f o ⋅@ f or k⋅Nper αLPN ⋅k 2 ⋅Nper .  11 βHPN  X  0 X   f f ðmÞ devðmÞ dev A < 0:004 ¼ f o ⋅@ f or k⋅Nper αHPN ⋅k 2 ⋅Nper

ð19Þ

ð20Þ

Note that we choose to set the switching between both    f models when ∑dev ðmÞ=k:Nper ¼ 0:004, which actually corresponds to a phase noise level σ ^ f n = f o of about 0.6 %. This novel estimator has been validated in simulation considering the case study of Fig. 5, i.e., a 3.04878MHz signal sampled at 125MHz with analysis of 30,487 signal periods. Simulations have been realized under the following conditions: & & &

imperfect setting of the oversampling ratio: Δf=10Hz, low random jitter: σRJ =10ps three different values of injected voltage noise: σRVN/0.4, 0.7 and 1 %

Fig. 17 PN estimation with digital technique vs. PN measurement with conventional method, for a simulated 3.04878 MHz signal sampled at 125MHz with imperfect setting of the oversampling ratio (Δf=10Hz), low random jitter (σRJ =10ps), and different values of injected voltage noise

Note that small random jitter has been included in the simulation to be representative of a realistic test environment. Results are summarized in Fig. 17 which reports the phase noise value estimated by the digital method (both the original technique and the new one) with respect to the phase noise value measured by the conventional method. These results clearly illustrate that the original technique is sensitive to voltage noise and that the saturation effect observed for low phase noise level depends on the level of injected voltage noise. The valid phase noise measurement range is therefore limited by the presence of voltage noise. In contrast for the new postprocessing algorithm, correct phase noise estimation is performed on the range from -40dBc down to -110dBc/Hz, whatever the value of injected voltage noise. These results therefore show the superior performance of the new postprocessing algorithm which does not suffer from the saturation effect observed with the original algorithm. An interesting point to mention is that, although the filter has been derived with respect to voltage noise since we have identified that it is the predominant type of noise in the experimental setup, it can also handle jitter in the sampling clock. To illustrate this point, simulations have been performed under the following conditions: & & &

imperfect setting of the oversampling ratio: Δf=10Hz, small voltage noise: σRVN/A=0.1% three different values of injected random jitter: σRJ =200, 350 and 500ps.

Results are summarized in Fig. 18 which reports the phase noise value estimated by the digital method (both the original technique and the new one) with respect to the phase noise value measured by the conventional method. Here again whatever the value of injected random jitter, the new postprocessing algorithm permits correct phase noise estimation from -40dBc/Hz down to -110dBc/Hz, whereas the valid

Simulation − original technique [ITC14] 0.4% voltage noise 0.7% voltage noise 1.0% voltage noise Simulation − new technique 0.4% voltage noise 0.7% voltage noise 1.0% voltage noise

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Fig. 18 PN estimation with digital technique vs. PN measurement with conventional method, for a simulated 3.04878 MHz signal sampled at 125MHz with imperfect setting of the oversampling ratio (Δf=10Hz), small voltage noise (σRVN/A= 0.1%), and different values of injected random jitter

measurement range of the original technique is limited by the level of random jitter. More generally, these results show that the new postprocessing algorithm offers improved robustness to nonidealities that may affect instantaneous frequency reconstruction. In particular, it is robust to imperfect setting of the oversampling ratio and presence of voltage noise or sampling clock jitter, therefore allowing the measurement of low phase noise levels. 4.3 Practical Implementation The improved digital technique relies on the same industrial setup than the original technique, i.e., 1-bit signal acquisition with a sampling frequency that is an integer multiple (preferably odd) of the signal frequency using a standard digital tester channel. Only the post-processing algorithm is modified. As illustrated in Fig. 19, an additional filtering step is inserted in order to remove unwanted deviations generated by voltage noise and the new estimator is used to correct the influence of the filter on the deviations induced by phase noise; all other steps remain the same.

5 Results 5.1 Experimental Setup To validate simulation results through measurements on actual analog signals, a laboratory test bench was developed. As illustrated in Fig. 20, an Agilent 33120A Arbitrary Waveform Generator (AWG) is used to generate a white noise signal. The output of this generator is connected to the FM input of an Agilent E4425B RF signal generator. The output of this generator is therefore a sinusoidal signal affected by phase fluctuations, whose phase noise level can be adjusted by means of

Simulation − original technique [ITC14] 200 ps random jitter 300 ps random jitter 500 ps random jitter Simulation − new technique 200 ps random jitter 350 ps random jitter 500 ps random jitter

the modulation depth fΔ. This signal corresponds to the Signal Under Test. For the purpose of the experiment, capture of the SUT is realized using a Yokogawa DLM2054 Mixed-Signal Oscilloscope (MSO). Note that in the context of an industrial production test, capture will be realized by an analog/RF tester channel for the conventional method, and a standard digital tester channel for the digital technique. Here, the MSO replaces the digitizer of the analog/RF tester channel, and 1-bit acquisition normally performed by the digital ATE is realized through software 1-bit quantization on the digitized samples captured by the MSO. Two distinct post-processing procedures are then implemented in Matlab®. The first one corresponds to the conventional method, i.e., FFT is applied on the digitized samples and the phase noise value PN is measured on the resulting spectrum. The second one corresponds to the digital technique, i.e., the dedicated post-processing algorithm is applied on the binary c. vector to compute the estimated phase noise value PN 5.2 Filter Validation The first experiment was to verify the correct operation of the filter in case of a sinusoidal signal without phase noise. For this we have considered the case same study than in Fig. 6, i.e., a 3.0487MHz signal delivered by the RF generator without frequency modulation and sampled at 125MHz by the mixed-signal oscilloscope. Results are illustrated in Fig. 21

Fig. 19 Novel post-processing algorithm for phase noise estimation from digital capture

wh hite no oise

AWG Agilent 33120A

Signal Generation

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FM-in

456

RF So ource Agilent E E4425B

Mixed-Signal Oscilloscope

Signal Capture

Yokogawa a DLM2054

1-b bit quantizzation

FFT (conventtional method)

0

1

0

Dedic cated Post-Proc cessing Algorithm (digital tecchnique)

(dBc/Hz)

Post Processing

1

(dB Bc/Hz)

Fig. 20 Experimental setup for hardware measurements

which gives the deviations observed before and after application of the filter. These results clearly demonstrate the efficiency of the filter to remove the unwanted deviations generated by voltage noise. Further experiments have been performed to verify the correct operation of the filter for different oversampling ratios. More specifically, we have analyzed signals with different frequencies while maintaining the same sampling frequency fs =125MHz (maximum value for this equipment). Results are summarized in Fig. 22 that reports the sum of absolute deviations after filtering according to the oversampling ratio. From the results of Fig. 22, it appears that there is actually a limitation on the value of the oversampling ratio ensuring

Fig. 21 Filter operation for a 3.0487MHz signal without phase noise delivered by the RF generator without frequency modulation, and acquisition with an oversampling ratio k=41

correct operation of the filter. Indeed the sum of absolute deviations remains very low in case of an oversampling ratio below 45, revealing efficient filtering of unwanted deviations. However, it drastically increases with the oversampling ratio for values above 45, indicating that the filter is not functional in such situations. As an illustration, Fig. 23 shows the operation of the filter in case of a 2.77MHz signal sampled at 125MHz, which corresponds to an oversampling ratio k=45. In this case, we can observe that regions with unwanted deviations overlap in time at some portions of the sequence and that deviations are not correctly filtered in these overlapping regions. The explanation of these overlapping regions resides in the combination of two phenomena related to the sampling process and voltageto-time conversion. Indeed the sampling process relies on a sampling frequency which is an integer multiple of the signal frequency and we’ve seen that the time interval between regions with unwanted deviations depends on the impairment between the signal frequency and the sampling frequency (cf. Eq. (13)). On the other hand during voltage-to-time conversion, the timing noise introduced by voltage noise depends on the voltage noise level but also on the signal frequency: the lower the signal frequency, the larger the timing noise (cf. Eq. (14)). So for the same voltage noise level, the lower the signal frequency is, the larger the regions with unwanted deviations. If the width of these regions becomes larger than the time interval due to frequency impairment, there is then an overlap. This is what happens in this experiment, where the signal frequency has been reduced to increase the oversampling ratio. In the overlapping regions, the distinctive features identified in case of deviations induced by voltage noise are not preserved, resulting in a filter malfunction in these regions. A necessary condition for the correct operation of the filter is therefore that there is no overlap between regions with unwanted deviations generated by voltage noise, which impose a limitation on the value of the oversampling ratio. This

Fig. 22 Sum of absolute deviation after filtering vs. oversampling ratio

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Fig. 23 Filter operation for a 2.77MHz signal without phase noise delivered by the RF generator without frequency modulation, and acquisition with an oversampling ratio k=45

limitation does not prevent from using the technique; it has only an impact on the measurement variability. Indeed as demonstrated in [7], measurement variability reduces when increasing the oversampling ratio and/or the number of captured periods. The consequence of a limited oversampling ratio can therefore be compensated by increasing the number of captured periods, if necessary. Note that the maximum value of the oversampling ratio ensuring correct operation of the filter should be evaluated for each case study since it depends not only on the signal characteristics (voltage noise amplitude, signal frequency) but also on the performance of the test equipment (frequency inaccuracy). 5.3 PN Hardware Measurements Hardware measurements were performed on a sinusoidal signal affected with phase fluctuations considering the same case study than in Fig. 5, i.e., a 3.0487MHz signal sampled at 125 MHz. Different levels of phase noise were injected varying the modulation depth fΔ of the RF source from 1kHz up to 1MHz. For each level of injected phase noise, 30,487 signal periods were acquired by the MSO and treated by the conventional method as well as the digital technique (after 1-bit quantization). Note that the same number of periods is used for both techniques, which therefore have the same test time. The acquisition of 30,487 signal periods is actually the typical setup for the conventional measurement, which corresponds to a test time of 10 ms. Results are summarized in Fig. 24 which reports the phase noise value estimated by the digital method (both the original technique and the new one), with respect to the phase noise value measured by the conventional method. For the sake of comparison, simulation results are also reported (Δf=10Hz, σRJ =10ps,σRVN/A=0.7%).

457

Fig. 24 Hardware validation: comparison between PN estimation with digital technique and PN measurement with conventional method for a 3.0487MHz signal sampled at 125MHz

The first comment on this graph is that there is a good agreement between simulation and hardware measurements, indicating that appropriate effects have been included in the model. This agreement also validates the new expression of the phase noise estimator that takes into account the impact of the filter, which has been established in simulation environment only. Finally, these results confirm the superior performance of the new digital technique that permits to remove the saturation effect observed with the original one. As a consequence, the valid measurement range is significantly extended: for this case study, the new algorithm permits to achieve accurate phase noise estimation down to -110dBc/Hz whereas the original one was limited to -85dBc/Hz. The efficiency of the technique can also be quantified by computing the RMS error between estimation and measurement over the full range of [−110dBc/Hz, −40dBc/Hz]: this error reduces from 11.8dBc/Hz using the original technique down to 1.6dBc/Hz with the new one.

6 Discussion and Conclusion This paper has presented a new post-processing algorithm that permits to perform phase noise estimation of sinusoidal analog/IF signals from 1-bit digital capture. The technique has the same foundation than a previous solution based on phase noise estimation using mean absolute deviation of estimated instantaneous frequency. However this solution has a limited measurement range and diverges from the conventional method in case of very low phase noise level. An analysis has been conducted to identify the origin of this limitation, which is related to unwanted deviations generated by the combination of imperfect setting of the oversampling ratio and presence of voltage noise. A novel post-processing algorithm has been developed in this paper to overcome this limitation. In particular, an additional filtering step has been introduced in order to

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discriminate deviations induced by voltage noise from deviations induced by phase noise and a new phase noise estimator has been defined to compensate the effect of the filter on the deviations induced by phase noise. The novel processing algorithm exhibits improved robustness with respect to nonidealities that may be present in the test equipment. It has been validated through hardware measurements on a 3MHz sinusoidal signal and results have demonstrated that it offers a significant improvement in terms of valid measurement range. More generally, the main benefit of the technique resides in the dramatic reduction in the required test equipment since it can be implemented on a standard digital ATE and therefore permits to get rid of the expensive analog/RF tester resources required for the conventional method. Moreover because digital channels are usually available in a large number on a standard ATE, it also offers the possibility to implement multi-site testing in order to further reduce the testing costs. However it should be mentioned that since the proposed solution relies on an oversampled acquisition, it is not directed towards the analysis of signals with very high frequency above the gigahertz but targets products with an output in the intermediate frequency range. Such products are used in a number of application domains including communication and multimedia, transportation, home automation, healthcare. The technique permits the direct analysis of signals up to several tens of megahertz using a single standard digital tester channel; it can be easily extended to signals up to several hundreds of megahertz by multiplexing digital tester channels. To illustrate cost savings that can be achieved with the technique, let us consider typical capabilities of a presentday ATE, for instance Advantest 93K:

Acknowledgments This work has been carried out under the framework of ENIAC JU project BELESIS: European Library-based flow of Embedded Silicon test Instruments^.

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Standard digital card (PS1600): 128 channels, up to 1.6 Gbps, High-speed digital card (PS9G): 64 channels, up to 9 Gbps, Mixed-signal card (MBAV8): 4 channels for signal generation, 4 channels for signal acquisition, up to 180 Msps, 300 MHz analog bandwidth.

Phase noise test with the conventional method necessitates the use of the mixed-signal card; it allow parallel testing of 4 devices with operating frequency up to 300 MHz. Phase noise test with the proposed technique can be implemented using only digital resources; the use of a standard digital card allows parallel testing of 32 devices with operating frequency up to 200 MHz (4 multiplexed channels per device, oversampling ratio k≅30), and the use of a high-speed digital card allows parallel testing of 32 devices with operating frequency up to 500 MHz (2 multiplexed channels per device, oversampling ratio k≅30). The proposed technique therefore yields substantial test cost savings with a reduction of at least one order of magnitude.

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Stephane David-Grignot received a double-degree in engineering from Centrale Nantes and ETSII Valencia in 2011 as well as a research master in nanotechnologies from Centrale Paris in 2012. He is currently a PhD student in the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) working on cost reduction for phase noise measurement on RF devices for NXP Semiconductors’ account, leading to one patent and several publications in international conferences. He has participated in a stop and start project for the car industry before, as well as designed an adaptive filter for a PLL on a three phase power inverter for solar panels. He has also implemented and performed 3-omega measurement campaigns on silicon nano-wires. Florence Azaïs received the Ph.D. degree in electrical engineering from the University of Montpellier, France in 1996. She is currently working in the Microelectronics department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) as a researcher of the National Council of Scientific Research (CNRS). Since 1993, she

459 has been interested in the general domain of test and reliability of integrated circuits and systems. Her main research interests include fault modeling, analog, mixed-signal and RF circuit testing, MEMS testing, reliability of integrated systems. She has contributed to 4 patents, authored or co-authored over 100 international papers, and contributed to the redaction of 3 books on these topics. She is chair of the IMSTW Steering Committee and she also serves as a member of the Program Committee of several international conferences (ETS, DATE, IMSTW, LATS). Laurent Latorre received a Ph.D. in Microelectronics from University Montpellier II in 1999. He holds a mechanical and electronics engineer degree. He spent a post-doc period at UCLA (CA, USA) where he worked on the design of liquid metal micro-relays (1999–2000). He is currently a professor at Polytechnic Engineering School of Montpellier. His research interests concern the design and test of CMOS microsystems and RF circuits. He is in charge of the Test Resource Center of CNFM, a national service that promotes education on industrial testing and supports research by making available state-of-the-art automated test equipment. François Lefevre joined NXP Semiconductors in 1998 after working for several companies including a TV tuner production site in Asia and a firm developing RF equipments for military communication purpose. Within NXP as a test engineer he used leading edge innovation to reduce the cost of production test for both new and current products. Original methods are also introduced to decrease project execution time. Then by leading the Design for Test definition of large RF, mixed-signal and digital ICs, he further contributed to provide an optimized industrial strategy. Also by driving new industrial equipment configurations and standards, he closed the loop from the product test strategy to the mass production. He is representing the Business Unit in an NXP Tester User Group. Several ideas were registered as patents by NXP.