Trans. Tianjin Univ. 2013, 19: 140-146 DOI 10.1007/s12209-013-1997-5

In-Pixel Charge Addition Scheme Applied in Time-Delay Integration CMOS Image Sensors* Xu Chao(徐

超)，Yao Suying(姚素英)，Xu Jiangtao(徐江涛)，Li Lingxia(李玲霞)

(School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China) © Tianjin University and Springer-Verlag Berlin Heidelberg 2013

Abstract：An addition scheme applicable to time-delay integration (TDI) CMOS image sensor is proposed, which adds signals in the charge domain in the pixel array. A two-shared pixel structure adopting two-stage charge transfer is introduced, together with the rolling shutter with an undersampling readout timing. Compared with the conventional TDI addition methods, the proposed scheme can reduce the addition operations by half in the pixel array, which decreases the power consumption of addition circuits outside the pixel array. The timing arrangement and pixel structure are analyzed in detail. The simulation results show that the proposed pixel structure can achieve the charge addition with negligible nonlinearity, therefore the power consumption of the periphery addition circuits can be reduced by half theoretically. Keywords：CMOS image sensor; time-delay integration; charge domain; two-stage charge transfer

Time-delay integration (TDI) image sensors are used in applications where a line-scan system is required for high quality, low noise and high contrast imaging even under low illumination conditions. The TDI cameras have been implemented for years with chargecoupled device (CCD) sensors where the TDI functionality is almost intrinsically available [1-3]. Although it is not easy to implement TDI in CMOS image sensors (CISs), they possess their inherent research value for the advantages of process accessibility, reduced cost, robustness to ionizing radiation, etc[4-6]. A number of reports on CMOS TDI image sensors have been published. In Ref.[7], several exposure methods which can realize the synchronous signal capturing of the image for CMOS TDI image sensors were presented, and a digital accumulation method was also presented. According to the exposure methods proposed in Ref.[7], a 25-stage CMOS TDI image sensor with analog accumulator was presented in Ref.[8]. In Ref.[9], a digital TDI line-scan image sensor was developed, but the TDI operation was realized by an off-chip field-programmable gate array (FPGA) rather than being integrated with the sensor on the chip. In Ref.[10], the noise of current accumulator in TDI CMOS image sensor was analyzed. A TDI CMOS image sensor with pipelined charge transfer

architecture was proposed in Ref.[11]. Basically, it is a current integration device, and no pinned structure is adopted in the pixel, so the structure would suffer the problem of high dark current. In a TDI CIS, on-chip addition operation is a required process, which can be implemented in the analog or digital domains. In either domain, a matrix of adders is needed to perform the storage and addition of readout signals. For the addition process in the analog domain, in each one of the adders, the operational amplifier (OPA) is a necessary component to perform the voltage accumulation, and all the OPAs’ power consumption generally accounts for a large part of that over the whole TDI CIS chip. In the case of addition in the digital domain, the analog-to-digital-converters (ADCs) are needed in each column, which can cause a considerable power consumption of the chip. To reduce the power consumption induced by addition operations, this paper introduces a hybrid addition scheme by accumulating the signals in the charge domain. By introducing an additional pinned diode used for charge storage into every pair of pixels in each column, the proposed structure can reduce the addition operations by half inside the pixel arrays. In this way, the setting time of OPA or the conversion time of ADC can be pro-

Accepted date: 2012-10-10. *Supported by National Natural Science Foundation of China (No.61036004 and No. 61076024) and Ph.D. Programs Foundation of Ministry of Education of China (No. 20100032110031). Xu Chao, born in 1983, male, doctorate student. Correspondence to Yao Suying, E-mail: [email protected].

Xu Chao et al: In-Pixel Charge Addition Scheme Applied in Time-Delay Integration CMOS Image Sensors

ing the process of readout and addition is also illustrated. In Fig.1, the sensor consists of 6 rows of pixels, i.e., the number of TDI stages is 6. For simplicity, only one column of pixels is shown. The sensor is placed at different locations at different time, which implies the relative movement of the sensor. For the sake of synchronous signal addition, the rolling shutter mode with temporal oversamping(7 adders are needed) is adopted[12]. In Fig. 2, 1 Proposed addition scheme and pixel only part of the addition process is demonstrated, and the previous state of adders is indicated in a compact form. As structure the same scene element is successively acquired by pixels 1—6, the intermediate result is stored in the same adder. 1.1 Proposed addition scheme As mentioned above, the matrix of adders in a TDI As the 6th sample has been added, the corresponding adder CIS is shown in Fig.1, where the timing principle includ- is read out, which is shown by a diamond mark.

longed to be twice its original level, which apparently can reduce the power consumption of the chip. This paper is organized as follows: in Section 1, the proposed addition scheme and pixel structure are described; Section 2 presents the simulations and results related to the proposed pixel structure; conclusions are presented in Section 3.

Fig.1

Timing with rolling shutter and states of adders

If the TDI addition is completed in the analog domain, the OPAs are the necessary components to perform the voltage accumulation. For an OPA, The setting time ts can be written as (1) 1 1 ts  ln   2π  GBW    where GBW is the gain-bandwidth product; and ε is the precision. Note that the setting time has to be shorter than the time interval between two consecutive addition operations. When the time interval is doubled, the OPA’s setting time can be prolonged to be nearly twice its original level and the GBW can be reduced by half, which can

reduce the power consumption of OPA by half correspondingly. Similarly, in the case of addition in the digital domain, when the time interval mentioned above becomes longer, the conversion time of ADC can be designed as a lower value, which undoubtedly can reduce the power consumption of ADC. However, the time interval or the TDI addition frequency cannot be changed arbitrarily for maintaining a high line frequency and achieving the synchronous addition of signals. This paper introduces a method to decrease the chip’s power consumption by means of reducing the number of addition operations in the adder arrays by half,

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(a) Addition in the charge domain

(b) Oversampling shutter mode

(c) Undersampling shutter mode

Fig.2 Schematic diagrams of addition in the charge domain with different sampling modes

either in the analog or digital domain. Combined with the conventional addition methods, the proposed technique accumulates the signals in the charge domain. As shown in Fig.1, the scene element F is captured successively by pixels No.1 and No.2. If the photoelectrons generated in pixel No.1 can be transferred to a storage node rather than being converted to a voltage signal and read out, they can be added with the photoelectrons generated in pixel No.2 after a period of time, as long as

Fig.3

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the two packages of electrons correspond to the same scene element. Thus, only one addition operation is needed in the adder outside the pixel arrays. Fig.2(a) shows the process mentioned above. For the oversampling mode shown in Fig.1, the readout of pixel No.1 is performed ahead of that of pixel No.2 during a rolling shutter cycle, and the mentioned storage node has to be added into a new package of charge corresponding to a different scene element, which can cause errors in the addition, as shown in Fig.2(b). An undersampling shutter mode is adopted to cope with the additional storage node, where the readout of pixel No.2 is completed prior to that of pixel No.1, as shown in Fig.2(c). The proposed addition method applied to TDI CMOS image sensor is shown in Fig.3. As previously described, the rolling shutter mode with temporal undersamping (5 adders are needed) is adopted. The addition in the charge domain is not illustrated in detail, and the mark beside the pixel indicates the stored charge corresponding to the scene element. The readout is performed in a descending order of the pixels’ numbers during the rolling shutter cycle. Only half of the output signals are needed to be transmitted through the column bus and added in adder arrays, and each of the added signals originates from two packages of charge generated in two adjacent pixels respectively, and the two parts of charge are added and converted to a voltage signal, typically in a floating diffusion (FD) node.

Operating principle of the proposed addition scheme

Xu Chao et al: In-Pixel Charge Addition Scheme Applied in Time-Delay Integration CMOS Image Sensors

1.2

Proposed pixel structure To realize the proposed addition scheme, a corresponding pixel structure is proposed, as shown in Fig.4(a). The sensor consists of 6 rows of pixels, and only one column of pixels is shown. Compared with the typical four-transistor (4T) pixel structure, the proposed one adopts a two-shared pixel. The sharing components are the source follower (MSF), the row select transistor (MSEL), the FD node and the reset transistor of FD (MRFD). Each pixel holds its own photodiode (PD) and transfer transistor (MTX). The storage diode (SD) is used for charge storage, and low dark current can be achieved in SD thanks to the adopted pinned structure [13]. To eliminate the effects of residue charges in PD or SD after the charge transfer processes, the corresponding reset transistors (i.e., MRPD and MRSD) are adopted, as shown in Fig.4(a). To distinguish the elements in different pixels, we mark them with the pixel numbers. Just as in the previous section, the charge from SD1 and PD2 is added into FD1-2, where the charge-to-voltage conversion is performed simultaneously. Using this structure, the reset noise at FD can be canceled by the true correlated double sampling (CDS) operation. Fig.4(b) shows the available layout of the proposed pixel structure. For simplicity, the transistors MSF and MSEL are not shown in the layout. Fig.5 shows the schematic diagram of cross section at line A-A′. In the two-stage charge transfer structure, to enable a perfect charge transfer from PD to SD, a potential difference is necessary. As described in Refs.[14] and [15], two different doping layers, i.e., n1 and n2, are used in the proposed pixel design, where n1 is smaller than n2. The former and the latter correspond to the n-type doping concentration of PD and SD respectively. The n-type layer n_vt is used to adjust the threshold voltage of MRFD for a higher electrostatic potential of FD. The pinned layer of PD or SD is marked with p_pinned. The p-type well marked with p_well is adopted to decrease the crosstalk between every two adjacent pixels as well as to

prevent the photoelectrons from diffusing into the SD. Note that only the PD regions (i.e., PD1 and PD2) are supposed to be sensitive to illumination, so the other parts of the chip are shielded with opaque metal layers, which are not shown in Fig.5. The timing diagram applied to the proposed pixel is shown in Fig.6. The controlling signals are connected to the gates of the corresponding transistors (i.e., VTX1 is connected to the gate of MTX1). To clarify the operation scheme, the paths for charge transfer are labelled beside the controlling signals, which are related to the process shown in Fig.3.

(a) Proposed pixel structure

(b) Layout

Fig.4 Schematic diagrams of the proposed pixel structure and layout

Fig.5 Schematic diagram of cross section at line A-A′

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Fig.6

2

Timing diagram for the proposed pixels

Simulations

We verify the function of the proposed pixel structure with Technology Computer-Aided Design (TCAD) tools. The length of PD1 or PD2 is 2 µm, and the width is 1 µm, which is the default value for two-dimensional (2D) simulation. The VDD is set to be 3.3 V in the design. Fig.7 shows the simulation result of the electrostatic potential distribution just after FD node is reset, when all the transistors are turned off. By cutting along path B-B′, we can obtain the curve of electrostatic potential, as shown in Fig.8. Path B-B′ is chosen because it is composed of points with the highest electrostatic potential in

the horizontal direction, where electrons are prone to stay in or to pass through. Fig.8 shows the electrostatic potential distribution along path B-B′. The result indicates that the potential difference between PD1 and SD, as well as the difference between SD and FD, is formed. The higher potential under the gate of RFD results from the threshold-adjust doping, which has no effect on the well capacity of PD or that of SD.

Fig.8

Fig.7 Simulated electrostatic potential distribution at line A-A′

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Electrostatic potential distribution along path B-B ′

To evaluate the performance of charge transfer and storage in the two-stage structure, we monitor the number of electrons residing in PD1 and SD1 throughout the

Xu Chao et al: In-Pixel Charge Addition Scheme Applied in Time-Delay Integration CMOS Image Sensors

working process of the device. In Fig.9, two rectangles are shown to define the areas where the number of electrons is calculated. The simulation is confined in a 2D mode, so the results indicating the number of electrons are in the form of line density. Given the length in the direction perpendicular to the cross section, we can calculate the total number of electrons by multiplication. The illumination and metal shield are also shown in Fig.9, where the names and connection relation of transistors are identical with those in Fig.7.

Fig.9

Schematic diagram of simulation with illumination

Fig.10 shows the test timing diagram. In the simulation, we choose 10 lux of illumination, and the exposure time is set to be 400 µs. For simplicity, the reset operations for PD1 and SD1 are not shown.

Fig.10

Test timing diagram

The simulation result is shown in Fig.11. The line density of electron in PD1 increases linearly with time until TX1 is turned on, when the photoelectrons accumulated in PD1 begin to be transferred to SD1. The line

Fig.11

Line density of electron in PD1 and SD1

density of electron in SD1 keeps at a fixed level until TG1 is turned on, when the electrons residing in SD1 begin to be transferred to FD. It can be concluded that the potential barrier between PD1 and SD1 has effectively prevented the photoelectrons in PD1 from diffusing into SD1 when TX1 is turned off. To verify the addition function in pixel, two kinds of operation modes are simulated, i.e., one-PD mode and two-PD mode. In the one-PD mode, only PD2 is illuminated. The photoelectrons accumulated in PD2 are transferred into FD1-2 and result in its voltage change. In the two-PD mode, both PD1 and PD2 are illuminated, and the two parts of electrons are finally added to FD1-2. Note that the electrons in PD1 experience a two-stage transfer when they reach FD1-2. In other words, the onePD mode is of traditional charge-voltage conversion method, and the two-PD mode is implemented with charge addition. Theoretically, the signal value (i.e., voltage change of FD1-2 before and after the charge is transferred into FD1-2) for the two-PD mode (i.e., V2PD) is twice of that for the one-PD mode (i.e., V1PD). In the simulation, the voltage of FD1-2 is obtained by detecting the voltage of contact electrode overlaid on PD1-2. The exposure time for the two modes is 400 μs, and the illuminations are set to be 0 lux, 1 lux, 10 lux and 100 lux. The simulation results are listed in Tab.1. It can be found that the double value of V1PD is nearly the same as V2PD, which indicates the feasibility of addition in the charge domain. Due to the short time of exposure, the signals cannot reach a big value. However, with the help of TDI addition, the signals can be raised to higher values. It can also be concluded that the signals caused by dark current arrive at nearly 5% of that when illuminations are set to be 1 lux. The level of dark current is acceptable in low illumination imaging, and the signals can be calibrated by the technique of dark background subtraction. Although the differences between V2PD and double value of V1PD increase with the exposure, they are maintained at a low level. As the TDI image sensors are often used under low illumination, the exposure cannot reach a large value, and the differences remain at a low level.

Tab.1 Signal value at different exposures Illumination/lux

Exposure/(lux·s)

V1PD/V

V2PD /V

2V1PD /V

0

0.00

0.000 011

0.000 022

0.000 022

2V1PD-V2PD/V 0

1

0.000 4

0.000 231

0.000 460

0.000 462

0.000 002

10

0.004

0.002 268

0.004 520

0.004 536

0.000 016

100

0.04

0.022 702

0.045 330

0.045 404

0.000 074

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3

Conclusions

［7］ Lepage G, Bogaerts J, Meynants G. Time-delay-integration architectures in CMOS image sensors [J]. IEEE Transac-

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