Analog Integrated Circuits and Signal Processing, 13, 261–274 (1997)

c 1997 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands. °

Low-Voltage CMOS Rail-to-Rail V-I Converters∗ CHUNG-CHIH HUNG,1,2 CHANGKU HWANG,3 MOHAMMED ISMAIL,1,2 KARI HALONEN,1 AND VEIKKO PORRA1 [email protected] 1 Electronic Circuit Design Laboratory, Department of Electrical Engineering, Helsinki University of Technology, Otakaari 5A, FIN-02150, Espoo, Finland; 2 On leave from Analog VLSI Laboratory, Department of Electrical Engineering, The Ohio State University, 2015 Neil Avenue, Columbus, Ohio 43210-1272, U.S.A.; 3 Formerly with Analog VLSI Laboratory, The Ohio State University and currently with Micrys, Inc. (formerly ChipWorks, Inc.),

1275 Kinnear Rd., Columbus, Ohio 43212

Received July 15, 1996; Accepted August 29, 1996

Abstract. This paper presents two CMOS low-voltage rail-to-rail voltage-to-current converters (V-I converter) which could be used as basic building blocks to construct low-voltage current-mode analog VLSI circuits. In each of the circuits, an N-type V-I converter cell is connected in parallel with its P-type counterpart to achieve commonmode rail-to-rail operation. A linear differential relationship of the N-type V-I converter, or its P-type complement, is obtained using a new class-AB linearization technique. In the first rail-to-rail V-I converter circuit, a constant transconductance is achieved through the use of two maximum-current selecting circuits and an output subtraction stage. In the second circuit, a constant transconductance value is obtained by manipulating the DC bias currents of N- and P-type V-I converter cells. Both of the circuits can operate from rail to rail with a power supply of 3V, or less depending on the VLSI technology and the DC bias current level. Key Words: low voltage, rail-to-rail, voltage-to-current converter, V-I converter, OTA 1.

Introduction

As VLSI technologies advance and the demand for portable and mobile electronic equipment is increasing, circuit design techniques for low power supply voltage will continue to receive greater attention. Modern analog and mixed-signal VLSI applications in areas such as mobile telecommunications, smart sensors, battery-operated consumer electronics and artificial neural computation require CMOS analog design solutions. With the reduction of power supply voltage, many of the existing CMOS analog building blocks, designed to operate from higher supply voltages, will lose a significant amount of operating range and need to be reconsidered and redesigned. Achievement of a rail-to-rail operating range is a key issue for lowvoltage circuits in order to maintain acceptable levels of signal-to-noise ratio. In this paper, we introduce two low-voltage railto-rail voltage-to-current converters which can also perform the square-root function. Both of them are achieved by different approaches, however, with the same V-I converter core circuit. Numerous analog ∗ This

work is supported in part by a Fulbright-Hays grant, by the Nokia Foundation, and by the Academy of Finland.

computational circuits can be constructed using these V-I converters. This paper is organized as follows. First, a low-voltage differentially-linear N-type V-I converter cell is presented. Because the common mode input range of a single N-type V-I converter is limited, in order to obtain a rail-to-rail common mode input range, another complementary P-type V-I converter is used to be driven in parallel with the N-type V-I converter. Next, two different methods to achieve a constant transconductance, gm , are explained. In the first approach, a constant transconductance is achieved by manipulating the total instantaneous output currents through the use of two maximum-current selecting circuits and an output subtraction stage. In the second method, a constant transconductance value is obtained by manipulating the DC bias currents of the N- and Ptype V-I converter cells. Performance results of these two circuits will be shown in Section IV. Finally, conclusions are given for this paper. 2.

A Linear N-Type V-I Converter Cell

An N-type low-voltage CMOS V-I converter is shown in Fig. 1 [1] [2], where Vin+ = VC + vin /2 and Vin− = VC − vin /2. Assume MOS transistors M1 , M2 , and

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vin 2 vin 2

(4) (5)

Note that this results in the sum of Vgs1 + Vgs2 being a constant. This property is referred to as “class-AB” linearization technique [3]. The output current of the V-I converter is then obtained as the difference of the two currents, I1 and I2 . That is KN ³ vin ´2 Vdc + I1 = (6) 2 2 KN ³ vin ´2 I2 = (7) Vdc − 2 2 p I1 − I2 = K N Vdc vin = K N 2IC /K N vin p = 2K N IC vin = gm N vin

Fig. 1. A circuit diagram of an N-type V-I converter cell.

M3 are matched, K 1 = K 2 = K 3 = K and VT 1 = VT 2 = VT 3 = VT , the simple square-law drain current expression, Id = K N (Vgs − VT N )2 /2 for an NMOS transistor is used (K N = (µe f f Cox W/L) N , where µe f f is the effective electron mobility, Cox is the gate-oxide capacitance per unit area, W is the channel width and L is the channel length). Refer to this circuit with vin as an input, and assume that IC is a fixed reference current. Due to the current mirror M4 and M5 , the drain current of M3 is equal to the constant current, IC . As the input vin changes, the source terminals of transistors M1 , M2 , and M3 follow accordingly. The current through M3 is constant. Any change in the voltage at the source terminals is amplified by the common-gate transistor M3 , and the result is fed back by M6 , M8 , and the common-source amplifier M7 to stabilize the current through M7 . Hence, the drain voltage of M7 is kept constant. Therefore, in the saturation region, Vgs3 − VT of M3 will be a constant, say Vdc . Because M1 , M2 , and M3 are tied at their sources, we have vin = Vgs1 − Vgs3 = Vgs3 − Vgs2 2 vin = (Vgs1 − VT ) − (Vgs3 − VT ) 2 = (Vgs3 − VT ) − (Vgs2 − VT )

(1) (2) (3)

(8) (9)

where gm N is a constant. Thus, a linear V-I converter is obtained. Because the common-mode input range of a single N-type V-I converter is limited, and in order to have a rail-to rail common-mode input range, a complementary P-type V-I converter is connected in parallel with the N-type V-I converter to form a complete V-I converter. 3.

Low-Voltage Rail-To-Rail V-I Converters

For a rail-to-rail V-I converter, the total transconductance always has to be constant from rail to rail, i.e., independent of the common-mode input voltage. A constant gm will keep harmonic distortion at very low levels [4]. For the proposed single N-type cell and its counterpart, a P-type converter cell, themselves, the V-I relations are given by p (10) In1 − In2 = 2K N IC vin = gm N vin p (11) I p2 − I p1 = 2K P IC vin = gm P vin where (In1 , In2 ) and (I p1 , I p2 ) are the output currents in the N-type and P-type cells respectively, and gm N , gm P are the transconductances of the N-type and Ptype cells respectively. The V-I relations are only linear when the input transistors are operating in the saturation regions. Their operating range is thus limited. In this section, we will present two approaches to achieve a constant-gm rail-to-rail V-I converter.

Low-Voltage CMOS

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in a series connection of a current source and a current sink, the minimum current always dominates [6]. Thus, because of I1 ≤ I2 , the drain current of Mn5 becomes I1 , but the drain current of Mn6 is still I2 . There is no current flow in Mn8 in this situation. Mn7 and Mn8 are turned off. Therefore, the output current will be Iout = I Mn6 = I2 = M AX (I1 , I2 )

(13)

From I and II, we can see that Iout = M AX (I1 , I2 )

Fig. 2. A circuit diagram of a maximum-current selecting circuit.

3.1.

Approach I

In this approach, the constant transconductance is achieved through the use of two maximum-current selecting circuits and an output subtraction stage. A maximum-current selecting circuit is shown in Fig. 2 [5]. The output current, Iout , will always take the maximum value of I1 and I2 . Its operational principles are explained as follows. I. I1 > I2 Because of the current mirrors of Mp1, Mp2 and Mn4, Mn5, Mn6, the drain current of Mp2 is I1 and the drain currents of Mn5, Mn6 are I2 . Thus, the current flowing through Mn8 is (I1 − I2 ), and so is the current in Mn7. Therefore, the output current is given by Iout = I2 + (I1 − I2 ) = I1 = M AX (I1 , I2 )

(12)

II. I1 ≤ I2 Again, because of the current mirrors of Mp1, Mp2 and Mn4, Mn5, Mn6, the drain current of Mp2 is I1 and the drain currents of Mn5, Mn6 should be I2 . However,

(14)

The complete circuit of this V-I converter is shown in Fig. 3 [7]. As we can see, this converter consists of a parallel connection of an N-type and a P-type converter cells, and also two maximum-current selecting circuits. The N-type converter cell is connected in parallel with the P-type complementary cell in order to cover all the operating common-mode input range from rail to rail. Both cells are linearized to extend the differential input signal swing. Through adjustments of transistor sizes, K N is set to be equal to K P . That is, the maximum gm values, gm N and gm P , which are also constant, are equal. Fig. 4 (a) shows the simulation result of the four currents In1 , In2 , I p1 , and I p2 (indicated in Fig. 3) as we change the common-mode voltage from rail to rail. After taking maximum values of (In1 , I p2 ) and (I p1 , In2 ), the result is shown in Fig. 4 (b). Thus, by using two maximum-current selecting circuits and a subtraction circuit, which subtracts current M AX (In2 , I p1 ) from current M AX (In1 , I p2 ), in the output stage, the output current is given by Iout = M AX (In1 , I p2 ) − M AX (In2 , I p1 ) p p = 2K N IC vin = 2K P IC vin = gmT 1 vin

(15) (16) (17)

where gmT 1 = gm N = gm P . Therefore, a rail-to-rail linear V-I converter is obtained. Notice, from Fig. 4 (a), that whenever In1 > I p2 that In2 > I p1 also and that whenever I p1 > In2 that I p2 > In1 also. So, at any given time, the output currents from one particular converter, the N- or the P-type, will be inputs to the subtraction circuit. That is, the total transconductance gmT 1 will just be the maximum value of gm N and gm P , as illustrated in Fig. 5. This also ensures that the nonlinearity cancelation as explained in Section II will always be maintained. The idea of a parallel connection of an N-type and a P-type cell circuits and the use of

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Fig. 3. The complete circuit of the Approach-I V-I converter. The arrows show the direction of the ac currents when Vin+ > Vin− .

Fig. 4. Simulation of (a) currents In1 , In2 , I p1 , and I p2 , (b) M AX (In1 , I p2 ) and M AX (In2 , I p1 ) for a rail-to-rail common mode input voltage sweep.

maximum-current selecting circuits can be widely extended to other computational circuits to reach the railto-rail operation for low-voltage VLSI applications. A similar principle has recently been used in the design of low-voltage/low-power opamps [8].

3.2.

Approach II

For a rail-to-rail V-I converter, if the total transconductance is the sum of the transconductances of the N-type and P-type cells, we need [4], [9] gm N + gm P = constant

(18)

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Fig. 5. Simulation of transconductance gm N , gm P , and gmT 1 for a rail-to-rail common mode input voltage sweep.

√ √ This means that we need IC N + IC P = constant if we set K N and K P equal, where IC N and IC P are the bias currents (IC ) in the N-type and P-type V-I converter cells, respectively. From Eq. (6) and (7), we can see that r p p KN Vdc I1 + I2 = 2 (19) 2 From the √ discussion √ in Section II, Vdc is constant and therefore I1 + I2 is also a constant. This means that the total transconductance will be constant if the bias currents IC N and IC P are provided by currents I1 and I2 of Eq. (6) and (7). Therefore, in addition to the complementary circuit of the N-type and P-type V-I converter cells, another pair of complementary N-type and P-type bias circuits are needed to provide proper DC bias currents such that a constant gm is achieved. The N-type bias circuit is shown in Fig. 6. The circuit is a modified version of the N-type V-I converter cell. M16 and M12 play the same roles as M1 and M3 of Fig. 1, respectively. Note that the output current,

Iout , which is the bias current IC N of the N-type V-I converter cell, is limited to 4IC , as the drain current of M16 will not exceed 4IC . The reason why we limit the maximum current to 4IC will become clear in the following discussion. The operation of the current limiter is also based on the fact that in a series connection of a current source (M15 ) and a current sink (M16 ), the minimum current always dominates [6]. The output current of this bias circuit will flow into the drain terminal of transistor M3 of the N-type V-I converter in Fig. 1. The complete circuit of the parallelly connected Ntype and P-type V-I converters with the N-type and its complementary P-type bias circuits is shown in Fig. 7 [9], [10]. The DC transfer equation of this complete V-I converter is derived next. For the bias currents IC N and IC P provided from the N-type and P-type bias circuits, assuming K N = K P = K , as in Eqs. (6), (7), and (19), we have r p p K IC N + IC P = 2 (20) VdcB 2

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Fig. 6. A circuit diagram of an N-type bias circuit.

Fig. 7. The complete circuit of the Approach-II V-I converter.

Low-Voltage CMOS √ where VdcB = 2IC /K (VdcB = Vdc due to the same bias currents IC for Figs. 1 and 6). Therefore, r r p p p K 2IC IC N + IC P = 2 (21) = 2 IC 2 K From Eq. (21), we can see why the current limiter is necessary. When one of the N-type or P-type bias circuits is turned off, the current limiter will limit the other bias current to 4IC which is consistent with Eq. (21),√e.g. when √ IC N = 0, IC P = 4IC , and √ IC N + IC P = 2 IC . For the N-type V-I converter cell, K ³ vin ´2 In1 = Vdc1 + (22) 2 2 K ³ vin ´2 In2 = Vdc1 − (23) 2 2 √ where Vdc1 = 2IC N /K . Thus, In1 − In2 = K Vdc1 vin

(24)

Similarly, for the P-type V-I converter cell, I p2 − I p1 = K Vdc2 vin √ where Vdc2 = 2IC P /K . Finally, Iout = (In1 − In2 ) + (I p2 − I p1 ) = K (Vdc1 + Vdc2 )vin r p 2 p = K ( IC N + IC P )vin K r 2 p 2 IC vin = K K p = 2 2K IC vin = gmT 2 vin

(25)

(26) (27) (28) (29) (30)

Notice that this resultant transconductance is different from that in Approach I, and that the total transconductance gmT 2 here is two times larger than the transconductance gmT 1 . This is because in Approach I, a constant transconductance is achieved by selecting the maximum value, instead of taking the sum of the two transconductances.

4.

Results

In this section, we discuss performance results of both circuits.

4.1.

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Approach I

The rail-to-rail V-I converter using the method of Approach I was fabricated in a 2µm N-well double-poly CMOS process by MOSIS having VT n = 0.8013V and VT p = −0.9793V . The chip microphotograph of this V-I converter is shown in Fig. 8. The transistor sizes used in this circuit are illustrated in Table 1. The power supply used for this circuit is a single 3V supply voltage. This circuit also works well with a power supply of 3V ± 0.3V . It can also operate at levels below 2.7 V depending on the DC bias current levels used and, of course, the values of VT n and VT p . For this rail-to-rail V-I converter, the measured DC transfer curves are illustrated in Figs. 9 and 10. In Fig. 9, the five straight lines were obtained when IC = 20µA, 40µA, 60µA, 90µA, and 140µA, respectively. We can see that the input signal swing is 2V P P when the bias current, IC , is varied from 20µA to 140µA. Also, the transconductance is changed from about 200µS to 400µS, as shown in the figure. In Fig. 10, when we decrease the input signal swing from 2V P P to 1V P P to keep the same linearity as in Fig. 9, a larger transconductance range, from 100µS to 400µS, is obtained while the bias current, IC , is tuned from 3µA to 150µA. The larger transconductance tuning range is achieved through the tradeoff of the smaller input signal swing. Fig. 11 shows the measured output current for a rail-to-rail common mode input voltage sweep when we set vin = 0.1V . The maximum output current variation is about 15%. From this figure, we can see that the rail-to-rail operation of this V-I converter is achieved. As for the linearity of the V-I converter, there is about 1.61% and 2.46% total harmonic distortion (THD) for 1V P P and 2V P P 10KHz input signals, respectively.

4.2.

Approach II

The rail-to-rail V-I converter using Approach II is being fabricated in the 1.2µm CMOS process of AMS, having VT n = 0.736V and VT p = −0.751V , in Austria, so in this section only the HSPICE simulation results are presented. The transistor sizes used are shown in Table 2. The power supply used for this circuit is a single 3V supply voltage and the circuit can also work well with a power supply of 2.7 V or lower depending on the values of VT used and on the levels of the DC bias currents. Generally, note that the minimum supply

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Fig. 8. The chip microphotograph of the V-I converter by Approach I. The figure shows clockwise starting from the top left hand corner, N-type cell, output subtraction stage, two maximum current-selecting circuits, and P-type cell.

Table 1. The transistor sizes of the V-I converter by Approach I.

Transistor

W/L (µm/µm)

Comment

M1, M2, M3

50/3

N-type V-I Converter

M4, M5

200/2

cell

M6, M7, M8

500/3

Mp1, Mp2, Mp3

140/3

P-type V-I Converter

Mp4, Mp5

70/2

cell

Mp6, Mp7, Mp8

1400/3

Mp11, Mp12, MO1, MO2

280/2

Maximum-current selecting

Mn 14, Mn15, Mn16, Mn17 Mn18, MO3, MO4

100/2

circuit and output stage

Low-Voltage CMOS

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Fig. 9. The measured DC transfer curves of the Approach-I V-I converter with IC = 20µA, 40µA, 60µA, 90µA, and 140µA, respectively.

Fig. 10. The measured DC transfer curves of the Approach-I V-I converter with IC = 3µA, 20µA, 50µA, and 150µA, respectively.

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Fig. 11. The measured output current of the Approach-I V-I converter for a rail-to-rail common mode input voltage sweep with vin = 0.1V .

Table 2. The transistor sizes of the V-I converter by Approach II.

Transistor

W/L (µm/µm)

Comment

M1, M2, M3, M12, M16

3.6/6

N-type V-I Converter

M4, M5, M11, M14, M15, M17, M18

60/3

cell and

110.4/1.8

bias circuit

M6, M7, M8, M13, M19, M20 M9, M10

9.6/3

Mp1, Mp2, Mp3, Mp12, Mp16

8.4/6

P-type V-I Converter

Mp4, Mp5, Mp11, Mp14, Mp15, Mp17, Mp18

20.4/3

cell and

Mp6, Mp7, Mp8, Mp13, Mp19, Mp20

330/1.8

bias circuit

Mp9, Mp10

12/3

MO2, MO5, MO6, MO8

10.2/1.8

MO1, MO3, MO4, MO7

30/1.8

Output stage

Low-Voltage CMOS

Fig. 12. The DC transfer curves of the Approach-II V-I converter with IC = 0.5µA, 1µA, 2µA, and 4µA, respectively.

voltage that can be used in both Approach I and II is approximately equal to 2VG S + 2VDS,sat . Below this level the input transistors may go from strong to weak inversion and the DC bias current sink (source) of the N-type (P-type) cell may go from the saturation to the triode region. For the rail-to-rail V-I converter, the simulated V-I curves are shown in Figs. 12 and 13. In Fig. 12, the four V-I curves were obtained when IC = 0.5µA, 1µA, 2µA, and 4µA, respectively. We can see that the input signal swing is 2V P P and that the transconductance is changed from about 10µS to 30µS by changing the bias current, IC , from 0.5µA to 4µA. In Fig. 13, when we decrease the input signal swing from 2V P P to 1.4V P P to keep the same linearity, a larger transconductance range, from l0µS to 40µS, is obtained while the bias current, IC , is tuned from 0.5µA to 7µA. Fig. 14 shows the output current for a rail-to-rail common mode input voltage sweep using vin = 0.4V . The two bumps at common-mode input voltages close to 1V and 2V are because the N-type input transistors are not entirely cut off, but work in the weak-inversion region when the P-type transistors are entering the strong saturation region, and vice versa. The maximum output current variation is about 7%. From this figure, we can also see that the rail-to-rail operation of this V-I converter is achieved. For the linearity of the V-I converter, there is about 0.6615% and 0.8470% THD for 1V P P and 2V P P 10KHz input signals, respectively. At IC = 2µA and VC M = 1.5V , the DC power con-

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Fig. 13. The DC transfer curves of the Approach-II V-I converter with IC = 0.5µA, 1µA, 2µA, 4µA, and 7µA, respectively.

sumption for the Approach-II circuit is about 0.31 mW. When we decrease the transistor sizes of the ApproachI circuit to have the same output transconductance as Approach II at IC = 2µA, its power consumption is only about 0.12 mW when VC M = 1.5V . In Approach II, a constant gm is achieved through additional circuitry to the DC part of the circuit. This may not be very suited for low-power applications. On the other hand, in Approach I, a constant gm is achieved by manipulating the output, rather than DC, currents of the N- and P-type cells. This leads to saving in power consumption. 5.

Conclusions

In this paper, two different approaches to design a lowvoltage rail-to-rail CMOS V-I converter are introduced. Both of the converters include a combination of an Ntype and P-type V-I converter cells connected in parallel to obtain the rail-to-rail input range. In Approach I, the method for a parallel connection of an N-type and a P-type cell circuits and the inclusion of two maximumcurrent selecting circuits can be widely extended to other computational circuits to reach rail-to-rail operation for low-voltage VLSI applications. In Approach II, in addition to the parallel connection of an N-type and a P-type converter cell, bias currents are taken from another pair of parallelly connected N-type and P-type bias control circuits to achieve constant transconductance. The applications of the new circuits are many,

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Fig. 14. The output current of the Approach-II V-I converter for a rail-to-rail common mode input voltage sweep with vin = 0.4V .

e.g. Operational Transconductance Amplifiers (OTA) in a GM-C filter with rail-to-rail common-mode input voltage [11]. They are also suitable for the development of a family of computational circuits, which can be seen as rail-to-rail low-voltage counterparts of the computational circuits in [1] and [12]. Another important application which takes advantage of the rail-torail common-mode operation is the use of these circuits in the implementation of large transconductance-based analog VLSI circuits, such as the cellular neural network implementation proposed in [13]. In this case, no DC level shifting will be required between outputs and inputs of different transconductors in the network.

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References 9. 1. S. R. Zarabadi, M. Ismail, and C.-C. Hung, “BiCMOS analog computational circuits,” in Microelectronics for Telecommunications, IV EBMicro—Escola Brasileira de Microeletronica (IV Brazilian Microelectronics School), Recife, Brazil, Jan. 15–20, 1995. Also see Ch. 5 in Analog VLSI: Signal and Information Processing, M. Ismail and T. Fiez (Eds.), McGraw Hill: New York, 1994. 2. S. R. Zarabadi and M. Ismail, “Linear voltage to current converter including feed-back network,” U.S. Patent No.5,317,279, issued May 31, 1994. 3. S. T. Dupuie and M. Ismail, “High frequency CMOS transconductors,” in Analog IC Design: The Current-Mode Approach

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(C. Toumazou, F. J. Lidgey, and D. G. Haigh, eds.), ch. 5. Peter Peregrinus Ltd., London, 1990. S. Sakurai and M. Ismail, “Robust design of rail-to-rail CMOS operational amplifier for a low power supply voltage.” IEEE Journal of Solid-State Circuits 31(2), pp. 146–156, Feb. 1996. E. A. Vittoz, “Analog VLSI signal processing: Why, where, and how?” Analog Integrated Circuits Signal Process. 6(1), pp. 27–44, July 1994. J. H. Botma, R. F. Wassenaar, and R. J. Wiegerink, “Simple rail-to-rail low-voltage constant-transconductance CMOS input stage in weak inversion.” Electron Letter 29, pp. 1145– 1146, 1993. C.-C. Hung, C. Hwang, K. Halonen, V. Porra, and M. Ismail, “CMOS analog cells for low-voltage VLSI signal processing applications,” in Proc. 39th Midwest Symposium on Circuits and Systems, Ames, Iowa, Aug. 1996. C. Hwang, A. Motamed, and M. Ismail, “Universal constantgm Iinput-stage architectures for low-voltage Op Amps.” IEEE Trans. Circuits and Systems I 42(11), pp. 886–895, Nov. 1995. P.-P. Vervoort and R. F. Wassenaar, “A CMOS V-I converter with a constant transconductance for common and differential input voltage,” in Proc. 2nd Intl. Conference on Electronics, Circuits, and Systems (ICECS), Amman, Jordan, Dec. 1995, pp. 161–164. C.-C. Hung, C. Hwang, and M. Ismail, ”A CMOS Low-Voltage Rail-To-Rail V-I Converter,” in Proc. 38th Midwest Symposium on Circuits and Systems, Rio de Janeiro, Brazil, Aug. 1995, pp. 1337–1340. C.-C. Hung, K. Halonen, V. Porra, and M. Ismail, “Lowvoltage CMOS GM-C filter with rail-to-rail common-mode voltage,” in Proc. 39th Midwest Symposium on Circuits and Systems, Ames, Iowa, Aug. 1996.