Analog Integr Circ Sig Process DOI 10.1007/s10470-017-1071-7

MIXED SIGNAL LETTER

Over rail-to-rail fully differential voltage-to-current converters for nm scale CMOS technology Andrzej Handkiewicz1 • Szymon Szcze¸sny2 • Marek Kropidłowski2

Received: 21 September 2017 / Accepted: 30 October 2017 Ó Springer Science+Business Media, LLC 2017

Abstract The converters presented in this paper are based on long channel complementary MOS transistors, instead of the commonly used differential amplifiers or differential transistor pairs which are difficult to implement in low voltage, nm scale CMOS technology. Nonlinearities of drain currents can be cancelled in the fully differential structure. As a result, the low power, nanometre standard digital CMOS technology converters are obtained. Layout examples are designed in 65 nm TSMC technology. Postlayout simulations show that the range of input voltage over rail-to-rail is achieved with very good linearity and reduced harmonic distortion. Keywords Voltage-to-current converters  Low power circuits  Analog circuit design  Standard digital CMOS technology

1 Introduction Voltage-to-current (V-I) converters are very useful cells in many applications like interface circuits, data converters, variable-gain amplifiers, oscillators and filters. A resistor is the simplest voltage-to-current or current-to-voltage converter. Two equivalent circuits which illustrate such a conversion are shown in Fig. 1(a). The condition under

& Andrzej Handkiewicz [email protected] 1

Technical Faculty, AJP, ul. F. Chopina 52, 66-400 Gorzow Wielkopolski, Poland

2

Faculty of Computing, Poznan´ University of Technology, ul. Piotrowo 3a, 60-965 Poznan, Poland

which the largest part of the current I ¼ V  G flows to the load is: R [ [ RL or G\\GL ;

ð1Þ

where G ¼ 1=R and GL ¼ 1=RL . Assuming that the voltage signals most convenient for CMOS technology are about 1 V and current signals are several lA, the value of R has to be no fewer than hundreds of kX0 s. Such resistance is not achievable in this technology and to solve this problem an active circuit with resistive input can be used, as shown for example in [1] or [2]. Let us note that in the approach illustrated in Fig. 1(a), the voltage input signal is delivered to the same node into which the output current flows. In this paper, VCR will be an acronym for a converter based on the idea of a huge resistance. Another current-to-voltage conversion is achieved with the use of a voltage-to-current transducer (VCT) presented in Fig. 1(b), in which the voltage node (V) and the current node are separated. The k and a scaling factors of an amplifier and a current mirror CM, respectively, facilitate a satisfactory transconductance g for G realizable on a chip. Two approaches dominate in the literature for implementing such a circuit in CMOS technology. The first one, based on an operational amplifier (OA) or an operational transconductance amplifier (OTA) used as buffers between the voltage and current nodes, is presented in [3] for example. In the second approach, a differential cell in which drain currents of two differential transistors are in proportion to a differential voltage delivered to their gates is used, as shown in [4] or [5]. CMOS technology development is currently oriented to digital circuits. Today it is very difficult to obtain classical analogue circuits like op-amps and various kinds of amplifiers in nanoscale low-voltage supply CMOS technology, which are the basic cells of the current-to-voltage

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Analog Integr Circ Sig Process

2 Long channel transistors for voltage-to-current conversion

Fig. 1 Models of V-I converters: resistor used as a voltage-to-current converter (a), Voltage-to-current transducer -VCT (b), macro-model of a V-I converter (c)

converters presented thus far. The paper [6] is an example which illustrates this problem well. The analogue part, composed of a buffer and amplifiers, of ADC presented in this work must be supplied at 1.8 V, while the standard supply is 1 V for the used 28 nm CMOS technology. Implementation of analogue circuits in nanometre digital technologies is easier in current mode, as demonstrated in [7]. In the era of deeply scaled CMOS, current mode operation is also an interesting alternative for logic circuits, [8]. We will show that the converters proposed in this paper, composed of long channel transistors and current mode compensation circuits, are able to meet the requirements of modern technologies. To achieve low power consumption and low noise at current mode operation, the transistor channels have to be as narrow as possible in the chosen technology. Fully differential structure of the proposed converters makes it possible to compensate nonlinearities and to reduce parasitic influence. Because of current mode operation of the designed cells, the obtained circuits can operate precisely at low voltage supply. In the next section the circuits that we propose to use as converters are described briefly. The next two sections show implementations in TSMC 65 nm technology of both kinds of converters based on these circuits.

As was mentioned in Introduction, the simplest idea for performing a V-I conversion is to use a passive resistor in series connection between a voltage source and a load. However, the several hundred kX resistor, necessary in such an application, is not feasible on a chip in CMOS technology. Instead of resistors in this section we will consider long channel transistors. Circuits composed of such a complementary pair of MOS transistors are presented in Fig. 2. Loads are not shown in the figure and the bulks of the nMOS and pMOS transistors are supplied from VSS and VDD voltage sources respectively. Using the circuit in Fig. 2(a) we will try to replace a huge resistor with long channel transistors in a non-saturation region. This region needs carefully chosen gate voltages. For the inverter in Fig. 2(b) we can obtain linear dependence of the output current Io on the input voltage V for the saturation region of both transistors. However, this is not satisfactory if we want to operate in rail-to-rail area. We assume that the input voltage V changes in the railto-rail region VSS \V\VDD ;

ð2Þ

and is achievable as fully differential signal. To have both transistors in Fig. 2(a) in an active mode, the proper polarization is obtained for V [ 0:

ð3Þ

If the signal is negative, V\0;

ð4Þ

Fig. 2 Basic circuits of a voltage-to-current converter, based on long channel CMOS transistors: with the input voltage delivered to the sources (a) and to the gates (b) of the transistors, respectively

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Analog Integr Circ Sig Process

both transistors are in cut-off mode and a twin circuit is necessary, with opposite signs of V delivered to the transistor sources. Considering the circuit in Fig. 2(b) we can divide the rail-to-rail range of the input voltage V into three subregions VSS \V\VSS þ VTn ;

ð5Þ

VSS þ VTn  V  VDD þ VTp ;

ð6Þ

VDD þ VTp \V\VDD :

ð7Þ

In the above areas, the transistors are in different modes. In the (6) range both transistors are in saturation region. In the (5) range the nMOS transistor from Fig. 2(b) is off and the pMOS is in non-saturation region. In the last (7) of the considered areas the transistor pMOS is off and the nMOS is in non-saturation region. Analysis, based on the standard square law models like that presented in [9] or [10] and depending of the considered region, of the circuits in Fig. 2 shows that a complementary pair of transistors can be useful in voltage-tocurrent conversion for proper gate voltages and transistor sizing. The idea to use inverter connection from Fig. 2(b) for voltage-to-current conversion is not new, [9]. However, the obtained circuits were unsatisfactory with respect to linearity and input voltage range. In the next sections we will show, that for transistor’s channels which are enough long, the resulting converters have very good linearity and frequency characteristics.

3 VCR converter The first kind of a V-I converter in the fully differential structure, composed of four basic circuits from Fig. 2(a), is presented in Fig. 3. Values of transistor widths and values of polarization voltages are indicated in the figure. The compensation circuit COMP, which is the second stage of the converter, is composed of three two-output

Fig. 3 Circuit diagram of the first kind converter (VCR) with gate voltages (V) and channel widths (nm). The channel lengths of all transistors are L = 1800 nm

current mirrors as described in [11]. Such circuits, capable of working at low voltage supply, were presented in our previous papers, for example in [12], and the design automation system to obtain the circuits is presented in [13]. The main functions of this second stage circuit are to tune the transconductance value, to reduce the common mode signal and to decrease the output voltage swing. Because of long channel transistors used to build the first stage, the third function of the second stage is also significant. We assume that the converters are loaded in circuits composed of two complementary transistors in a diode connection (NMOS: L = 400 nm, W = 160 nm, PMOS: L = 400 nm, W = 445 nm), not shown in the figure. Such circuit is able to carry 87 lA current capacity. The layout, presented in Fig. 4, was designed in Mentor Graphics environment on a chip area 23:95 lm  16:99lm for TSMC 65 nm technology. The long channel transistors of the first stage of the converter are located in the top part of the figure and the three current mirrors of the second stage are on the bottom. The parasitic parameters of the circuit were extracted with the use of Calibre. Such circuit was simulated in all details. The relation of the output differential current I ¼ I þ  I  versus differential value of input voltage, V ¼ V þ  V  , was obtained in DC analysis. Two parameters are calculated on the basis of the function I(V): a linearity error LE(V) and a transconductance g(V). The linearity error LEðVÞ ¼

jIðVÞ  Ilin ðVÞj ; maxðIlin Þ  minðIlin Þ

ð8Þ

is based on a distance jIðVÞ  Ilin ðVÞj of the function I(V) to its linear approximation Ilin ðVÞ, similarly as it is defined dI . in [14]. The transconductance is calculated as gðVÞ ¼ dV The proper programs in MATLAB are written to calculate LE and g. The linearity error for this converter is shown in Fig. 5(a), with the acronym VCR used, and is smaller than 0:8% in the voltage range twice that of over rail-to-rail.

Fig. 4 Layout of the VCR converter in TSMC 65nm technology

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Analog Integr Circ Sig Process

Fig. 5 Characteristics of the converters, composed of long channel CMOS transistors, obtained in DC post-layout simulations: linearity errors (a), normalized transconductances (b), output currents for railto-rail common mode input voltage sweep (c)

Fig. 5(b) shows the transconductance g(V) normalized with respect to gð0Þr ¼ 6:78 lS. To illustrate better the linearity of converters a triangular voltage waveform is delivered to their inputs, to perform not only DC but also the transient analysis. To analyse different ranges of input voltage the smaller (0.5 V) and the bigger (1 V) amplitudes were chosen in Fig. 6. For better transparency of this result, the transient

analysis is shown exclusively for a VCR converter. The left vertical axis corresponds to voltage (solid line) and the right vertical axis corresponds to current (dashed line) waveforms, respectively. The transient simulations allow to determine the parameters of a converter macro-model, presented in Fig. 1(c). The parameters, calculated with the use of peak to peak values of triangular waveforms of voltages and currents, like in Fig. 6, for two different loads are as follows: g ¼ 6:66 lS, Gi ¼ 22:61 lS, Go ¼ 1:82 lS. The current delivered from the supply to the first stage of the converter is less than 100 nA and can be ignored with respect to the current of the second stage circuit. The power consumption is 22:29 lW at standard in the technology voltage supply 1:2 V. The differential current, as a difference of currents from positive and negative outputs, for common mode input voltages, V þ ¼ V  ¼ V, is shown in Fig. 5(c). This current is at least one order of magnitude smaller than presented in [4] for example. It is the result of a fully differential structure of the converter and the compensation circuit used as the second stage. It makes it possible to achieve very good CMRR (common mode rejection ratio) in our circuit. We will calculate CMRR as a ratio between the differential gain and the common mode gain. The differential gain obtained on the basis of the DC analysis mentioned at the beginning is ð7:6  ð 7:6ÞÞlA=2:4 V and the common-mode gain from Fig. 5(c) is 0:072 lA=2:4V. The obtained value of CMRR is then 46.5 dB. The frequency response of VCR, obtained after transient analysis, is presented in Fig. 7(a). The cut-off frequency for 3 dB attenuation is equal to 398 MHz. Such analysis, with 1Vpp sinusoid, was also performed to obtain THD with respect to frequency, as it is presented in Fig. 7(b). The transient analysis, for a sinusoid with 100 kHz frequency and changed amplitude Vamp , allows us to obtain THD as a function of signal value shown in Fig. 7(c). A figure of merit (FoM), which is defined as FoM ¼

Fig. 6 Waveforms obtained on the input and the output of the converter

123

Vin Vsupp

BW

P

;

ð9Þ

[3], for our data: Vin ¼ 2:4 V, Vsupp ¼ 1:2 V, BW ¼ 398 MHz, P ¼ 0:0223 mW, assumes the value MHz 35695 mW which is at least two orders of magnitude better than presented in the literature, [3]. In the end, analysis of circuits sensitivity to the dispersion of polarization voltages of biases was performed. Assuming the power supply of the circuit is symmetrical, generating a -0.6 V voltage does not require additional implementation. The result of the analysis is shown in Fig. 8 in the form of changes of the nonlinearity error. As you can see, a 0.35 V voltage dispersion does not significantly affect the processing

Analog Integr Circ Sig Process

Fig. 8 Change of the VCR nonlinearity error (LE) depending on the dispersion of polarization voltages: for voltages of 0.35, 0.7 V and for both voltages

Fig. 9 Circuit diagram of the second kind converter (VCT) with channel widths (nm). The channel lengths of all transistors are L = 1800 nm

Fig. 7 Characteristics of the converters obtained in transient postlayout simulations: frequency characteristics (a), THD as a function of frequency (b) and as a function of signal value (c)

accuracy. In case of a 0.7 V voltage dispersion of 40%, the nonlinearity error equals no more than 4%. We see that the converter with excellent properties is obtained and, because of the differential structure, it operates in an input voltage region twice that of the rail-to-rail range.

4 VCT converter The VCT converter, like VCR one, is also composed of two stages. The difference lies in the first stage, now built of two basic circuits presented in Fig. 2(b). The circuit diagram of the VCT is shown in Fig. 9. Values of transistor widths are indicated in the figure. Results of transient

analysis for 400, 900 and 1800 nm channel lengths of the transistors in the first stage are presented in Fig. 10. As mentioned in Section 2, Fig. 10 illustrates good linearity in voltage-to-current conversion for all channel lengths exclusively in the (6) region. In the (5) and (7) regions the linearity is satisfactory only for channel length equal to 1800 nm. The simulations were performed as pre-layout, because layout was only generated for the longest channels L = 1800 nm. The described analysis is the simplest and effective method of selecting transistor lengths of the converter. The layout, presented in Fig. 11, was also designed in Mentor Graphics environment on a chip area 28:74 lm  10:66 lm for TSMC 65 nm technology. As can be seen, the long channel transistors are located on the left part of the chip. With the use of Calibre, the parasitic parameters were extracted. Power consumption is equal to 26:82 lW, where only less than 14% is delivered to the first stage. In Fig. 5(b) the transconductance g is shown which is normalized to gð0Þ ¼ 11:75 lS. The linearity error, shown in

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Analog Integr Circ Sig Process

Fig. 10 Waveforms of the VCT converter composed of transistors with 400, 900 and 1800 nm channel lengths, respectively

Fig. 11 Layout of the VCT converter in TSMC 65 nm technology

Fig. 5(a), is smaller than 0:7% in the voltage range from  1:1 V to 1.1 V which is nearly two times over rail-torail. Similarly, as previously, the transient analysis gives parameters of a macro-model in Fig. 1(c). The calculated values are: g ¼ 12:43 lS and Go ¼ 3:49 lS, while the conductance Gi can be neglected. SI-Studio environment, [13], makes it possible to design the compensation circuit with proper transistor sizing, so that the voltage swing on the output is small. As was mentioned previously, the converters are loaded in complementary pair of CMOS transistors in diode connection. For the load circuit composed of transistors with medium channel lengths equal to 400 nm, the differential voltage swing is about 575 mV, which is 24% of the differential input voltage (2.4 V). This means that the relatively large output conductance Go does not cause significant error of the output current when the load is changed. For example, if the load changes in the whole assumed design space (the channel lengths between 80 and 1000 nm) this error is approximately 10%. For the common mode input voltage, the differential current, denoted as VCT, is presented in Fig. 5(c). This result shows that as for the previous kind of converter,

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CMRR is also large. The obtained value of CMRR calculated as ð13:5  ð13:6ÞÞl A=2:4 V, from DC analysis, divided by 0:108l A=2:4 V, from Fig. 5(c), is then 48 dB. Let us note, that the power supply rejection ratio (PSRR) and common mode rejection ratio (CMRR) are well defined in the case of OpAmp’s or OTA’s, see [15] for example. It is clear, that our converter which does not use OpAmp’s or OTA’s is sensitive to supply voltage changes. It denotes that PSRR is relatively low, especially for VCT converter, as it is shown in Fig. 12. However, in our circuits this parameter does not change up to 100 MHz, while in the case of OpAmp, PSRR falls rapidly with the frequency. The frequency response of VCT, obtained after transient analysis, is presented in Fig. 7(a). The cut-off frequency for 3 dB attenuation is equal to 1124 MHz. Such analysis was also performed to obtain THD as a function of frequency shown in Fig. 7(b). Similarly as for the VCR converter, THD is obtained and presented in Fig. 7(c) with respect to a sinusoid amplitude. A figure of merit (FoM) for the VCT converter data assumes the 76891 MHz mW value. Properties of both converters are compared to other realizations in Table 1. In the CTA column, the pre-layout results from [2], in the CAS column the measurement results from [3], in the column SoC from [16], in the column from [17] and in the VCR and VCT columns the postlayout results of our converters are presented. The sensitivity of VCR and VCT circuits to process dispersion was analysed using TSMC manufacturer technology files. Results are shown in Fig. 13. The linearity error in the rail-to-rail range is below 1.8% and in the voltage range twice that of over rail-to-rail is equal to 3.04%. Next, sensitivity analysis for supply dispersion was performed and discussed in the end of Sect. 3. Finally,

Fig. 12 Results of PSRR calculations for VCR and VCT converters

Analog Integr Circ Sig Process Table 1 Comparison of voltage-to-current converters

Parameter

CTA

CAS

SoC

AppPh

VCR

VCT

CMOS

180 nm

180 nm

350 nm

600 nm

65 nm

65 nm

Supply voltage

1V

1.2 V

3.0

2.5

1.2 V

1.2 V

g ½lS

100

12.5

–

–

6.66

12.43

Input range [V]

0–1

0–1.18

0.2–0.3

0.6–1.8

- 1.2 to 1.2

- 1.1 to 1.1

Bandwidth [MHz]

39.2

14.5

–

0.01

398

1124

–

–

THD [dB] for 1Vpp

- 44.4

- 51.6

@1 MHz

@100 kHz

Power ½lW

730

75

1000

FoM [MHz/mW]

54

190

–

–

0.0112

–

2

Area ½mm 

- 38

- 66.1

@5 MHz

@5 MHz

–

22.29

26.82

–

35695

76891

0.0064

0.000407

0.000306

converters obtained up to now are only close to rail-to-rail. Fig. 12 shows that the weakness of our solution is a small PSRR. In some applications it can be necessary to use rectifiers to supply converters, especially in the case of VCT. FoM of the realized converters is at least two orders of magnitude better than reported in the literature.

References

Fig. 13 Process dispersion analysis for VCT circuit (solid lines) and VCR circuit (dotted lines): SS slow NMOS and slow PMOS, SF slow NMOS and fast PMOS, FS fast NMOS and slow PMOS, FF fast NMOS and fast PMOS

PSRR calculation is added with a suitable comment in Sect. 4.

5 Conclusions Two kinds of V-I converters are presented in the paper: with common and separated input voltage and output current nodes, respectively. The novelty consists in using long channel transistors and a fully differential structure. Highly linear and over rail-to-rail converters are obtained in this approach. Because of only two complementary transistors stacked up between both supply rails, the converters can operate effectively in nanometre standard digital CMOS technology at low voltage supply. The converters were designed in 65 nm TSMC technology and post-layout simulations show very good properties with respect to linearity, frequency range, harmonic distortion, common mode rejection and power consumption. The obtained input voltage range is up to twice of rail-to-rail voltage, while

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Andrzej Handkiewicz is a professor at the Technical Faculty, AJP, Gorzow Wlkp. Until September 2017 he was also a professor at the Faculty of Computing, Chair of Computer Engineering, Poznan University of Technology, Poznan, Poland. In 1990 he was on research leave at the Swiss Federal Institute of Technology in Zurich. He is a member of many Polish and international (IEEE, IEICE) scientific societies. He is the author of the book ’MixedSignal Systems: A Guide to CMOS Circuits Design’ edited by Wiley-

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IEEE. He has published over 100 technical articles in the areas of mixed- signal circuits for filtering and image compression. Szymon Szcze¸sny graduated in 2008 from Automatics and Management at the Faculty of Computing and Management of the Poznan University of Technology. In 2013 he defended a thesis in Computer Science at the Faculty of Computing and Management of the Poznan University of Technology, qualifying as a Ph.D. He is mainly interested in tasks for automating processes of designing layouts of currentmode circuits with switched currents with the use of hardware description languages. He is mainly interested in tasks for automating processes of designing layouts of circuits with switched currents, prediction of defects in processes of topography fabrication and algorithms for synthesising analogue circuits by using hardware description languages. Marek Kropidłowski received the M.S. degree in telecommunication and elec- tronic engineering and Ph.D. degree in automatic control and robotics all form Poznan University of Technology, Poznan, Poland. His current research interests cover digital systems design, one- and two-dimensional signal processing and em- bedded systems based on FPGA.