Appl Phys A (2012) 106:967–982 DOI 10.1007/s00339-011-6724-2

Realistic limits to computation III. Climbing the third dimension G.F. Cerofolini

Received: 1 August 2011 / Accepted: 7 December 2011 / Published online: 24 December 2011 © Springer-Verlag 2011

Abstract As far as ultra-dense crossbars are related to correspondingly dense wire arrays, the crossbar route to terascale integration depends on the availability of preparation techniques for wire arrays with density of 106 cm−1 or more. This linear density implies, for a planar arrangement, a pitch of 10 nm or less, which not only is at the limits of the current technical possibilities, but also can modify appreciably the band structure of silicon. A dramatic increase of density could only be achieved if it were possible to organize the nanowires in a three-dimensional fashion still exploiting the planar technology. In this work processes are described for the fabrication of out-of-plane, vertically arranged, polycrystalline silicon nanowires via a rigorously top-down batch process. These techniques are consistent with the production of wire arrays with linear density (projected on the surface) larger than that achievable with any other proposed top-down process. Used for the fabrication of the bottom wire arrays of crossbars, these processes should eventually allow a cross-point amount per unit area in excess of 1012 cm−2 , thus providing candidate technologies for ultra tera scale integration. The technique developed for such out-of-plane crossbars can be used to implement new functions like coils, solenoids and transformers. Keywords Nanoelectronics · Sublithographic definition techniques · Silicon nanowires · Crossbar · 3D integration · Demultiplexing · Nanoscale solenoid

G.F. Cerofolini () Department of Materials Science, University of Milano–Bicocca, via Cozzi 53, 20125 Milano, Italy e-mail: [email protected]

1 Introduction Predicting the ultimate limits at which information can be stored and managed in complex circuits is not trivial, because it is not clear which constraints can reasonably be posed. In the first part of this series [1], I assumed operation at room temperature and a planar arrangement of the elementary units, while in the second part I considered the technological limits imposed by the planar technology [2]. There I showed that the tera-scale integration (TSI)1 is the upper limit of what is potentially achievable by means of hybrid combinations of CMOS (complementary metal–oxide– semiconductor) platforms with electrically configurable materials. On another side, it is highly probable that the current CMOS technology will succeed in developing along its mainstream to a final density of about 2–3 × 1011 cm−2 . Due to the enormous efforts required for the development of new technologies, it is highly questionable that any new hybrid technology, based on reconfigurable materials, rather than on transistors, as memory elements may replace the CMOS technology for gaining a factor of four only in final densities; the situation would instead be very different for any new technology that allowed the production of circuits with ultra TSI (UTSI). In this work I shall show that the batch fabrication of UTSI circuits is possible by relaxing the condition of pla1 With GSI (giga-scale integration), TSI and so on, one intends the abil-

ity to integrate 109 , 1012 etc. switching elements in the same chip. Generally, the chip area of complex circuits is slightly larger than 1 cm2 , so that the above numbers are also a (slight) overestimate of the amount per square centimetre. Since the interest of this work is also addressed to the preparation of complex but small circuits (e.g. with total area of 102 µm2 ), I instead assume that acronyms GSI, TSI etc. denote the ability to batch fabricate at the density of 109 , 1012 cm−2 etc. Unless otherwise specified, ‘density’ will henceforth be the short form of ‘areal density’.

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nar arrangement assumed in [1] however preserving, as in [2], their producibility via the planar technology. I shall also show that not only does the new architectures allow the integration in the circuit of new devices, but also that they are able to add new functions to the CMOS platform.

2 Preliminary considerations Fixing the attention on density and assuming with Feynman that computation can be performed using as elementary bits the atoms at solid surfaces (at a density of the order of 1015 cm−2 ), the maximum achievable density would be consistent with circuits (memories in particular) with peta-scale integration (PSI)—the Feynman limit [3]. Although scanning tunnelling probes demonstrate that managing (i.e. modifying and sensing) the information stored in an atom (as conformation, charge or spin state) is possible, the job is nonetheless difficult. This is especially true if one wants to manage gigabits (rather than single bits) on a laboratory time scale. The information cannot be stored as (positive or negative) charge states because allowed situations, where almost all surface atoms are charged, would be characterized by huge electric fields (of the order of 109 V cm−1 , because of the Gauss theorem), much higher than the breakdown field of any known material. It could however be stored as a metastable conformation state of surface atoms or as internally ionized states A+ B− of pairs AB of surface atoms that in the ground state are neutral. Since both these states may be viewed as defects of the equilibrium states, in practice any configuration is out of equilibrium, with a configuration entropy diverging for θ → 0 or θ → 1, where θ is the fraction of surface atoms in the excited state. These occurrences imply that a memory necessarily works under non-equilibrium conditions and emphasizes the unavoidable errors in data storage [4]. A different approach for attaining the ultimate computation limits stands on Drexler ideas. In a series of publications started in 1982 and culminating in a book on molecular machines, manufacturing and computation, Drexler suggested that the optimal scale for the exploitation of microscopic objects at the macroscopic scale is the molecular or supermolecular one [5]. Limiting the attention to computation, there are molecules with properties that to some extent mimic the ones of the field-effect transistor (FET); in particular, some π conjugated molecules may undergo redox reactions to metastable excited states with conductance differing by orders of magnitude from that in the fundamental state. They may thus be viewed as reconfigurable molecules with potential application as memory elements. Ignoring their detailed shape, they may be modelled as cylinders of diameter δ of the order of 1 nm and length , in the interval 4–5 nm. Assuming that the molecules are orderly arranged on a surface

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and packed in such a way that each of them does not overlap regions potentially interested by the neighbouring ones, irrespective of their orientations, each of them would occupy an area (δ + 2)2 , so that the maximum achievable density would therefore be in the interval 0.8–1.2 × 1012 cm−2 . Any process able to impart a preferential orientation to the molecules and thus to reduce the molecule separation from 2 to l (with l < 2) will increase the bit density to (δ + l)−2 , so that the use of molecules as elementary information units would permit ultra tera scale integration (UTSI). The quantity 12 (δ + l) is usually defined as feature size f and the plane tiled with a square lattice of bits with feature size f (thus with bit density of 1/4f 2 ) is referred to as 4f 2 architecture. There is a widespread consensus that the maximum achievable planar density is just (4f 2 )−1 , although there is no theorem supporting this statement. Producing molecular devices with UTSI complexity is, however, a major technological problem: even assuming the ability to self-assemble the molecules in an ordered way at a solid surface (for instance, via the Langmuir–Blodgett deposition technique), there remains the problem of controlling them by external electrodes, linking the molecular world to conventional CMOS circuitry. The self-assembled monolayer (SAM) of reprogrammable molecules can be integrated with a silicon-based platform in a rigorous top-down approach exploiting the crossbar architecture [6–10], for which the following organization seems the most natural one [11, 12]: – a CMOS platform (including the functions of power supply, input–output, addressing, sensing etc.), embedding – an ultra-dense crossbar (formed by two perpendicularly oriented nanowire arrays), hosting – a nanoscale reconfigurable element in each cross-point: ⎧ ⎫ ⎨ CMOS platform, ⎬ TSI circuit = ultra-dense crossbar, (1) ⎩ ⎭ nanoscale elements. If all cross-points forming the crossbar have a rectifying behaviour, are equivalent and are equally accessible, then the structure may behave as a memory. As discussed in the next section, the nanoscale element is not necessarily formed by a packet of reconfigurable molecules. Of course, the material nature of the nanoscale element impacts severely on the preparation process; although some steps may resemble bottom-up processes, organization (1) is substantially top-down.

3 Functional materials This section is intended to give a scheme of the functional materials that have been considered or proposed as memory

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elements. It is in no way addressed to describe the material properties, but rather to discuss their scaling possibilities and integration issues in (1). The list starts from reconfigurable molecules that, in Drexler frame, should be the minimum element able to store the information. 3.1 Reconfigurable molecules Self-assembly is an essential feature for batch processing of molecules for electronic applications. The first works in molecular electronics were based on the fact that thiolterminated molecules self-assemble spontaneously at the surface of noble or near-noble metals (like gold, platinum, mercury etc.) forming compact and ordered monolayers [13]. The ease of this process has made SAMs on preformed contacts of noble or near-noble metals the usual test vehicle to check the potentials of molecular electronics. The possibility of preparing electrically reconfigurable molecules was demonstrated using π -conjugated molecules containing amino or nitro groups [14]. The first demonstrator of non-volatile molecular memories was however prepared employing the crossbar structure functionalized with SAMs of thiol-terminated rotaxanes as reprogrammable cells [15]. The rotaxanes were embedded between the metal layers forming the crossbar via a process, referred to as XB, that can be summarized in the following sequence: XB1 , deposition and definition of the first-level (‘bottom’) noble or near-noble metal wire array; XB2 , deposition of a SAM of rectifying and reconfigurable molecules, functioning also as vertical spacer separating lower and upper arrays; and XB3 , deposition and definition of the second-level (‘top’) metal wire array. Although potentially revolutionary, the XB approach (with two arrays of metal strips) has been found to have serious limits. – The reconfigurable organic molecules are incompatible with high-temperature processing, so that the top layer must be deposited at room or slightly higher temperature. This need implies a preparation based on physical vapour deposition (PVD), where the metallic electrode results from the condensation of metal atoms on the outer surface of the SAM of organic molecules. This process, however, poses severe problems of compatibility, because isolated metal atoms, quite irrespective of their chemical nature, are mobile and decorate the molecules, rather than being held at their outer extremities [16–18]. – A safe determination of the conductance state of bistable molecules requires the application of a voltage V with modulus appreciably larger than kB T /e, with kB being the Boltzmann constant, T the operation temperature and −e the electron charge. Since kB T /e = 25 mV at room

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temperature, a realistic lower limit to |V | is 0.1–0.2 V. Applied to molecules with typical length around 3 nm, this potential generates an electric field, of the order of 5 × 105 V cm−1 , sufficiently high to produce metal electromigration along the molecules [19]. – The energy barrier for metal-to-molecule electron transfer is controlled by the polarity of the contact. In turn, it increases with the electronegativity difference along the bond between metal and molecule. The use of thiol terminations for the molecule, as implicit in the XB approach, is expected to be responsible for high energy barriers, because of the relatively high electronegativity of sulphur. While the first difficulty can in principle be removed by slight sophistication of the process [20], the other difficulties are more fundamental in nature and their solution requires abandoning the shibboleth of SAMs on noble metals. The most natural alternatives to metals are based on conductive carbon (as π -conjugated molecules, carbon nanotubes, graphite or graphene) or heavily doped silicon. The two proposed solutions are both based on heavily doped silicon for the bottom array, while in one the top array is formed by π -conjugated polymers (XB+ process) while in the other by heavily doped silicon (XB∗ process). Although the material properties of π -conjugated materials are still of difficult control, a possible solution to the electromigration problem was achieved by preparing the bottom electrodes in the form of silicon wires (as done in [21]) and the top electrodes in the form conducting π -conjugated polymers (as suggested in [22]). This process, referred to as XB+ , can be summarized in the following sequence: XB1+ , deposition and definition of the bottom array of heavily doped poly-crystalline silicon (poly-Si) wires; XB2+ , deposition of the active (reconfigurable) element, working also as vertical spacer separating bottom and top arrays; and XB3+ , deposition and definition of the top array of conducting π -conjugated polymers. The use of poly-Si as second wire array would certainly render the process more consistent with the CMOS technology. The use of poly-Si as material for the top array too seems however impossible because it is prepared almost exclusively via chemical vapour deposition (CVD) at incompatible temperatures with organic molecules. The only way to overcome the second difficulty consists in a process, XB∗ , where the two heavily doped poly-Si wire arrays defining the crossbar are prepared before the insertion of the organic element. Preserving a constant separation on the nanometre length scale is possible only via the growth of a thin film (working as a sacrificial spacer) on the first array before the deposition of the second one [23, 24]: XB1∗ , preparation of a bottom array of poly-Si wires;

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XB2∗ , growth of a sacrificial layer as vertical spacer separating lower and upper arrays; XB2∗ , preparation of a top array of poly-Si wires crossing the first-floor array; XB4∗ , selective chemical etching of the spacer; and XB5∗ , insertion of the reprogrammable molecules in a way to link upper and lower wires in each cross-point. The basic idea of the process XB∗ is thus based on the insertion of the functional molecules after the preparation of the crossbar [25], that has conceptually opened the interest toward Si–C silicon functionalization not only for application as sensors, but also as switching devices [26–30]. In this way the definition of the memory element just between crossing wires is reminiscent of host–guest chemistry (with cross-point arms as host and functional molecules as guest), although on a different scale. Whichever process one considers, a point is however stressed: the hybrid approach, although still moving in a topdown approach, remains a difficult uphill path, especially in view of the existence of other solutions (the ones considered in the next parts) of much easier integration. The hybrid solution is expected to offer real advantages only if the molecules embed in themselves many more functions than simple change of resistance. Molecules are not the only materials potentially exploitable as reprogrammable elements of crossbars. 3.2 Phase-change materials If the attention is limited to materials able to behave as reprogrammable resistors, the ones that have attracted the largest attention and have now reached the maturity for practical applications are phase-change materials (PCMs) [31]— typically mixed chalcogenides, the most common of which is Ge2 Sb2 Te5 . The PCMs of interest for electronics are characterized by two phases: PCMa (amorphous) with low conductivity and PCMc (crystalline) with much higher conductivity. Moreover, they can be transformed reversibly into one another by suitable heating–cooling cycles [32]: fast heating

PCMc

−→ ←−

fast cooling

PCMa −→ PCMa

slow cooling

In principle, the use of PCMs as memory elements seems simple, provided that one is able to control heating and cooling through an intense Joule heating produced by the passage of a current through the material. Actually, the first demonstrator of PCM memories followed by only two years the discovery of the phenomenon [33]. The first approach to reduce the programming current was the reduction of the contact area. Since the crossbar architecture allows in principle the contact to be reduced to a

diameter of a few nanometres, there is the problem of understanding the scalability limits of PCMs. A physical limit to the scalability of PCMs is related to the minimum size required to transform a localized energy pulse into a hot region. This estimate can be taken from the theory of silicon amorphization: the minimum region required for the thermalization of a localized energy pulse involves 104 atoms. This value is based on the following assumptions: – the thermalization involves the formation of a collisional cascade, involving 2n atoms at stage n; – collisions occur between nearest neighbours; and – the thermalization is completed when the atoms involved in the collisional cascade form a hot spherical cloud. Combining these assumptions, one gets the condition 2n = 4 4 3 3 4 3 πn , which gives n  13 and 3 πn ≈ 10 [34, 35]. A direct consequence of this discussion is the following criterion. Physical design rule 1 Each PCM cell must contain 104 atoms at least. For an atomic density of 5×1022 cm−3 , the PCM cell should thus have a minimum diameter of 6–7 nm. Of course, the dissipated heat diffuses to neighbouring cross-points; this implies a second design criterion: if t is the duration of the heat pulse required for the change slow cooling PCMa −→ PCMc , the size of the region within which the temperature √ is almost uniform (and sufficient for the change) varies as 2κt, where κ is the thermal diffusivity. This implies that all cross-points √ separated by the considered one by a distance lower than 2κt are indistinguishable from it. This discussion provides thus the following criterion. Physical design rule 2 The minimum separation consistent √ with PCM memories is given by 2κt . Of course, thermal conductivity could be drastically reduced by filling the region separating the memory elements with an SiO2 aerogel (that seems technically possible) [36]. Without discussing this point in detail, I tentatively assume that the minimum pitch allowed by PCM is on the length scale of 10 nm. 3.3 Redox materials The functionalization of the cross-point with the insertion of an insulator generates a MIM (metal–insulator–metal) structure. The variety of phenomena that may occur when a potential difference is applied between the metallic plates of MIMs is enormous; a classic, still readable, review is given in [37]. If the MIM structure displays a nonlinear behaviour

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with the applied voltage, it may be viewed as a memristor, a fundamental two-terminal elementary circuit (completing the more familiar family of resistors, capacitors and inductors), characterized by the fact that the current flowing through it depends on the time integral of the applied voltage. The memristor was hypothesized by Chua several years ago [38], but its first practical realization has been claimed only recently, for cross-points functionalized with TiO2 [39]. Limiting to the material, rather than circuital, aspects of the MIM structure, a coarse-grained classification of the reconfigurable materials in the MIM structure is into primarily electrochemical, thermal or ion-migration-induced switching mechanisms. The entire subject is accurately covered in the review by Waser and Aono [40], so that I shall limit my attention to a special case (of materials whose switching mechanism is based on the formation of filamentary conductive paths based on the electrochemical growth and dissolution of metallic filaments) with the aim of exploring which are the scaling possibilities of this structure. For low applied voltage V (say for |V | < VREAD , where VREAD is a characteristic voltage) the MIM structure is nothing but a capacitor (with negligible parasitic current IOFF for |V | < VREAD ). On another side, the cations of several insulators (typically oxides and chalcogenides) undergo cathodic reduction with the formation of filamentary metallic inclusions when the voltage exceeds (in modulus) a characteristic value VWRITE . The length and number of such inclusions increase with the duration of the application of the reduction voltage. The application of such a voltage for a certain time produces thus a configuration where even at low voltage (say VREAD ) there is the passage of a current ION appreciably larger than IOFF , ION  IOFF . If the reduction process is reversible (i.e. if the filamentary metal embedded in the oxide may be reverted to the original state by the application of a positive potential), the material may be used as a two-terminal memory cell [40, 41]. From the fundamental point of view, a cross-point filled with one of such insulators as reconfigurable element behaves as a memory element. At this stage of knowledge, it is difficult to predict which is the lowest limit to which redox cells can be scaled down. Nonetheless, some estimates are possible. For instance, to have an appreciable increase of current, the height h of the newly formed emitting tip must largely exceed the surface roughness σ of the region where it is built; on another side, to avoid shorts, the insulator thickness t must largely exceed h. The following inequality chain must thus be satisfied: σ h t.

(2)

Together with this ‘vertical’ design rule, one should consider also ‘horizontal’ design rules. A physical limit is obtained by

observing that the accumulation of potential energy surfaces responsible for an increase of the electric field at the top of the emitting tip is achieved only if the base of the protruding tip is appreciably smaller than the remaining region hosting it. Assuming that base and height of the protruding region are roughly the same, the feature size f must satisfy the following condition: h f.

(3)

At last, denoting with p the pitch of the structure, the condition for the absence of conduction between neighbouring cross-points is t − h p − f.

(4)

Just to give a qualitative estimate of the minimum pitch achievable using redox materials, assume (quite arbitrarily) that a b means a ≤ 5b. Then observe that even devicequality surfaces of (1 0 0) single-crystalline silicon have a surface roughness of 0.2 nm [42] (smaller values of σ , σ  0.05 nm, have been reported [43, 44], but such values were obtained with processes poorly consistent with crossbar architecture). The first of inequalities (2) thus gives h ≥ 1 nm and its insertion into inequality (3) gives a minimum feature size of 5 nm, f ≥ 5 nm. The second of inequalities (2) gives t ≥ 5 nm and the insertion of the lower limits of t, h and f into (4) gives a minimum pitch of about twice the feature size. With these values, the maximum achievable linear density should be 106 cm−1 . In passing, the above hypotheses allow the energy required to write or erase a bit to be calculated: the protrusion, indeed, is formed by about 102 atoms; if the redox dissipates 1 eV per atom, the energy required and the charge involved would be 1.6 × 102 eV and 2.6 × 10−5 pC, respectively.

4 The crossbar structure The crossbar structure is a matrix of Nx × Ny cross-points formed by an array of Nx wires separated, by a given functional material, from a superimposed array of Ny wires perpendicularly oriented [6–10]; orientation, however, is not critical. From now on, the arrays will be defined as ‘bottom’ and ‘top’, respectively. The functional material in the cross-point can conceptually be scaled to single molecules; the discussion of Sect. 3 applied to this case would give a theoretically achievable density of around 3 × 1012 cm−2 . In this hypothesis, the attainment of the TSI would be related to the ability to prepare wire arrays with linear density δ of around 106 cm−1 . This NW linear density would allow the preparation of crossbars with cross-point density higher by about two orders of magnitude than the current bit density of CMOS integrated circuits (ICs). The producible cross-point density, however, would remain just at the border of TSI.

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The most dense demonstrators of crossbars are not too far from the above limit: the highest linear density of wires presented up to now is 6 × 105 cm−1 , corresponding to a potential cross-point density of 3.6 × 1011 cm−2 [45, 46], whereas the most dense molecular memory hitherto presented had a bit density of 1 × 1011 cm−2 (and complexity of 1 kbit) [21]. The ultimate cross-point density is related to the linear densities of the wire arrays that define it. Nanowires (NWs) may be prepared using lithographic methods: conventional photolithography (henceforth ‘lithography’ without attributes), combined with controlled overetching, allows their cheap production, but the maximum linear density is limited to 105 cm−1 by the achievable pitch P of about 100 nm. Advanced (electron-beam, deep-ultraviolet or extreme-ultraviolet) lithography allows the density limit to be extended by a factor of 5–10, but at a huge production cost, due to investments for deep- or extreme-ultraviolet lithography, or to low throughput for electron-beam lithography.2 However, the simple geometry of the wire arrays allows them to be prepared via much cheaper non-lithographic techniques (NLTs). The general feature of NLTs is based on the transformation of a thickness into a width. This operation is convenient when: (i) the thickness t is controllable on a length scale much smaller than the lithographically producible length scale W ; and (ii) the NLT keeps the width w close to the thickness t of the film. Situation (i) is characteristic of many films, whose thickness is controllable on the nanometre length scale, vs. a lithographic definition on the length scale of 102 nm. From now on, I shall limit myself to situations satisfying both (i) and (ii), for which non-lithographic features are indeed sublithographic features: NLT

t −→ w (w  t W ) , where the sizes of sublithographic features are denoted with lower-case letters, whereas those of lithographically defined features are denoted with the same capital letters. I shall conform to this convention even in the following. It is stressed that techniques for the controlled non-lithographic preparation of features, with width on the 10-nm length scale, are known for a long time [52, 53]; what renders them of interest for the present applications, however, is not simply the width, but rather the pitch. 2 Without pretending to consider economic problems, I recall that the cost of an apparatus for deep-ultraviolet lithography is about 30 M$. The low throughput of electron-beam lithography is due to the fact that this technique defines the pattern in a serial way and the throughput varies with the feature size F roughly as F 4 [51].

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Among the NLTs with this feature, I mention the superlattice nanowire pattern transfer (SNAP) technique that may be used for the preparation of masks for subsequent nanoimprint lithography (NIL), and the multi-sidewall patterning technology (MSPT) that instead requires a preliminary pattern defined lithographically. The SNAP technique is essentially used for the preparation of contact masks for NIL [54, 55]. SNAP masks are typically produced by growing on a single-crystalline substrate a superlattice by molecular-beam epitaxy, cutting the sample perpendicularly to the surface, polishing the newly exposed surface and etching selectively the different strata of the superlattice. For instance, a contact mask with p of 16 nm (and thus with linear density of 6 × 105 cm−1 ) has been reported [46] and SNAP masks were used to demonstrate the feasibility of crossbars hosting reprogrammable molecules as memory elements at a bit density of 1011 cm−2 [21]. The MSPT, instead, is limited to the production of polySi NWs and is essentially based on the repetition (in additive or multiplicative fashion) of the sidewall patterning technique (SPT), an age-old technology originally developed for the dielectric insulation of source-and-drain metal electrodes from the gate of field-effect transistors (FETs), and succeeds in the preparation of wire arrays with p on the 10-nm length scale [56–60]: NWs with width of 7 nm [57] and arrays with p = 35 nm have actually been reported [23, 24]; the most dense crossbar hitherto produced had a bit density of the order of 1010 cm−2 [61, 62].

5 Has the crossbar architecture the potential to replace the CMOS one? For the development of the crossbar architecture (possibly based on NLTs) as an alternative to the current CMOS one, one has to consider that, for an alternative technology to be affirmed, it does not suffice that it is able to produce devices with better performance-to-cost ratio than the current one. Rather, the new technology must attain these results on a shorter time scale than the one of the CMOS technology and must have potentials of growth that the current technology does not have. Denote with Fn and with F not only the feature sizes that characterize the considered and ultimate CMOS nodes, but also the overall technologies themselves (currently Fn = 0.045 µm [63] and F is predicted to be around 10 nm); in the same way, denote with fn and with f the corresponding non-lithographic feature sizes and the corresponding technologies. If (as it seems to be the case) no competitive sublithographic technology is developed before the attainment of the ultimate CMOS technology F , the potential market that can be attacked by sublithographic technologies is that 2 2 of devices with density between 1/4F and 1/4f .

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Since F  1 × 10−6 cm (realistically) and f  5 × cm (optimistically), the potential market of crossbarbased ICs is probably related to devices with density between 2–3 × 1011 cm−2 and 1 × 1012 cm−2 ; most likely this range is too small to deserve the development of a new technology. 10−7

6 Is there indeed a need for UTSI? Irrespective of the material defining the wire, the appearance of quantum effects suggests that the minimum pitch of the wire arrays defining the crossbar can hardly be reduced below 10 nm. This limit follows from the wavelike nature of carriers and from the appearance of quantum size effects. The carrier de Broglie wavelength λ at room temperature, λ ≈ 10 nm, is such that wavelike phenomena (interference, diffraction etc.) are expected to be manifested just in that length scale, thus making poorly distinguishable nearby memory elements and producing direct tunnelling from one wire to adjacent ones. For the same reason, the appearance of quantum size effects requires a control of wire size to fractions of λ. The use of silicon for nanowires makes the shrinkage even more difficult. The silicon bulk properties are totally lost when its minimum size approaches 3 nm, below which silicon becomes a direct-band insulator, with band gap around 1.5 eV [64, 65]. Another important factor limiting the scaling of silicon nanowires is the possibility of doping them to a controlled amount. The ionization energy E ion of dopants in silicon has indeed been reported to vary with the diameter d of the silicon nanowire as ion E ion = E∞ + 2.1E0 a0 /d,

(5)

where 2E0 and a0 are the atomic units of energy and length ion is the dopant ion(E0 = 13.6 eV, a0 = 0.53 Å) and E∞ ization energy in bulk silicon [66]. Freezing of dopants is < ion expected to be a minor effect for 2.1E0 a0 /d ∼ E∞ ; taking ion E∞  60 meV as characteristic of dopants in silicon, (5) would give a lower limit dmin to d of approximately 25 nm, appreciably larger than the hypothesized 5 nm. The combination of all these factors would therefore suggest that the technological effort to reduce size and spacing could not have an adequate counterpart in applications. On another side, in view of the enormous progress in multichip packaging (think simply of portable universal-serialbus flash drives), one might question if the continuous effort toward larger and larger integration makes sense. The answer is however positive. Consider, for instance, the idea of using swarms of nanorobots (each with area of, say, 102 µm2 , comparable with that of a red blood cell) wandering through the circulatory system to provide an auxiliary surveillance system supporting the immune system [67]. Although expected to develop on a time scale of a few decades,

the potential market of such circuits, 1015 nanorobots per year,3 is so large as to justify a strong technological effort in that direction. The tasks of each of them (navigation, recognition, power supply, data transmission etc.) are so numerous and complex to require not less than 1 Mbit. The integration of 106 bits or more in an area of the order of 102 µm2 requires necessarily an UTSI. As discussed above, densities of 106 bits on 102 µm2 or more are however inconsistent with the bit planar arrangement. They necessarily require some form of three-dimensional (3D) integration. In line with what said in the Introduction, however, 3D integration is a realistic route for UTSI only if it is achievable via the planar technology. By the third dimension I intend not only the perpendicular direction to the plane of the circuit, but also any other axis upon which one can allocate different bits at different heights. Voltage is certainly one of them and attempts at coding the memory content with three or four different voltage values are actually known [68]. This elegant development, however, is not free, because it requires a logic for the transformation of information in base 3 or 4 into binary information. What one knows from the history of ICs is that one has to spend in circuit complexity to gain in bit density, as shown by the development of random access memories (RAMs) from static RAMs to dynamic RAMs, or by the progressive replacement of NOR by NAND flash memories. The management of three or more different values of the signal, however, is a difficult task, becoming progressively more difficult with the number of logic levels, so that this route is expected to be able to increase the overall density by a factor of two at most. Much easier is the exploitation of the third spatial dimension. Imagine simply depositing as top wire array a three-layered (metal–dielectric–metal) film, and to define the wires all together. Since each side in crossbar arrays can be functionalized and accessed independently of the other one, its top side can be used as lower array of a second crossbar defined by the deposition of the reprogrammable material and of a third array. The procedure can be reiterated so that the deposition of nz + 1 wire arrays will eventually result in nz crossbars hosted in the same region of the first crossbar. In this way the original bit density (so chosen as not run into the difficulties due to the appearance of quantum effects) is multiplied by a factor of nz . The deposition of 11 wire arrays, on a crossbar with density 1011 cm−2 , could bring the stacked circuit into the TSI realm. Although the stacked crossbars represent certainly a solution to the problem of 3D integration,4 this solution suffers 3 This

estimate follows from assuming the whole mankind as potential consumer, that the swarm is formed by 105 agents and that they have a clearance time of 1 year [67]. 4 Actually also the CMOS technology is characterized, for the preparation of interconnects, by the repetition of the same process. How-

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however from some difficulties: first, even though planarization steps can be inserted between subsequent depositions of wire arrays, the loss of planarity necessarily resulting from the progressive increase of thickness of the stack implies that the array pitch must increase with the order of deposition. Second, and more important, is the fact that the production cost of a circuit with nz crossbars increases with nz + 1, so that if the production cost is essentially due to the core of the circuit, the crossbar, the increase of density is not associated with a corresponding decrease of cost per bit (actually the driving force toward larger and larger integration). In view of the above consideration, a good solution to 3D integration should be based on a process not involving the repetition of advanced-lithography steps. In the following, I shall show that not only are NLTs able to solve in a cost-effective way the problem of 3D integration, but also that they may provide more aggressive architectures than the now conventional 4F 2 .

7 The 2f F architecture Although no theorem stating that the 4F 2 (or 4f 2 ) architecture is the maximum achievable density, there is a widespread consensus on it. Really few works have objected to this opinion [69]. In this section I shall show how it is possible to exploit a few properties of standard IC processing (like selective etching and directional growth) for the preparation of crossbars with 2f F architecture. Consider a multi-layered film (Si3 N4 |SiO2 )N 

 Si3 N4 |SiO2 | Si3 N4 |SiO2 | · · · Si3 N4 |SiO2 |





  1

2

N

= 10 − 102 )

with large N (N and tSi3 N4 tSiO2 (to be more specific, I have in mind values around tSi3 N4 = 1 nm and tSiO2 = 30 nm). Such a film may easily be obtained by chemical vapour deposition (CVD). After protecting this multi-layered film with a thick Si3 N4 layer (with, say, tSi3 N4 = 300 nm), define a mask with width W and length L, with L  W . Using this mask to remove the unprotected Si3 N4 , the process proceeds with a sequence of N cycles so formed: – selective etching of SiO2 , stopping vertically at the underlying Si3 N4 layer and completing with the lateral recession of the remaining film from the original edge by ever, although the complexity of an interconnection layer is presumably much lower than that of a crossbar, the CMOS technology has been involved in the reduction of the number of interconnecting layers via the use of insulators with lower dielectric constant than SiO2 and conductors with higher electrical conductivity than aluminium.

a wanted amount (due to the isotropy of the etch, this amount cannot however be smaller that tSiO2 ); – selective etching of the thin Si3 N4 layer, stopping vertically at the underlying SiO2 layer and completing with a negligible lateral recession of the remaining film from the original edge. Figure 1 sketches six cycles of this sequence. This figure shows that starting from a window of side W the repetition of N cycles generates two ladders each formed by N steps with height (tSi3 N4 + tSiO2 ) and wanted length (however larger than tSiO2 ). A highly directional PVD of a metal film of thickness tw smaller than (tSi3 N4 + tSiO2 ) produces an array of 2n electrically insulated wires running in the direction of the major side L of the original mask. Note that the horizontal separation of these wires is nil, while the vertical separation is (tSi3 N4 + tSiO2 − tw ). For the preparation of a crossbar, the process requires the deposition of the reprogrammable material, of the necessary insulating spacers and of the counter-electrodes. A process involving (i) the directional deposition (PVD) of the insulating layer, (ii) a slight overetching of the metal wires followed by the conformal deposition (CVD) of the electrically reconfigurable material, (iii) the directional etching of this layer (in an SPT fashion) leaving a lateral spacer (see again the sketch in Fig. 1), (iv) the conformal deposition (CVD) of the second metal layer and (v) the definition of the top wire array, might be used for that. Simplifications are possible: for instance, if the functional material is stable at high temperature, tolerates heat treatment in O2 and the wire material oxidizes forming a passivating oxide, the spacer may simply be formed by heat treatment in O2 . It is noted that if f is the minimum feature size allowed by this technique (f  tSiO2 ), the 2N electrically insulated wires hold in the plane a region extending by W + 2Nf : the pitch is just f , although a mean amount W/2N per wire is lost for the definition of the original geometry. Crossing this array, with a conventional upper array where upper wires have a pitch of 2F , produces thus a crossbar with crosspoint occupation area 2f F (1 + W/2f N ) (that behaves as 2f F for large n). This occupation is better by a factor of two than that allowed by the standard crossbar structure—a seemingly impossible result. Of course, the use of NLTs for the production of the top array would result in cross-points with mean occupied area of 2f 2 (1 + W/2f N ). An obvious criticism to this process is that the underetching producing the recessed region below each Si3 N4 mask does not produce a rectangular shape, but rather a smooth geometry. This difficulty can however be circumvented by exploiting the strong dependence of the silica etch rate on phosphorus doping [70] and grading this doping to have a rectangularly shaped underetching.

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8 An even more aggressive architecture Although the technique I am going to describe is very recent, it finds its roots in the invention of the silicon-gate technology.5 The first applications of the silicon-gate technology were based on an Si3 N4 –SiO2 bilayer as gate insulator [72], the function of the bottom Si3 N4 layer being of tolerating the HFaq etching without formation of deep recessed regions below the gate. The Si3 N4 layer became useless (and was eventually removed) after the introduction of a re-oxidation step after the formation of source and drain. The idea of exploiting the recessed region as a host with parallel-plate geometry, for self-assembling therein functional molecules, was proposed in [25]; its use as a template for the formation of nanowires was instead proposed in [74]. In that paper it was shown that poly-Si nanowires can be arranged in vertical arrays with pitch around 50 nm, and the vertical arrays can be arranged with lithographic horizontal separation exploiting techniques for the controlled etching and filling of the recessed regions resulting from conventional IC processing. 8.1 The basic idea The process starts with the formation of a multi-layered film of insulators A and B over a suitable insulating substrate C as sketched in the following: 1

2

N

      C|| A|B| A|B| · · · A|B| 

tN

(6)

=N (t A +t B )

The materials are characterized by the existence of a selective etch of A with respect to B; C may coincide with A or B. To be concrete, I shall think of A as SiO2 , of B as Si3 N4 and of C as a thick SiO2 layer (the ‘preferred embodiment’) and specialize the following description to these materials.

Fig. 1 The sequence involving selective etching of SiO2 and Si3 N4 (steps 1–7, left to right), directional PVD of the bottom wire array (step 8), the conformal deposition of the reprogrammable material followed by its directional etching and the directional deposition of a passivating layer

5 The progress of electronics is paced not only by the continuous improvements of its basic technology (lithography) that have reduced the feature size from the submillimetre length scale to the deep- submicrometre one, but also (and at the beginning mainly) by the invention of techniques for the self-alignment of one layer with respect to another. Among them the most important ones are the spacer-patterning technique (for the self-alignment of contacts with respect to the gate), local oxidation of silicon (for the self-alignment of active zones with respect to the field) and silicon-gate technology (for the self-alignment of source and drain with respect to the gate). History is sparing of compliments to scientists, and even more to technologists: although everybody of the one hundred thousand researchers involved in silicon-device processing is familiar with the silicon-gate technology, the paper reporting its invention in 1968 [71] and the one describing its practical application one year later [72] have had, according to the Institute of Scientific Information, 112 and 42 quotations only [73].

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G.F. Cerofolini

Fig. 2 Cross sections (left) and plan views (right) of the structures resulting in the preparation of the vertical wire arrays

The thicknesses of SiO2 and Si3 N4 are not critical; however, for reasons of concreteness, I shall fix them to be t SiO2 = 30 nm and t Si3 N4 = 20 nm, respectively. This choice will eventually result in poly-Si NWs with thickness around 30 nm; this thickness is sufficiently high as to preserve the physical properties of poly-Si as well as not to stress the technology. The number N of bilayers forming the film is such as to allow the formation by directional etching (e.g. via reactive ion etching, RIE) of a deep trench with depth tN = N(t SiO2 + t Si3 N4 ). The overall process, sketched in Fig. 2a–g, involves the following steps: (a) the sequential deposition of N SiO2 –Si3 N4 bilayers; (b) the definition thereon of a deep trench; (c) the formation of N recessed regions per trench side by partial selective etching of the SiO2 layers; (d) the conformal deposition of a doped poly-Si film of thickness appreciably larger than the one required for the complete filling of the recessed regions; (e) the partial selective etching of the film for the duration required to etch silicon from the horizontal regions; (f) the conformal deposition of the functional material and its directional etching (or, for applications in molecular electronics, the re-oxidation of the resulting silicon wires with formation of a sacrificial spacer to the second wire array [9, 20]); and (g) the conformal deposition of another poly-Si film and its definition with the formation of a second wire array. 8.2 Proof of the idea The idea was proved for N = 4; the difficulties of scaling to much larger N arise due to the accumulated stress, essentially due to Si3 N4 ; this stress can however be reduced by

intermittent depositions of relatively thick stress-relieving SiO2 layers. The structure was found producible for all widths W in the explored interval 0.2–100 µm, and the minimum useful width Wmin is expected to be controlled by the possibility of hosting two dielectrically insulated wires (actually the width 0.2 µm was produced using a poly-Si hard mask defined by a sidewall patterning technique [75]). The detailed process and the electrical characterization of the poly-Si nanowires, showing that they are already ready for UTSI application, are given in [75]. A flavour of the structures actually achievable at stages (b), (c) and (g) is obtained by inspecting the images (obtained by scanning electron microscopy, SEM) shown in Fig. 3. 8.3 Density limits If the directional etch in (b) produced truly vertical sidewalls, the NW linear density would indeed be limited by the trench depth alone. Due to the fact that the RIE results in trenches with finite aspect ratio, the producible density is limited even for N → +∞. It is thus reasonable to ask which density limits can be achieved via the described technique. To calculate the maximum achievable density, one must first consider the incomplete anisotropy of the RIE. The loss of verticality poses indeed a limit to the maximum achievable wire density. Of course, since the top array is built on a strongly non-planar structure one has to consider two different aspect ratios: one, R  , resulting from the definition of the multi-layered SiO2 –Si3 N4 stack (via SiO2 chemistry) and the other, R, resulting from the definition of the poly-Si top layer. To simplify the discussion, the actual trench shape is approximated by the rectilinear one shown in Fig. 4. Moreover,

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Fig. 4 Geometrical parameters defining the trench

definition of a bottom wire density with pitch projected on the plane of p∗ given by p⊥ b , +  R 2N whereas, for the top array, one has

Fig. 3 SEM cross sections of the structures resulting after steps (b), (c) and (g). The complicated structure of the top-level poly-Si nanowire in the recessed region below the first bottom-level poly-Si nanowire might impact the crossbar function but could be removed by substituting Si3 N4 for SiO2 as substrate

one has to consider that the bottom array has a vertical organization, with pitch p⊥ , whereas the top array has a horizontal organization, with pitch p . Before discussing in detail the density limits, I will spend a few words commenting on symbols. A few quantities (like the pitch p of the pattern that can be defined along the surface or the aspect ratio R) are characteristic of both the bottom and top arrays, although they may take different values in the two situations. To avoid confusion, apices ‘ ’ or ‘ ’ will be used to denote that the primed quantity refers to the bottom or top array, respectively. If p  and p  are the pitches in the bottom and top arrays, the area involved in one cross-point is just p  × p  . For a planar arrangement, the area f 2 actually held by a cross-point is approximately 14 of that value (the apparent ‘theoretical limit’ of the fully planar technology); this property does not extend to crossbars with the 3D organization considered in this work. Rather, one has to consider that the vertical organization allows the

p∗ =

(7)

p  = p + 2t  /R  ,

(8)

where t  is the thickness of the planarizing film and R  is the aspect ratio of this film after the definition of the pattern; R  is a property of the process and of the planarizing material, whereas t  cannot be lower than the thickness Np⊥ of the stack. To simplify the discussion, I shall however limit myself to consider the case R  = R  = R. In this case, the combination of (7) and (8) gives



p⊥ b 2p⊥ N + p + p∗ × p  = 2N R R =

2N bp p⊥ (b + p ) 2p⊥ + + . 2N R R2

(9)

Equation (9) shows that the projected area p∗ ×p  decreases steadily with R while it increases steadily with p , p⊥ and b: the minimum of p∗ × p  is thus obtained by setting the technology to the maximum of R and the minima of b, p and p⊥ . Of these minima I comment only the one of b that, according to [74], is given by b = 3t A + t B = p⊥ + 2t A .

(10)

Fixing these values, the extremum of p∗ × p  with respect to the number N of bilayers forming the stack is obtained when ∂(p∗ × p  )/∂N = 0, i.e. for  R bp . (11) N= 2 2 p⊥

978

The occupied area is obtained by inserting (11):

1 2 p∗ × p  = p⊥ (b + p ) + (bp )1/2 . R 2

G.F. Cerofolini

(12)

8.4 Memory element Since the increase of density associated with the vertical organization is not prevailingly due to a decrease of size of the cross-point, the memory element may remain the same as in the standard planar technology. The major difficulty is essentially related to the deposition technology that requires a deposition in recessed regions. The very fact that good ohmic contacts could be prepared by PVD even in vertically arranged wires [75] suggests that analogous equipment can be used for the deposition of memory materials, too. 8.5 Addressing Up to now, the attention of this work has essentially been focused on density. On another side, density is not the only parameter of interest for electronics: the problem of linking the nanoworld to the macroworld represents a central issue in the development of nanotechnology [47]. Although stochastic methods for linking the nanoworld to lithographically accessible contacts (in a way mimicking a bottom-up organization) have been developed [48–50], they are extraneous, if not totally orthogonal, to the CMOS technology. Rather, this problem is manifestly better attacked in a topdown approach [2, 9, 77–84]. The use of the crossbar as a memory requires that each cross-point is externally accessible. Of course, this requires the ability of demultiplexing the Nx + Ny wires. If the wires have sublithographic pitch, their demultiplexing can be done either using links to the addressing circuitry defined with advanced lithography, or exploiting tricks able to separate sublithographically close wires into lithographically separable contacts. Tricks for doing that task are known [2, 9, 20]. Although they unavoidably imply some loss of area (see Fig. 5), one of them, first formulated in [2] and experimentally proved in [61, 62], requires an addressing circuitry of minimum complexity. 8.5.1 Addressing the top array Since in the top array the wires run on a plane parallel to the surface, any of the methods proposed for their deterministic demultiplexing [2, 9, 84] can be used. 8.5.2 Addressing the bottom array None of the methods hitherto proposed can be used for the demultiplexing of vertically arranged nanowire arrays: the

Fig. 5 Comparison of addressing strategies involving advanced lithography (top) or tricks for the lithographic demultiplexing of sublithographic wire arrays (bottom). The NLT trick adopted for demultiplexing has been shown for word lines only; for bit lines the strategy is the same

full exploitation of this technology would thus require the development of a new demultiplexing method. Although at this stage I have not yet a detailed process for that, I have however defined a process strategy. With reference to Fig. 6 the nano-to-litho link would be possible if one were able to cut the stack with a plane crossing the surface at an angle from the normal close to 90◦ . This cut could be produced using an attack etching the layer at faster rate along, rather than perpendicularly to, the surface. For that, it would be sufficient to implant the unprotected layer with phosphorus at high dose choosing energies and fluences in such a way to have a concentration of phosphorus and of radiation damage increasing with the depth from the surface and to exploit the strong dependence of the etch rate on concentration of phosphorus [70] or of radiation damage [85]. Transforming this process scheme into an actual process seems possible, though it likely involves accurate tuning.

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Fig. 6 Side (top) and plan (bottom) views sketching the structure for the demultiplexing of vertical arrays of nanowires

Of course, the method produces a pattern of contacts holding a relatively large area. It is however noted that the size of the contact region (which can be reduced, by accurate tuning of the angle, to the area of the contact region sketched at the bottom of Fig. 5) impacts the overall crosspoint density by an amount that decreases steadily with the cave aspect ratio.

9 Adding new functions—coils, solenoids and transformers In the gargantuan and tumultuous development of microelectronics the attention has been mainly concentrated on active elements and interconnects; passive elements (resistors, capacitors, inductors and memristors) have been poorly considered: although memristors were proposed in 1971 [38], they have been the focus of attention only recently [39, 86] (that makes difficult the prediction of their role in future nanotechnology). Capacitors, instead, after the silicon-gate technology have been of easy integration and similarly resistors after the widespread use of ion implantation—they have never been a bottleneck for the development of the silicon technology. Inductors, instead, have been largely ignored essentially because of the difficulty of their integration in the silicon technology [87]. This fact is particularly disappointing not only because their availability would make easier voltage transformation, but also because it could allow the development of nanoscale magnetic sensors of large potential interest [88–91]. Remarkably enough, the vertical organization of the nanowires combined with their demultiplexing technique allows the preparation of solenoids with size on the submicron length scale. For that, it is sufficient to design the original mask and to process the devices as sketched in Fig. 7. This procedure allows the seed to be cut at low angle. At

Fig. 7 Masks defining the seed of the nanowires (top) and protecting them from ion implantation (middle) and from the subsequent etch (bottom)

this stage, rather than contacting each end of the nanowires independently of one another as sketched in Fig. 6), the solenoid is prepared by connecting the left-hand side of the nth nanowire to the right-hand side of the (n + 1)th, as sketched at the bottom of Fig. 8. The preparation of the transformer requires two solenoids in the same stack. This arrangement is easily obtained by defining the seed as shown in Fig. 9, observing that the process results in the same number of contacts for inner and outer coils and that the voltage transformation ratio is determined by the number of connected wires and the relative areas of inner and outer solenoids. The magnetic field BM generated by a macroscopic solenoid is given by BM = μ0 μr I /P ,

(13)

980

Fig. 8 Mask defining the metal interconnects of the nanowires to produce a solenoid (grey)

G.F. Cerofolini

macroscale) scales to r = ρM /a = (ρn /ρM )k, with ρn being the resistivity of the nanoscale conductor. Assuming that the macroscopic voltage V is applied to the nanoscale solenoid, too (that is possible only if it is smaller than the breakdown voltage), the magnetic field scales from BM = μ0 μr AV /ρM LP to Bn = μ0 μr aV / ρn p = (ρn /ρM )BM . In other words, for this kind of scaling, geometry does not matter and the magnetic field at the nanoscale is controlled by the wire conductivity. Taking into account that the conductivity of heavily doped poly-Si is smaller than that of good metal conductors by approximately three orders of magnitude, one would arrive to the quite disappointing conclusion that a magnetic field of, say, 1 T is reduced to 10−3 T on going to the nanoscale. The standard silicon technology, however, contains in itself the tool for overcoming part of the above difficulty. For that, imagine that, after filling the recessed region with polySi, most of it is etched away by time-controlled oxidation, leaving in the cavity only a very thin pad. This pad may then be used as a seed for the deposition of a tungsten plug from WF6 precursor with the same process adopted to form the vias for multi-layer metallization of ICs. Assuming that this process succeeds indeed in the formation of metallic wires in the recessed regions, scaling at constant voltage would produce a current therein sustaining approximately the same magnetic field as in the macroscopic solenoid. In this situation the magnetic energy per unit volume in the nanosized solenoid is the same as in the macroscopic one. It is however noted that scaling at constant voltage is possible only if the resulting electric field is smaller than the breakdown voltage of the dielectric stack. For a solenoid of length 1 µm, the maximum operating voltage should be smaller than 102 V.

Fig. 9 Mask defining the seed for the preparation of transformers

where μ0 is the magnetic constant (μ0 = 4π × 10−7 T m/A), μr is the relative permeability of the medium, P = L/N , N is the number of loops forming the solenoid, L is its length and I is the current flowing through it. This equation determines the scaling rules allowing the design of a nanoscale solenoid when a macroscopic one is known. Assume that the macroscopic solenoid is reduced to the nanoscale scaling all the sizes by the same factor k (k  1); in this case one has P → p = P /k, L → l = L/k, L →  = L/k, A → a = A/k 2 , so that the resistance R of the macroscopic solenoid (R = ρM L/A, with ρM being the resistivity of the wire on the

10 Conclusions A new technology, based on the controlled etching and filling of recessed regions, formed during meticulous processing of multi-layered structures, has been demonstrated to be able to open a door to TSI thanks to the vertical arrangement of cross-points in crossbar structures, and to the conjugation of magnetic components (coils, solenoids and transformers) with the standard CMOS platform. Combining density and complexity, an IC may be considered to have TSI when its bit density in zones of repetitive logic is of the order of 1012 cm−2 and contains more than 109 transistors. The core of current ICs, the FET, is scalable to a gate length F of 10 nm; the FET arrangement in 4F 2 architecture could thus produce a density of 2.5 × 1011 cm−2 . Not only is this density marginally consistent with TSI, but is expectedly producible only thanks to a massive use of

Realistic limits to computation

advanced (deep-ultraviolet, extreme-ultraviolet or electronbeam) lithography. If a technology is intended to be a set of techniques for the reproducible and large-volume production of goods, the extension of current silicon production techniques to the 10-nm length scale suffers the risk of failing as a technology because of the dramatic increase of lithography cost-ofownership. On the contrary, there is an increasing confidence that non-lithographic production techniques have TSI in their line of fire, at least resting at titles of recent papers like ‘Prospects for terabit-scale nanoelectronic memories’ (2005) [79], ‘A 160-kilobit molecular electronic memory patterned at 1011 bits per square centimetre’ (2007) [21], ‘Threedimensional crossbars with tera-scale integration produced via top-down planar technology’ (2010) [74] or ‘Crossbar architecture for tera-scale integration’ (2011) [76]. These and other works on the same subject suggest that nonlithographic techniques for the production of nanowires and their demultiplexing can be arranged, possibly in hybrid combination with reprogrammable molecules, to define a suitable technology for UTSI. In particular in this work I have demonstrated that vertically arranged nanowire arrays can be fabricated with linear density in large excess to 106 cm−1 in a rigorous topdown approach and employing conventional IC processes, although in a non-conventional fashion. The demonstration of the feasibility of the process was carried out in an academic facility. Its transfer to IC production plants should ultimately be suitable for the production of vertical nanocrossbars for ICs of TSI complexity.

References 1. 2. 3. 4.

5. 6. 7. 8. 9. 10. 11. 12.

13.

G.F. Cerofolini, Appl. Phys. A 86, 23 (2007) G.F. Cerofolini, Appl. Phys. A 86, 31 (2007) R.P. Feynman, Eng. Sci. 23(5), 22 (1960) E. Bussola, What is a memory, that it may comprehend itself? in Memory Mass Storage, ed. by G. Campardo, F. Tiziani, M. Iaculo (Springer, Berlin, 2011), pp. 1–58 E. Drexler, Nanosystems—Molecular Machines, Manufacturing and Computation (Wiley, New York, 1992) J.R. Heath, P.J. Kuekes, G.S. Snider, R.S. Williams, Science 280, 1716 (1998) M. Forshaw, R. Stadle, D. Crawley, K. Nikoli´c, Nanotechnology 15, S220 (2004) G.S. Snider, R.S. Williams, Nanotechnology 18, 035204 (2007) G.F. Cerofolini, E. Romano, Appl. Phys. A 91, 181 (2008) G. Csaba, P. Lugli, IEEE Trans. Nanotechnol. 8, 369 (2009) G.F. Cerofolini, D. Mascolo, Semicond. Sci. Technol. 21, 1315 (2006) G.F. Cerofolini, V. Casuscelli, A. Cimmino, A. Di Matteo, V. Di Palma, D. Mascolo, E. Romanelli, M.V. Volpe, E. Romano, Semicond. Sci. Technol. 22, 1053 (2007) J.C. Love, L.A. Estroff, J.K. Kriebel, R.G. Nu, G.M. Whitesides, Chem. Rev. 105, 1103 (2005)

981 14. M.A. Reed, J. Chen, A.M. Rawlett, D.W. Price, J.M. Tour, Appl. Phys. Lett. 78, 3735 (2001) 15. Y. Luo, C.P. Collier, J.O. Jeppesen, K.A. Nielsen, E. Delonno, G. Ho, J. Perkins, H.-R. Tseng, T. Yamamoto, J.F. Stoddart, J.R. Heath, Chem. Phys. Chem. 3, 519 (2002) 16. R.F. Service, Science 302, 556 (2003) 17. D.R. Stewart, D.A.A. Ohlberg, P. Beck, Y. Chen, R.S. Williams, J.O. Jeppesen, K.A. Nielsen, J.F. Stoddart, Nano Lett. 4, 133 (2004) 18. C.N. Lau, D.R. Stewart, R.S. Williams, D. Bockrath, Nano Lett. 4, 569 (2004) 19. N.B. Zhitenev, W. Jiang, A. Erbe, Z. Bao, E. Garfunkel, D.M. Tennant, R.A. Cirelli, Nanotechnology 17, 1272 (2006) 20. G.F. Cerofolini, Nanoscale Devices. Fabrication, Functionalization, and Accessibility from the Macroscopic World (Springer, Berlin, 2009) 21. J.E. Green, J.W. Choi, A. Boukai, Y. Bunimovich, E. JohnstonHalperin, E. Delonno, Y. Luo, B.A. Sheriff, K. Xu, Y.S. Shin, H.R. Tseng, J.F. Stoddart, J.R. Heath, Nature 445, 414 (2007) 22. H.B. Akkerman, P.W.M. Blom, D.M. de Leeuw, B. de Boer, Nature 441, 69 (2006) 23. G.F. Cerofolini, G. Arena, M. Camalleri, C. Galati, S. Reina, L. Renna, D. Mascolo, V. Nosik, Microelectron. Eng. 81, 405 (2005) 24. G.F. Cerofolini, G. Arena, M. Camalleri, C. Galati, S. Reina, L. Renna, D. Mascolo, Nanotechnology 16, 1040 (2005) 25. G.F. Cerofolini, G. Ferla, J. Nanopart. Res. 4, 185 (2002) 26. G.F. Cerofolini, C. Galati, S. Reina, L. Renna, Semicond. Sci. Technol. 18, 423 (2003) 27. M.P. Stewart, F. Maya, D.V. Kosynkin, S.M. Dirk, J.J. Stapleton, C.L. McGuiness, D.L. Allara, J.M. Tour, J. Am. Chem. Soc. 126, 370 (2004) 28. G.F. Cerofolini, C. Galati, S. Reina, L. Renna, G.G. Condorelli, I.L. Fragalà, G. Giorgi, A. Sgamellotti, N. Re, Appl. Surf. Sci. 246, 52 (2005) 29. T. He, J. He, M. Lu, B. Chen, H. Pang, W.F. Reus, W.M. Nolte, D.P. Nackashi, P.D. Franzon, J.M. Tour, J. Am. Chem. Soc. 128, 14537 (2006) 30. M.Y. Bashouti, R.T. Tung, H. Haick, Small 23, 2761 (2009) 31. G.W. Burr, M.J. Breitwisch, M. Franceschini, D. Garetto, K. Gopalakrishnan, B. Jackson, B. Kurdi, C. Lam, L.A. Lastras, A. Padilla, B. Rajendran, S. Raoux, R.S. Shenoy, J. Vac. Sci. Technol. B 28, 223 (2010) 32. S.R. Ovshinsky, Phys. Rev. Lett. 21, 1450 (1968) 33. R.G. Neale, D.L. Nelson, G.E. Moore, Electronics 49(9), 56 (1970) 34. G.F. Cerofolini, L. Meda, Phys. Rev. B 36, 5131 (1987) 35. G.F. Cerofolini, L. Meda, C. Volpones, J. Appl. Phys. 63, 4911 (1988) 36. A.C. Pierre, G.M. Pajonk, Chem. Rev. 102, 4243 (2002) 37. G. Dearnaley, A.M. Stoneham, D.V. Morgan, Rep. Prog. Phys. 33, 1129 (1970) 38. L. Chua, IEEE Trans. Circuit Theory CT-18, 507 (1971) 39. D.B. Strukov, G.S. Snider, D.R. Stewart, S.R. Williams, Nature 453, 80 (2008) 40. R. Waser, M. Aono, Nat. Mater. 6, 833 (2007) 41. R. Waser, R. Dittmann, G. Staikov, K. Szot, Adv. Mater. 21, 2632 (2009) 42. G.F. Cerofolini, A. Giussani, A. Modelli, D. Mascolo, D. Ruggiero, D. Narducci, E. Romano, Appl. Surf. Sci. 254, 5781 (2008) 43. G.F. Cerofolini, C. Galati, L. Renna, Surf. Interface Anal. 35, 968 (2003) 44. G.F. Cerofolini, C. Galati, S. Lorenti, L. Renna, O. Viscuso, C. Bongiorno, V. Raineri, C. Spinella, G.G. Condorelli, I.L. Fragala, A. Terrasi, Appl. Phys. A 77, 403 (2003) 45. R. Beckman, E. Johnston-Halperin, Y. Luo, J.E. Green, J.R. Heath, Science 310, 465 (2005)

982 46. N.A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, J.R. Heath, Science 300, 112 (2003) 47. M. Roukes, Sci. Am. Rep. 17(3), 4 (2007) 48. Y. Huang, X. Duan, Q. Wei, C.M. Lieber, Science 291, 630 (2001) 49. Y. Huang, X. Duan, Y. Cui, L.J. Lauhon, K.-H. Kim, C.M. Lieber, Science 294, 1313 (2001) 50. Z. Zhong, D. Wang, Y. Cui, M.W. Bockrath, C.M. Lieber, Science 302, 1377 (2003) 51. A.E. Grigorescu, C.W. Hagen, Nanotechnology 20, 292001 (2009) 52. D.C. Flanders, A.E. White, J. Vac. Sci. Technol. B 19, 692 (1981) 53. G.A. Garfunkel, M.B. Weissman, J. Vac. Sci. Technol. B 8, 1087 (1990) 54. D. Wang, B.A. Sheriff, M. McAlpine, J.R. Heath, Nano Res. 1, 9 (2008) 55. J.R. Heath, Acc. Chem. Res. 41, 1609 (2008) 56. D.C. Flanders, N.N. Efremow, J. Vac. Sci. Technol. B 1, 1105 (1983) 57. Y.-K. Choi, J. Zhu, J. Grunes, J. Bokor, G.A. Somorjai, J. Phys. Chem. B 107, 3340 (2003) 58. Y.-K. Choi, J.S. Lee, J. Zhu, G.A. Somorjai, L.P. Lee, J. Bokor, J. Vac. Sci. Technol. B 21, 2951 (2003) 59. G.F. Cerofolini, P. Amato, E. Romano, Semicond. Sci. Technol. 23, 075020 (2008) 60. Y. Zhao, E. Berenschot, H. Jansen, N. Tas, J. Huskens, M. Elwenspoek, Nanotechnology 20, 315305 (2009) 61. M.H. Ben Jamaa, G. Cerofolini, G. De Micheli, Y. Leblebici, Complete nanowire crossbar framework optimized for the multispacer patterning technique, in Int. Conf. Compilers, Architecture and Synthesis for Embedded Systems—CASES 2009 (2009), pp. 11–16 62. M.H. Ben Jaama, G. Cerofolini, G. De Micheli, Y. Leblebici, IEEE Trans. Nanotechnol. 10, 891 (2011) 63. L. Chao (ed.), Intel Technol. J. 12, 77 (2008) 64. L.T. Canham, Appl. Phys. Lett. 57, 1046 (1990) 65. L.T. Canham, Nature 408, 411 (2000) 66. V. Schmidt, J.V. Wittemann, U. Gösele, Chem. Rev. 110, 361 (2010) 67. G.F. Cerofolini, P. Amato, M. Masserini, G. Mauri, Adv. Sci. Lett. 3, 345 (2010) 68. P. Horowitz, W. Hill, The Art of Electronics, 2nd edn. (Cambridge University Press, Cambridge, 1989) 69. I.S. Kim, S.L. Cho, D.H. Im, E.H. Cho, D.H. Kim, G.H. Oh, D.H. Ahn, S.O. Park, S.W. Nam, J.T. Moon, C.H. Chung, High performance PRAM cell scalable to sub-20 nm technology with below 4F 2 cell size, extendable to DRAM applications, in 2010 Symp. VLSI Technology (2010), Digest of Technical Papers, pp. 203–204

G.F. Cerofolini 70. M.L. Polignano, P. Picco, G.F. Cerofolini, J. Electrochem. Soc. 127, 2734 (1980) 71. F. Faggin, T. Klein, Solid-State Electron. 13, 1125 (1970) extended version of work presented by F. Faggin, T. Klein, L. Vadasz, in Int. Electron Devices Meet., Washington, DC, October 1968 72. L.L. Vadasz, A.S. Grove, T.A. Rowe, G.E. Moore, IEEE Spectr. 6(10), 28 (1969) 73. http://isiwebofknowledge.com/. Accessed on 5 October 2010 74. G.F. Cerofolini, M. Ferri, E. Romano, F. Suriano, G.P. Veronese, S. Solmi, D. Narducci, Semicond. Sci. Technol. 25, 095011 (2010) 75. M. Ferri, A. Roncaglia, S. Solmi, F. Suriano, G.F. Cerofolini, E. Romano, D. Narducci, Microelectron. Eng. 88, 877 (2011) 76. G.F. Cerofolini, M. Ferri, E. Romano, F. Suriano, G.P. Veronese, S. Solmi, D. Narducci, Semicond. Sci. Technol. 26, 045005 (2011) 77. K.K. Likharev, Electronics below 10 nm, in Nano and Giga Challenges in Microelectronics, ed. by J. Greer, A. Korkin, J. Labanowsky (Amsterdam, Elsevier, 2003), pp. 27–68 78. K.K. Likharev, D.B. Strukov, CMOL: Devices, circuits, and architectures, in Introducing Molecular Electronics, ed. by G. Cuniberti, G. Fagas, K. Richter (Springer, Berlin, 2005), pp. 447–477. Chap. 16 79. D.B. Strukov, K.K. Likharev, Nanotechnology 16, 137 (2005) 80. D.B. Strukov, K.K. Likharev, Nanotechnology 16, 888 (2005) 81. K.K. Likharev, J. Nanoelectron. Optoelectron. 3, 203 (2008) 82. K.K. Likharev, Sci. Adv. Mater. 3, 322 (2011) 83. D.B. Strukov, R.S. Williams, Proc. Natl. Acad. Sci. USA 106, 20155 (2009) 84. G. Cerofolini, E. Romano, D. Narducci, The litho-to-nano link, in Dekker Encyclopedia of Nanoscience and Nanotechnology, 2nd edn., ed. by J.A. Schwarz, C.I. Contescu, K. Putyera (Dekker, New York, 2009), pp. 1890–1900 85. M.Q. Huda, K. Sakamoto, Nucl. Instrum. Methods Phys. Res. B 216, 20 (2004) 86. J. Borghetti, G.S. Snider, P.J. Kuekes, J.J. Yang, D.R. Stewart, R.S. Williams, Nature 464, 873 (2010) 87. A. Zolfaghari, A. Chan, B. Razavi, IEEE J. Solid-State Circuits 36, 620 (2001) 88. L. Ciobanu, D.A. Jayawickrama, X. Zhang, A.G. Webb, J.V. Sweedler, Angew. Chem., Int. Ed. Engl. 42, 4669 (2003) 89. J.W. Sweedler, R.L. Magin, T.L. Pack, A.G. Webb, Microcoil based micro-NMR spectrometer and method, US Patent 6,788,061, 7 Sept. 2004 90. A.G. Goloshevsky, J.H. Walton, M.V. Shutov, J.S. de Ropp, S.D. Collins, M.J. McCarthy, Rev. Sci. Instrum. 76, 024101 (2005) 91. M. Poggio, C.L. Degen, Nanotechnology 21, 342001 (2010)