Analog Integr Circ Sig Process DOI 10.1007/s10470-015-0591-2

A 10 bit 16-to-26 MS/s flexible window SAR ADC for digitally controlled DC–DC converters in 28 nm CMOS Stefan Haenzsche1 • Sebastian Ho¨ppner1 • Rene Schu¨ffny1

Received: 22 January 2015 / Revised: 13 March 2015 / Accepted: 18 June 2015 Ó Springer Science+Business Media New York 2015

Abstract This paper presents a 10 bit charge redistribution successive approximation analog-to-digital converter (ADC) for integrated digitally controlled DC–DC converters. A timing efficient implementation of a window function is proposed, where only a reduced input range is converted. A redundant search is applied to overcome the speed limitation of the analog components. The window mode enables further speed enhancement without an increase of clock frequency and power consumption. Position of the set-point and size of the window is digitally adjustable every conversion. Fabricated in 28 nm low-power CMOS technology the ADC occupies only 110 9 85 lm2. In full range mode a conversion rate of 16 MS/s is achieved and in window mode 26.7 MS/s, respectively. With a measured total power consumption of 710 lW and 9.1 bit ENOB a FOM of 81 fJ/conv-step is reached. A large input range with constant resolution, highly linear characteristic, and high robustness to PVT variations together make this ADC an advantageous alternative to delay line or ring oscillator based window ADCs. The highly digital nature of the proposed architecture allows implementation in modern sub-100 nm CMOS technologies. Keywords Analog-to-digital conversion  ADC  Successive approximation  SAR  Non-binary  Redundant search  Window function  DC–DC converter

& Stefan Haenzsche [email protected] 1

Institute of Circuits and Systems, Technische Universita¨t Dresden, 01069 Dresden, Germany

1 Introduction Energy efficient power management systems demand for on-chip DC–DC converters. Integrated solutions require low-power ADCs, compatible with modern sub-100 nm CMOS technologies. The classical architecture of a DC– DC converter applies a window or tracking ADC, that measures only a window around a given set-point, since the regulated output voltage remains in a expected narrow range during the settled state. For dynamic voltage scaling (DVS) the position of the quantization window has to be adjustable corresponding to the requested output voltage. A monotonic characteristic with fixed LSB size, independent of the set-point, ensures stability of the control loop. Low power consumption, scalable by sample rate and resolution, is required to ensure good energy efficiency of the complete system. The established solutions of digitally controlled DC– DC converters apply flash or pipeline ADCs achieving high sample rates at medium resolution [1]. Main disadvantage of flash ADCs is their high power consumption, which increases exponentially with the resolution. Pipeline and cyclic ADCs require high gain operational amplifiers and dissipate much power. Furthermore, their performance degrade with technology scaling and low supply voltage [2]. New architectures like delay-line or ring-oscillator based ADCs have been proposed recently [3]. But due to non-linear delay effects a constant resolution is only achieved in a small input range [4]. Additionally, their performance depends non-linearly on temperature and supply voltage, thus calibration is required. SAR ADCs reach the highest energy efficiency among all ADC architectures, due to the minimal amount of active circuitry [2], and resolutions up to 12 bit are achieved without calibration. The highly digital nature of SAR

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Fig. 1 Block level schematic of a conventional window ADC

ADCs allows implementation in modern CMOS technologies [5, 6] and flexible scaling of resolution and conversion rate [7]. Figure 1 illustrates the block level schematic of a classical window ADC, consisting of a set-point DAC to generate the reference voltage, an amplifier for error signal amplification and common-mode shift, and a flash or pipeline ADC with reduced resolution. This architecture has several drawbacks regarding technology scaling and low power design. The error amplifier relies on MOS devices with good analog performance for design of high gain amplifiers and the current mode or resistor string DAC consumes high power and area. An SAR ADC with two contiguous reference voltages is used in [8] to cover only a narrow input range. But this approach allows no change of set-point or window size. The DAC inherently included in every SAR ADCs can be used to generate the set-point voltage and a modified search algorithm enables window mode operation. The reduced number of steps, required to resolve only a small input range, increases the sample rate without additional power. This paper presents an SAR ADC with flexible window function and redundant search tree, well suited for power management solutions in modern CMOS technologies. The basic circuit structure was previously presented in [9] and is extended by theoretical analysis of the speed enhancement, description of offset and gain error correction and additional measurement results.

the next conversion step. The asynchronous conversion complicates the system integration. An other approach adds redundancy to the conversion algorithms to tolerate wrong comparator decisions in the first conversion cycles and to correct them later on. The most popular possibility is the application of a sub-binary redundant search. During the binary search the step from one control word of the DAC to the next is always divided by 2. In general the step size in cycle i is given by si ¼ q  si1 ¼ s0  qi

with the factor q. The redundant search algorithm uses q [ 0:5 in contrast to the conventional binary search with q ¼ 0:5: Due to the smaller amount of information per cycle, the conversion needs m¼1

N1 N  log2 q log2 q

123

ð2Þ

cycles to reach N bit resolution. The overlap of consecutive steps result in a tolerance range, where a correct conversion result is reached independent of the actual comparator decision, as illustrated in Fig. 2. An incorrect upwards step in the third cycle is corrected later on. The size of the tolerance range is a measure for the redundancy. The conventional binary search algorithm requires settling to 12 LSB accuracy independent of the step size. In contrast, a redundant search relaxes the settling requirements to an acceptable error relative to the step size, leading to an almost constant settling time. Thus, a larger clock frequency can be applied and even with additional conversion cycles an overall speed-up is achieved. Figure 3 shows the steps size s(i) and the required settling time tset ðiÞ for different settings of q at the example of a 10 bit conversion. The redundancy can be built directly into the capacitive DAC, with the main advantage of keeping the power efficient conventional digital control algorithm [12]. But a symmetric error tolerance is only achieved with a fully

2 Redundant search tree The achievable conversion rate of charge redistribution SAR ADCs is mainly limited by the comparator speed and settling of the DAC. The common binary search algorithm requires settling to the final accuracy for all conversion steps. There exist several approaches to increase the attainable sample rate. An asynchronous control prevents incorrect comparator decisions by adjusting the period of each conversion cycle to the actual required settling time. Digitally controlled delay elements are used in [10] to individually tune the duration of each conversion cycle. In [11] the edge at the output of a clocked comparator triggers

ð1Þ

Fig. 2 Illustration of the redundant search

Analog Integr Circ Sig Process

step size s(i) [LSB]

tset(i) [1/τ]

q=0.5 (binary) q=0.54 7 6 5 4 3 2 1

with small step size around that start value, as shown in Fig. 4. Equivalent to the input range of the conventional algorithm, window operation with m cycles leads to a window size w ¼ 2m : The relation between the sample rate fwin in window mode and ffull in full range operation reads

q=0.57 q=0.59

speed up

fwin N þ j ; ¼ ffull m þ j

100

additional cycles

10 1

0

2

4

6

8

10

12

Conversion Cycle i

Fig. 3 Step size and settling time of a 10 bit conversion with redundant search

differential design. Furthermore, the layout complexity is increased by non-binary capacitor ratios. Another approach implements the sub-binary redundancy in the digital control [13, 14], leading to more flexibility but at the cost of higher digital complexity and power consumption. This work applies a generalized non-binary redundant search by digital calculation of the decisions levels with a configurable set of conversion steps.

by assuming j additional cycles for sampling the input voltage. The decreased cycle count in relation to full range operation leads to an increased conversion rate. The digital control of the conventional binary search algorithm requires very little hardware as it can be implemented as a shift register [15]. A tunable initialization can simply be added to existing implementations but the conventional bit cycling can not be applied to arbitrary initial values without an addition. In [16] window operation is performed by adding the set-point to the output of the conventional SAR control unit. Additional multiplexers are used to switch between the SAR control unit for full range or window operation. Figure 5(a) shows this basic circuit

3 Window function The conventional SAR algorithm starts at the center of the input range and reaches N bit resolution in N conversion cycles. It can easily be adapted to window mode operation. Only a reduced input range is captured by starting the search algorithm at a given set-point and adjacent iteration

Fig. 4 Successive approximation with window mode

Fig. 5 SAR architecture with window operation. a Structure from [16], b Proposed structure with improved timing

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Analog Integr Circ Sig Process

structure. The delay of the adder is appended to the timing critical control loop, slowing down the total conversion speed. Non-uniform propagation delay of the adder causes glitches in the DAC control word and they additionally increase the settling time of the DAC. The proposed architecture in Fig. 5(b) eliminates the major timing related disadvantages by placing the arithmetic at the data input of the registers. The presented window operation is enabled by the same arithmetic operations used for the digital calculation of the redundant search. The voltage step to the set-point in the first conversion cycle is the most timing critical. The following steps are smaller and require a shorter settling time. One possibility to ensure accurate settling of the first step is to provide a settling time of two or more clock cycles. The other possibility is to apply a redundant search, that relaxes the settling requirements of the following steps too. For example, the non-binary step sizes {7, 5, 3, 2, 1} allow settling error correction within a tolerance range of ±5 LSB in the first step.

4 Circuit implementation The single-ended architecture consists of a capacitive DAC with top-plate sampling, a fully differential clocked comparator with pre-amplifier, and an advanced digital control.

Fig. 6 Block level schematic of the ADC

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The simplified structure of this architecture is shown in Fig. 6. The redundancy is calculated in the digital part of the converter and not implemented in the DAC. To cover a signal range up to 1.2 V, the complete analog part of the ADC is built of medium-oxide IO devices with a minimal channel length of 150 nm. A supply voltage of 1.8 V instead of 1.0 V core supply is used for comparator, sample switch and DAC. 4.1 Digital control circuit The digital control as presented in Fig. 6 consists of two 10 bit adders and two latch stages for calculation and storage of the control word. The basic structure of the redundant search tree calculation is based on the architecture in our previous work [5]. A synchronous state machine controls the conversion sequence. A look-up table (LUT) provides the step size step½9 : 0 of the control word related to each conversion cycle. Different data sets allow operation with binary or redundant search in full-range and window mode. The next control words ctrlUp=Down½9 : 0 for up and down step are concurrently calculated and thermometer coded. To reduce power consumption and to improve timing, latches are inserted to gate adders and decoders. The first latch stage prevents the thermometer decoder from toggling while addition and subtraction is in progress and provides a constant input for the latches

Analog Integr Circ Sig Process

Fig. 7 Capacitor and decoder array structure

behind the decoder. The second latch stage, associated with the row and column select signals, is directly controlled by the comparator. The comparator decides which control word is stored and used for the next cycle. Instead of multiplexers a custom latch design with two separate data inputs is used. In contrast to [13], the thermometer decoder is not in the timing critical path. This architecture can easily be extended for window mode operation. Instead of initializing the first latch stage with a fixed value (512 for a resolution of 10 bit) the setpoint (center of the window) is used and a data set with adequate step sizes is applied. The additional multiplexer and entries in the LUT are not timing critical and occupy very low area. 4.2 Partly thermometer coded capacitor array As trade-off between area and accuracy a combination of a 7 bit thermometer coded main-DAC and a 3 bit series-split binary weighted DAC is implemented as shown in Fig. 6. The thermometer coded DAC guarantees an inherently good differential linearity, requires no calibration, and occupies an acceptable low area. No MIM capacitors are available in this technology. Instead, the vertical capacitance between metal layers is employed. A unit capacitance of 10 fF is used to prevent coupling from the column and row select lines to the capacitor top-plate and to suppress the non-linear effect of the comparator input capacitance and charge injection of the

sample switch. The resulting input capacitance of 1.28 pF exceeds the kTC-noise requirements. The main-DAC is arranged in a 16 by 8 array with separate thermometer decoder for column and row select signals presented in Fig. 7. The non-unity series-split capacitor is placed in a separate up-sized column inside the array to ensure an uniform proximity. 4.3 Comparator The comparator of an SAR ADC is crucial for its total power consumption. Most of the recent low power SAR ADCs with medium resolution use a clocked latch as dynamic comparator [7, 17]. But large kick-back noise is only tolerable at fully differential architectures, where both inputs of the latch are driven by equal source impedance. Otherwise asymmetric capacitive kick-back noise causes a hysteresis and large offset. At this single-ended architecture, one input of the comparator is connected to the capacitive DAC and the other to the reference voltage, with obviously different source impedance. A pre-amplifier is used to decouple the clocked latch from the DAC and to ensure symmetric input conditions. This arrangement results in a stable DC accuracy but at the cost of static power consumption. The comparator applied in this work consists of two amplifier stages, followed by a clock latch. The amplifiers are built of NMOS differential pairs with resistor loads. A

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Analog Integr Circ Sig Process

Fig. 8 Schematics of the comparator stages. a First pre-amplifier stage with cascode, b clocked comparator latch

replica bias circuitry guaranties proper operating points, insensitive to PVT variations. Figure 8 shows the schematics of the first amplifier stage and the clocked latch. A high bias current of 150 lA is needed to attain a sufficient noise performance of the first stage. The gate-drain capacitance of the differential pair acts as Miller-capacitance and produces an increased signal dependent input capacitance. A cascode is applied to suppress this effect by stabilizing the drain voltage of the differential pair. Additionally, the PSRR of the comparator is improved, because coupling from the supply voltage to the input of the comparator and thereby to the DAC is avoided. The additional current sources M6 and M7 stabilize the operating point of the cascode and prevent the drain nodes of M1 and M2 from floating at large differential input voltages. The gain of the amplifier is not effected by these low always-on currents, but the dynamic behavior is improved.

with a typical large offset but low full-scale error. The offset error is approximated by  EOS  VOS þ VRef 

CTP Nk 2 C þ CTP

 

Qinj ; 2N C

where only the offset of the comparator VOS is a device specific random value. The gain error is completely determined by the parasitic and load capacitance of the DAC EG ¼ 

VRef  CTP Nk 2 C þ CTP

 VRef

CTP : Nk 2 C

Gain and offset of an N bit single ended architecture with top-plate sampling is effected by the parasitic capacitance CTP of the capacitors top-plate, including the comparator input capacitance, by charge injection Qinj of the sample switch, and by the comparator offset VOS . Based on the charge stored in the capacitor array the input voltage VIn related to the conversion result d is defined by   2k  d  C þ Qinj ð3Þ VIn ¼ VRef  1  þ VOS 2N C þ CTP with the reference voltage VRef and the resolution k of the sub-DAC. The resulting characteristic is shown in Fig. 9

123

ð5Þ

The conversion of the digital set-point dSP into the related voltage VSP is effected by identical offset and gain error as illustrated in Fig. 9. A digital correction is applied 0 to adjust the internally used set-point value dSP to the parameters of the actual characteristic in the following way 0 ¼ dSP þ cG  dSP  cOS dSP

5 Digital offset and gain error correction

ð4Þ

ð6Þ

The two correction coefficients cG and cOS are stored in the memory after start-up of the chip. By using the conversion result only relative to the set-point, no additional correction is required. By this approach only occasional and timing uncritical calculations of Eq. 6 are necessary when the setpoint changes, instead of correcting every conversion result.

6 DC–DC converter application system The ADC is integrated into a SoC with a digitally controlled DC–DC converter. The prototype chip contains a Tensilica Xtensa LX4 processor, several ADPLLs [18], an high resolution PWM generator [19], the SAR ADC and

Analog Integr Circ Sig Process

Fig. 9 Characteristic of the single-ended architecture with top-plate sampling

power stage. The buck converter operates at a typical PWM frequency of 1.25 MHz. On-chip power switches drive an external inductor and capacitor to generate a 0.6–1.15 V core voltage from 1.8 V IO supply. A maximum power of 200 mW is provided for the regulated voltage domain. Oversampling the regulated voltage with an ADC sample rate of 16 MS/s enables digital filtering within one PWM cycle to reduce noise. It further allows for fast reaction to load steps by instantaneous restart of the PWM signal. The analog part of the SAR ADC is powered by a separate 1.8 V supply. The digital part is supplied by the global 1.0 V always-on power domain. The ADC has a fully internal bias current generation but uses an external 1.2 V reference voltage.

Fig. 10 Photograph of the fabricated device

7 Measurement results The 3 mm 9 3 mm prototype chip has been fabricated in 28 nm standard-digital low-power CMOS technology and packaged into a 44 pin ceramic package. All power and ground pads are connected by double-bonds. A photograph of the die with all on-chip components is shown in Fig. 10. The layout of the complete ADC including bias circuitry and reference voltage filter is presented in Fig. 11. The dimensions of the ADC are 110 9 85 lm2. The complex digital control is small compared to the comparator and capacitor array, as it occupies only 7 % of the total area. Figure 12 compares the measured INL and DNL error of the conventional binary search and the redundant search algorithm at a sample rate of 16 MS/s. The results of the binary search in Fig. 12(a) suffer from large steps in the characteristic at the main transition points. Applying the redundant search fully eliminates DNL errors caused by insufficient DAC and comparator settling. The resulting INL and DNL is limited to 0.6 LSB and ±0.3 LSB respectively as shown in Fig. 12(b). A slight non-linearity is caused by charge injection of the sample switch and

Fig. 11 Layout of the ADC with a total area of 110 9 85 lm2

voltage dependent input capacitance of the comparator. Shape and magnitude correspond to simulated characteristics. Beside this effect no systematic disturbance is visible. This proves the high accuracy of the partially thermometer coded architecture and proper shielding of the sensitive top-plate. A histogram of measured offset, gain, and INL error is presented in Fig. 13. Low device specific variations allow to apply identical correction coefficients to all devices. Figure 14 shows the measured transfer characteristic in 5 and 6 step window modes. Full redundancy is only available in the range of ±15 and ±31 LSB, but even at the margins no accuracy degradation is visible. As the window

123

DNL [LSB]

-1.0

INL [LSB]

Analog Integr Circ Sig Process

2.0 1.0 0.0 -1.0 -2.0

input frequency = 3.62MHz

0

128

256

384

512

640

768

896

DNL [LSB] INL [LSB]

(a)

2.0 1.0 0.0 -1.0 -2.0

0 -20 -40 -60 -80 -100

SNR = 56.4 dB SNDR = 55.4 dB THD = -62.2 dB SFDR = 62.5 dB ENOB = 8.9

input frequency = 700kHz

1024

Code

-1.0

Amplitude [dB]

0.0

0 -20 -40 -60 -80 -100

Amplitude [dB]

1.0

1.0 0.0

SNR = 59.1 dB SNDR = 56.6 dB THD = -60.1 dB SFDR = 60.0 dB ENOB = 9.1

0

500

1000

1500

2000

2500

3000

3500

4000

Frequency [kHz]

Fig. 15 Measured output spectra of the ADC at 8.3 MS/s. Continuous ADC data transfer rate from the SoC is limited to 125 MHz clock frequency, not allowing sine wave measurement at full sample rate 0

128

256

384

512

640

768

896

1024

Code

(b)

Number

Fig. 12 Measured DNL and INL error at a sample rate of16 MS/s. a Conventional binary search algorithm, b redundant search algorithm

12 10 8 6 4 2 0

38 40 42 44 46 48

12 10 8 6 4 2 0

Offset [LSB]

884 886 888

Gain [LSB/V]

12 10 8 6 4 2 0 0.3 0.4 0.5 0.6 0.7

max(INL) [LSB]

Fig. 13 DC parameters of 41 devices from two wafers

mode directly uses a part of the full range characteristic it achieves the same accuracy. The size of the window is independent of the applied set-point.

Fig. 16 Power breakdown for the ADC in lW

At a clock frequency of 245 MHz the full range mode with redundant search achieves a sample rate of 16 MS/s with 12 cycles for conversion and 3 cycles for acquisition. The sample rate of window mode operation with only 6 or 7 conversion cycles is increased to 26.7 and 24 MS/s. The power consumption is almost not effected by the mode of operation. The output power spectra of the ADC and related dynamic parameters are presented in Fig. 15. A peak SNDR of 56.6 dB is obtained. Spurs are caused by the 880

860

870 +19

860

Code

Code

850

set−point 840 −18 830

0.98

0.99

1

1.01

input voltage [V]

(a)

set−point −33

820 810

window size = 41.3mV 820 0.97

840 830

LSB = 1.2mV

+34

850

1.02

1.03

LSB = 1.2mV window size = 74.9mV

800 0.96

0.98

1

1.02

1.04

input voltage [V]

(b)

Fig. 14 Characteristics of window operation at a set-point of 1.0 V. a Window mode with 6 conversion steps, b window mode with 7 conversion steps

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Analog Integr Circ Sig Process

signal dependent on-resistance of the transmission gate sample switch. But dynamic parameters near Nyquist-frequency are fully uncritical at application in a DC–DC converter, because the regulated voltage has a very low slope and is oversampled by the ADC. Figure 16 shows a power breakdown for the various blocks at 245 MHz clock frequency. The segmentation is based on simulation. Absolute values are adjusted to the measured total power consumption. The power of digital circuitry for redundant search calculation and window function is 81 lW. The total power is dominated by the comparator. The measurement results of the different operating modes are summarized in Table 1. Table 2 presents a performance comparison to recent low power SAR and other ADCs in sub-100 nm techTable 1 Summarized measurement results Parameter

Unit

Full range

Window

Window

Resolution

Bit

10

5

6

Sample rate

MS/s

16

26.7

24

12

6

7

Vset  22 mV

Vset  36 mV

Conv. cycles Input range

V

0–1.2

Reference

V

1.2

Input cap.

pF

1.28

DNL

LSB

±0.3

INL

LSB

0.6

Offset error

mV

Without calibration: 49 with calibr.: ±3

Clock freq.

MHz

50–250

Power

lW

Total: 710, analog: 560, digital: 150

nologies. In full-range mode a FOM of 81 fJ/conv-step and an ENOB of 9.1 bit is reached. Compared to other SAR ADCs this design has a relatively high power consumption caused by the static current of the comparator and the high supply voltage of the analog part, but it achieves a good DC accuracy, insensitive to PVT variations.

8 Conclusion An SAR ADC with redundant search and window function for integrated DC–DC converters is presented. The ADC operates in full range mode during ramp up of the regulated voltage and in window mode during the settled state. The redundant search tree corrects wrong comparator decisions caused by incomplete DAC and comparator settling and allows a sample rate up to 16 MS/s. Window mode operation additionally offers a speed enhancement by factor 1.6 without an increase of clock frequency or power consumption. The location of the window can be altered at every conversion, enabling application of dynamic voltage scaling (DVS). The window function is fully implemented in the digital part of the ADC and compatible with different capacitor array structures. All previously presented SAR ADCs with digital calculation of a redundant search [5, 13, 14] can easily be extended for this window function with few additional hardware. The highly digital nature of the proposed design benefits most from technology scaling, offers much flexibility and allows implementation in sub100 nm CMOS technology. Compared to delay line or ring oscillator based window ADCs, this architecture

Table 2 Performance comparison to other window ADCs and low power SAR ADCs Device parameter

[3]

[20]

[4]

[16]

[17]

[6]

[7]

This work

Architecture/mode

VCO

Pipeline

Delay line

SAR

SAR

SAR

SAR

SAR

Resolution (bit)

(12)

10

4

7 (4b win.)

10

8

10

10 (5/6b win.)

Sample rate (MS/s)

30 (BW)

26

4.0

19.2

40

24

4.0

16 (26.7)

Input range (V)

± 0.45

1.0

0.87–1.32

Vset  80 mV

1.1

0.7

1.36

1.2

ENOB (bit)

10.3

8.7

4.1

–

9.15

7.0

9.4

9.1

INL error (LSB)

1.5

1.2

0.15

–

0.7

0.54

0.42

0.6

FOM (fJ/conv-step)

150

161

210

–

63

17

6.5

81

Supply voltage (V)

–

1.2

1.0 and 2.5

1.2

1.1

0.7

1.1

1.0 and 1.8

Power (lW)

11400

1780

14

21.6

2700

54.6

17.4

710

Area (10-3mm2)

20

330

9

24

80

5.8

47

9.35

Technology (nm)

65

65

65

65

40

40

90

28

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Analog Integr Circ Sig Process

offers a larger input range with constant resolution and highly linear characteristic. Acknowledgments This work was funded by the Leading-Edge Cluster ’Cool Silicon’ and the Center for Advancing Electronics Dresden, which are sponsored by the Federal Ministry of Education and Research (BMBF), Germany.

12.

13.

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Stefan Haenzsche received the Dipl.-Ing. (M.Sc.) in Electrical Engineering from Technische Universita¨t Dresden, Germany in 2006. Since 2006, he has been a research assistant with the Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits at Technische Universita¨t Dresden. His research interests include circuit design of analog to digital converters and mixed signal verification.

Analog Integr Circ Sig Process Sebastian Ho¨ppner received the Dipl.-Ing. (M.Sc.) in Electrical Engineering in 2008 and his Ph.D. in 2013 (received Barkhausen price), both from Technische Universita¨t Dresden, Germany. He is currently with the Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits at Technische Universita¨t Dresden, working on silicon integration of low power SoCs in deep-submicron CMOS technologies. His special research interests include low power and high-performance circuits for clocking and data transmission. He is author or co-author of over 30 papers and 4 patents in the above fields and has acted as reviewer for various IEEE conferences and journals.

Rene Schu¨ffny received the Dr.-Ing (Ph.D.) and the Dr.-Ing. habil. (D.Sc.) degrees from Technische Universita¨t Dresden, Germany, in 1976 and 1983, respectively. Since April 1997, he has held the Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits at Technische Universita¨t Dresden. His research interests include CMOS image sensors and vision chips, design and modelling of analog and digital parallel VLSI architectures, and neural networks. He is author or co-author of numerous publications in the above field and has acted as reviewer for several international journals.

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