Analog Integr Circ Sig Process (2012) 73:801–808 DOI 10.1007/s10470-012-9901-0
Time-based all-digital sigma–delta modulators for nanometer low voltage CMOS data converters YiQiao Lin • Mohammed Ismail
Received: 7 October 2011 / Revised: 28 March 2012 / Accepted: 6 June 2012 / Published online: 1 July 2012 Springer Science+Business Media, LLC 2012
Abstract A phase-based delta–sigma (DR) analog-todigital converter (ADC) is proposed and the idea is demonstrated using two architectures. The first architecture adopts a delay-locked-loop (DLL) mechanism. It is realized by a modification of a DLL using a voltage-controlled delay line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed DR ADC achieved 50.5 dB SNDR or 8.09 bits resolution for a 10 MHz signal bandwidth. The second architecture adopts a combination of voltage-controlled and digitally-controlled delay lines (VCDL–DCDL) as the phase-domain counterparts of an ADC–DAC in a traditional delta–sigma modulator. Simulation results of the new modulator achieve a 57.8 dB SNR, or a 9.28 bit over a 10 MHz bandwidth. Keywords Analog to digital converter DR Modulators Phase quantizer Quantization noise shaping Jitter shaping Low voltage devices Wireless sensor nodes Bio chips
Y. Lin (&) M. Ismail Department of Electrical and Computer Engineering, The Analog VLSI Lab, 2015 Neil Avenue, Columbus, OH 43210, USA e-mail:
[email protected];
[email protected];
[email protected] M. Ismail e-mail:
[email protected] Y. Lin M. Ismail Department of Electrical and Computer Engineering, The ElectroScience Lab, 2015 Neil Avenue, Columbus, OH 43210, USA
1 Introduction Recent time-based implementations of delta–sigma data converters have drawn significant interest in the recent literature. Developments [1–3] in time-based ADCs have utilized voltage controlled oscillator (VCO) based quantizers to realize a voltage-to-frequency-to-digital conversion on a reference clock waveform. As such, the frequency, as a time-varying quantity, is used as the intermediate parameter in the ADC process. In these VCObased DR ADCs, the input voltage is utilized as the control voltage of the VCO, whose output is a clock waveform with its frequency varying as a function of the input voltage. The counter at the output of the quantizer counts the output frequency as a quantized digital signal. Due to the fact that such time-based designs are predominantly constructed with digital circuits, they reap the benefits of digital scaling to nanometer feature sizes, i.e., low power and small die size, when compared to conventional DR ADCs [4]. If we categorize the conventional DR ADC as involving an amplitude-to-digital conversion, and the recently developed VCO-based ADC as involving a frequency-todigital conversion, we propose a Phase-based DR ADC which utilizes a phase-to-digital conversion. This concept is depicted in Fig. 1. Two architectures are then implemented to demonstrate the idea of the phase-based ADC. The first modulator is modified from the block connections of a Delay Locked Loop architecture to realize a single bit phase-based DR ADC modulator, the details of which is described in Sect. 2. The second modulator architecture is realized by a combination of voltage-phase-digital and digital-phasevoltage conversions, resulting in a Multi bit phase-based DR ADC modulator. The details of the multi bit DR ADC
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Fig. 1 Phase-based ADC structure
modulator is described in Sect. 3. We will see that the proposed architecture not only supports low voltage low power applications, but also avoids the jitter accumulation problem when compared to the aforementioned VCObased ADCs.
2 Single-bit phase-based ADC using DLL block 2.1 DLL overview Figure 2 shows the fundamental block diagram of a DLL [5]. In Fig. 2, the output clock is time-delayed from the input clock based on the VCDL control voltageVctrl, where Vctrl comes from the cascade of a phase detector, charge pump and loop filter. The relationship between the input clock phase uin, output clock phase uout, and the control voltage Vctrl is given as uout ðzÞ ¼ uin ðzÞ þ KVCDL Vctrl
ð1Þ
where KVCDL is the VCDL gain. This can be rewritten in terms of the input/output clock phase difference as ð2Þ Du ¼ uout uin ¼ KVCDL Vctrl The charge pump input is the phase difference between the output and reference clocks, and the output of the loop filter acts as a feedback voltage allowing the phase of the output clock to track the reference phase. From Eq. (1), we see that the voltage-to-phase function in Fig. 1 can by realized very easily through a VCDL. To complete the design, a block for phase-to-digital function is needed. 2.2 Proposed single bit DLL-phase-based ADC
stated previously, the VCDL and the phase detector combination functions as a voltage-to-phase converter which outputs a signal pulse of width Duo, where the pulse width is proportional to the control voltage Vctrl. An extra D-flip– flop (DFF) is introduced at the output of the phase detector sampling the Du pulse with a reference clock, uref,diff, and quantizes the phase information contained in the pulse width into 1-bit digital stream, introducing a quantization error E(n) into the circuit. The Z-domain model of the second order DLL-phasebased ADC of Fig. 3 is shown in Fig. 4, where KVCDL is the VCDL gain defined in (2), KCP is the gain of the charge pump which builds the feedback path of the modulator, and uin is the input reference clock to the VCDL and phase detector. The jitter in the sampling reference clock uref,diff is also included as an independent noise source to the quantizer. Figure 4 also shows that there are three main sources of noise: the quantization error E(z), the jitter of the input reference clock uin(z) and the jitter in the sampling reference clock of the DFF, uref,diff. The transfer characteristic of the DLL-based ADC shown in Fig. 4 can be derived as: YðzÞ ¼ STFðzÞVin ðzÞ þ NTFj ðzÞuin ðzÞ þ NTFe ðzÞEðzÞ þ NTFref ðzÞuref ðzÞ
ð3Þ
where, the signal transfer function is given by STFðzÞ ¼
KVCDL z2 ð1 z1 Þ2 KVCDL KCP z1
ð4Þ
the jitter transfer function of the input reference clock of the VCDL and PD is: NTFj ðzÞ ¼
ð1 z1 Þ3 ð1 z1 Þ2 KVCDL KCP z1
ð5Þ
and the quantization noise transfer function is identical to the jitter transfer function of the sampling clock of the DFF:
The single bit phase-based ADC (see Fig. 3) is developed by modifying the DLL of Fig. 2, to yield a DLL-phasebased DR ADC. We cut the original DLL loop at the output of the charge pump to be the input of our new loop. As
Fig. 2 Block diagram of a Delay Locked Loop
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Fig. 3 DLL based ADC block diagram sharing the same mechanism as a conventional DLL
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803 20 0
|STF(z)|
Magnitude (dB)
-20 -40 -60
|NTF (z)| (40dB/decade) e
-80
|NTF (z)| (60dB/decade)
-100
Fig. 4 Z-domain model of DLL based ADC
NTFe ðzÞ ¼ NTFref ðzÞ ¼
ð1 z1 Þ2 ð1 z1 Þ2 KVCDL KCP z1
j
-120 -140 10
ð6Þ
-2
10
-1
10
0
Normalized Frequency (Hz)
Subsequently, the transfer function in Eq. (3) can be simplified as:
Fig. 5 The magnitude of STF(z), NTFe(z), and NTFj(z) with extra order of jitter shaping
YðzÞ ¼ STFðzÞVin ðzÞ þ NTFj ðzÞuin ðzÞ þ NTFe ðzÞðEðzÞ þ uref ðzÞÞ
The output of the charge pump subtracts the effect of the above two and is followed by the loop filter [7, 8]. ð7Þ 2.3 Simulations for DLL-phase-based DR ADC The behavioral model of the presented second order DLLphase-based DR ADC (see Fig. 3) is simulated with a 10 MHz input signal bandwidth and a 640 MHz sampling rate. The input reference clock for the VCDL and sampling clock of DFF are both jittery with the maximum variation window of the clock edge (rising or falling) to be 10 % of the clock period [9]. Figure 6 depicts the power spectral density (PSD) of the ADC output stream when choosing the input amplitude to be -6 dBFS, which achieves the maximum SNDR. With the jittery clock, the ADC achieves a maximum SNDR of 50.5 dB, equivalently 8.09 bits ENOB. On the other hand, the jitter-free clock gives the ADC a SNDR of 54.5 dB, an approximately 4 dB improvement. Furthermore, similar to the second order conventional DR ADC, we found that when doubling the oversampling ratio (OSR), the SNDR is increased by 15 dB (equivalently, the resolution is increased by 2.5 bits). 0
-50
PSD [dB]
The transfer functions in (3) are plotted in Fig. 5 where we have set KVCDL = KCP = 1 for simplicity. We can see that the signal transfer function (STF) shows a low pass characteristic. Furthermore, the quantization noise transfer function NTFe (which is identical to NTFref) shows a high pass characteristic with 40 dB/decade noise shaping. The jitter transfer function NTFj of the input reference clock of both VCDL and the PD also shows a high pass characteristic with 60 dB/decade noise shaping, satisfying the noise shaping condition. It will be easy to explain the above observations by looking at the model in Fig. 4. The extra order of jitter shaping results from the phase quantizer, as the jitter actually goes through an extra order of a z-1loop acting as a differentiator. This makes the proposed design less susceptible to clock jitter in the reference clock. Moreover, we notice that unlike in VCO based quantizers, such as those using ring oscillators, the open loop nature of the VCDL in the proposed architecture makes it possible to eliminate the jitter accumulation present in the ring oscillator [6]. It is also easy to see that stability is not an issue to be concerned with. Moreover, a careful design of the VCDL optimized for linearity must be made as the overall linearity of the converter is directly tied to that of the VCDL. We also recognize that using the charge pump is a highly efficient implementation of the feedback path, which allows for the integration of the input adder into its operation, when compared to traditional feedback path realizations utilizing a DAC. For example, the analog input can be used to control the pull-up current of the charge pump as a voltage controlled current source, while at the same time, the output bit stream can be used to control the pull-down current of the charge pump as a switch.
-100
BW = 10MHz
-150
10
5
10
6
10
7
10
8
Frequency [Hz]
Fig. 6 Output spectrum of DLL-based ADC with both reference jitter shaping and quantization noise shaping
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3 Multi-bit phase-based ADC 3.1 Proposed DR modulator A block diagram of the proposed phase-based ADC is depicted in Fig. 7. The analog input experiences a voltage-tophase-to-digital conversion to achieve a binary output, which then undergoes an inverse conversion, i.e., a digital-to-phaseto-voltage, through the feedback path back to the input. In the feed forward path of the proposed model (Fig. 7) a phase-quantizer (the voltage-to-phase and phase-to-digital blocks) acts as the counterpart of the A/D quantizer in the feed forward path of a classical modulator [4]. The phase-quantizer takes the voltage input, converts it into phase information and digitizes the phase. Next, a multi-bit DAC in the feedback path of the classic modulator is replaced by a digital-to-phase plus phase-to-voltage conversion block. This path starts with the digital word as the control signal to the digital to phase conversion block where the digital word is transformed into a phase signal, which is then converted back as a feedback voltage to be subtracted from the input of the modulator. To realize a circuit implementation of Fig. 7, a 2.5 bit VCDL/DCDL based DR ADC is shown as below in Fig. 8. We next detail the principles of operation for each of the blocks in the proposed system of Fig. 7, as well as their implementations shown in Fig. 8.
Fig. 8 Proposed 2.5 bit VCDL/DCDL based DR ADC
3.1.2 Phase-to-digital conversion with a unique clock tracking scheme Following the voltage-to-phase conversion, in order to digitize the phase waveform of the VCDL output, a decoder is utilized. As shown in Fig. 9, the output of each inverter stage in an N-stage VCDL is used as the input to a register array where the signals are sampled by the reference clock. The outputs of the register array are then sent to a simple priority decoder [10] to achieve an L-bit binary output. The clock input of the delay chain, Uin, is set to be at the input over sampling frequency fs.
3.1.1 Voltage-to-phase conversion The first step in the phase-based ADC is the voltage-tophase conversion. To perform the voltage-to-phase conversion as shown in Fig. 7, we utilize a VCDL with the 4inverter chain [5] in Fig. 8. Generally, the details of an Ninverter chain are shown in Fig. 9. (signal polarity is ignored for simplicity). The delay at the output of the nth delay cell can be written as: Uout;n ¼ Uin þ n Tinv;0 þ n KV Vctrl
ð8Þ
where Uin is the input clock phase, Tinv,0 is the nominal delay of each delay cell, Kv is the gain of each delay element, and Vctrl stands for the analog control voltage. We note that n B N where N is the total number of delay cells in the delay line. In this paper, N = 4.
Fig. 7 Proposed multi bit Phase-based ADC model
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Fig. 9 Voltage-phase-digital conversion
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805
To explain how the phase-to-digital block of Fig. 9 operates, we look at a unique sampling scheme that is realized by having the register sampling clock CLKRef taken directly from the last delay element of the delay chain Uout,N (the Nth delay cell). Thus, compared to the clock input, Uin, the sampling clock of the register CLKRef is delayed by: DUCLK ¼ CLKRef Uin ¼ Uout;N Uin ¼ N Tinv;0 þ N KV Vctrl
DQ ¼
ð12Þ
3.1.3 Digital-to-phase conversion The digital words at the output of the decoder are then used as the input to the DCDL in the feedback path. This DCDL outputs a clock waveform with a delay proportional to the value of the digital words. Figure 10 shows an example of a digitally controlled delay line [11] through which we have the delay at the output approximately proportional to the product of the channel resistance R of the transistors and the total capacitance at the inverter output [11]:
ð9Þ
As previously stated, the control voltage, Vctrl, is assumed constant throughout the sampling period. If we choose NTinv,0 = Ts/2, in Eq. (9), it is evident that: When Vctrl = 0, then DUCLK;0 ¼ N Tinv;0 ¼ Ts=2
1 TS TS ¼ N 2 2N
ð10Þ
Uout;DCDL Uref ¼ DUaR ðCpara þ
N X
C i bi Þ
ð13Þ
i¼1
In this case, the register samples all ‘‘1’’s at DN…D0 and achieves all ‘‘0’’ at decoder output YL…Y0 (as seen in the truth table of the priority decoder in Fig. 9). When Vctrl = DV, then
In Eq. (13), Uout,DCDL and Uref are the phase at the output and input of the DCDL respectively, Cpara is the total parasitic capacitor at the output of the inverter A1. C1…CN are the shunt capacitances of each inverter, and b1…bN refer to the digital words applied to the line as a control vector.
DUCLK;V ¼ N Tinv;0 þ N KV Vctrl ¼ DUN;0 þ N KV DV ¼ Ts=2 þ N KV DV ð11Þ
3.1.4 Phase-to-voltage conversion
where NKVDV e (0, Ts/2). Depending on the value of DV, the decoder [10] detects the first 0–1 transition in the word DN…D0 in order to determine the ‘‘relative delay’’ NKVDV, a linear function of Vctrl. The reason to connect the sampling clock of the register, CLKRef, directly from the output of the delay chain, Uout,N, is to have the CLKref waveform behave as a ‘‘dynamic’’ function of the delay. This delay is also controlled by Vctrl in order to cancel out the nominal (fixed) delay of the delay chain, NTinv,0, and to achieve a linear transformation at the decoder, NKVDV (Table 1). As a result, the phase delay information is quantized into a binary waveform. For an N-stage delay chain, an L bits output is achieved where L = log2N ? 1. We remark that quantization noise (assumed white) introduced in the phase signals is given as:
The delayed waveform from the DCDL, Uout,DCDL, is then compared to the reference clock, Uref at a phase detector. The output of this phase detector is directly connected back to the input giving the modulator a feedback voltage VF. This completes the phase-to-voltage conversion shown in Fig. 8. Looking at the feedback summation node, the input can be treated as a pulse (pulse width Ts) with amplitude in the range of (0 - VDD). The output of the phase detector (the subtracting terminal) is a pulse whose width, DUPD, is modulated by the digital words (and hence is within the range of (0 - Ts)) but with amplitude fixed at VDD. Ideally, the power of the input pulse, VinTs, (area under the dashed line in Fig. 11), and the power of feedback pulse, VDDDUPD, are equivalent.
Table 1 Priority decoder truth table DN
DN-1
……
D1
D0
Decoder output
YL
……
Y1
Y0
1
X
XXXX
X
X
0
0
0…0
0
0
0 0
1 0
XXXX 1 XXX
X X
X X
1 2
0 0
0…0 0…0
0 1
1 0
0
0
01XX
X
X
3
0
0…0
1
1
…
…
…
…
…
…
…
…
…
0
0
0…0
1
X
0
1…1
1
1
0
0
0…0
0
1
1
0…0
0
0
N
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Fig. 10 Shunt-Capacitors-Controlled Delay Line
PSD [dB]
0
-50
-100
BW = 10MHz
3.2 Simulation Summarizing the proposed architecture, the behavioral model of the proposed VCDL/DCDL based DR ADC of Fig. 8 is simulated with the bandwidth of 10 MHz and the oversampling rate of 64. In our simulations, a VCDL with a 4-inverter chain is used to realize the voltage-to-phase conversion. To digitize the phase waveform of the VCDL output, a 4–3 decoder is utilized to perform a five level, 2.5 bit quantization as described in the previous section. The VCDL/DCDL ADC achieves 57.6 dB SNDR and 9.28 bits ENOB (See Fig. 12). We also demonstrate that when doubling OSR, the SNDR increases by 15 dB. The linearity in the feedback path is also simulated in Fig. 13 by looking at the power of the output pulse of the phase detector as a function of the digital words at the DCDL input (digital output of quantizer). We recognize that utilizing phase in both the feedforward path and feedback path of the proposed design, rather than amplitude, allows us to circumvent limited voltage signal swings under today’s increasingly reduced supply voltages, particularly in embedded low voltage devices such as in wireless sensor nodes or bio chips. Compared to existing VCO-based delta sigma ADC models, which use a DAC in the feedback path, our design fully supports rail-torail operation by utilizing phase in both the feedforward and feedback paths. We further remark that unlike the VCO-based quantizers, such as those using ring oscillators, the open loop
-150 10
5
10
6
10
7
10
8
Frequency [Hz]
Fig. 12 Power Spectrum Density of the VCDL/DCDL ADC
Fig. 13 Linear Voltage-Phase-Digital transfer Characteristic (normalized power of the pulse at the output of PD vs the digital code at the input of DCDL)
nature of the VCDL used in the proposed phase-based quantizer eliminates the jitter accumulation factor present in the ring oscillator [6].
4 Conclusion
Fig. 11 Comparison of input and feedback voltage where the ideal equality VinTs = VDDDUPD is satisfied
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A phase-based DR ADC is proposed. Two architectures were implemented to demonstrate the feasibility of this idea. The first architecture utilizes the mechanism of a DLL while introducing a phase quantizer. With a 10 MHz input bandwidth and a sampling rate of 640 MHz, the DLL-phasebased ADC model achieves 50.5 dB SNDR or 8.09 bits ENOB. In addition to quantization noise shaping, the proposed model also offers a third order noise shaping to the reference clock jitter of the phase quantizer, achieving a higher degree of linearity. The proposed architecture is predominantly digital and as such lends itself naturally to low power nano-scale devices. The second architecture
Analog Integr Circ Sig Process (2012) 73:801–808
adopts a VCDL/DCDL combination playing the roles of ADC/DAC in the conventional modulator in the phase domain. In the feedforward path, the voltage-to-phase-todigital conversion is realized through the use of a VCDL for voltage-to-phase conversion and a decoder for the phase-todigital conversion. In the feedback path, a digital-to-phaseto-voltage conversion is completed through the use of a DCDL for the voltage-to-phase conversion, and a phase detector for a phase-to-voltage conversion. Behavioral modeling of a 5-level, 2.5 bits realization is performed by using a 10 MHz input bandwidth and an OSR of 64. The VCDL/DCDL based ADC achieves 57.6 dB SNDR and 9.28 bits ENOB. The proposed design shifts all quantization and feedback operation into the phase domain. Since the architecture is predominantly digital, it can be a highly desirable solution for low power nano-scale device design. Acknowledgments The authors would like to acknowledge useful discussion with Prof. Bahar Jalali-Farahani at Arizona State University, Sleiman Bou-Sleiman at The Ohio State University and WenHung Hsieh at National Chiao Tung University.
References 1. Taillefer, C. S., & Roberts, G. W. (2009). Delta–sigma A/D Conversion Via Time-Mode Signal Processing. IEEE Trans. Circuits Syst. I, Reg. Papers, 56(9), 1908–1920. 2. Straayer, M. Z., & Perrott, M. H. (2008). A 12-Bit, 10-MHz Bandwidth, Continuous-Time DR ADC with a 5-Bit, 950-MS/s VCO-Based Quantizer. IEEE Journal of Solid-State Circuit, 43(4), 805–814. 3. Park, M., & Perrott, M. H. (2009). A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time ADC with VCO-based Integrator and Quantizer Implemented in 0.13 lm CMOS. IEEE Journal of Solid-State Circuit, 44(12), 3344–3358. 4. Schreier, R., & Temes, G. C. (2004). Understanding delta–sigma data converters. New York: Wiley-IEEE Press. 5. Baker, R. J. (2007). CMOS circuit design, layout, and simulation. Wiley-IEEE Press: Wiley-IEEE Press. 6. Beomsup, K., Weigandt, T.C., & Gray, P.R. (1994). PLL/DLL system noise analysis for low jitter clock synthesizer design. In IEEE International Symposium on Circuits and Systems (pp. 31–34). London: IEEE. 7. Chae, Y., & Han, G. (2009). Low voltage low power inverterbased switched-capacitor delta sigma modulator. IEEE Journal of Solid-State Circuit, 44(2), 458–472. 8. Wang, L., & Theogarajan, L. (2010). A micropower delta–sigma modulator based on a self-biased super inverter for neural recording systems. In IEEE Custom Integrated Circuits Conference (CICC) (pp. 19–22). San Jose: CICC. 9. Kundert, K. (2009). Modeling jitter in PLL-based frequency synthesizers. Retrieved June 1, 2009 from http://www.designersguide.org/Analysis/PLLnoise?jitter.pdf. 10. Staszewski, R. B., Vemulapalli, S., Vallur, P., Wallberg, J., & Balsara, P. T. (2006). 1.3 V 20 ps Time-to-digital converter for frequency synthesis in 90-nm CMOS. IEEE Transactions on Circuits Systems II, 53(3), 220–224. 11. Andreani, P., Bigongiari, F., Roncella, R., Saletti, R., & Terreni, P. (1999). A digitally controlled shunt capacitor CMOS delay
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Yiqiao Lin is currently pursuing her Doctorate degree at the Ohio State University’s Analog VLSI Lab and ElectroScience Lab. She obtained the M.S. in 2010 from The Ohio State University, both in Electrical Engineering. Her current research interests are in analog, RF, and mixed-signal integrated circuit design for wireless communication systems. Her current work focuses on the development of an ultra-low power transceiver front end. She has one US patent disclosure pending. Mohammed Ismail Joined Khalifa University of Science, Technology and Research (KUSTAR), UAE in April 2011. He spent over 25 years in academia and industry in the US and Europe and is the Founder of the Ohio State University’s (OSU) Analog VLSI Lab, one of the foremost research entities in the field of analog, mixed signal and RF integrated circuits. He also served on the Faculty of OSU’s ElectroScience Lab. He held a Research Chair at the Swedish Royal Institute of Technology (KTH) where he founded the RaMSiS (Radio and Mixed Signal Integrated Systems) Research Group there. He had visiting appointments in Finland (Aalto university), Norway (NTH and University of Oslo), the Netherlands (Twente University) and Japan (Tokyo Institute of Technology). At KUSTAR, Dr. Ismail holds the ATIC Professor Chair and serves as Director of the Sharjah Campus. He is the Founding Chair of the newly established ECE Department which exists on both campuses (Sharjah and Abu Dhabi) of the University and has its roots in the Etisalat College established in 1989. It now has over 40 faculty and 500 students, 450 undergraduate and 50 graduate students pursuing MS and PhD programs. Dr. Ismail has initiated the new KUSTAR’s ICT Research Center encompassing 5 Research Labs conducting multidisciplinary research in information security, e-services and networks, multimedia communications and embedded mixed signal systems. He is working on creating the ATIC-KUSTAR Semiconductor Research Center focusing on low power System on Chip (SoC) design, test and IP development targeting the strategic areas of low power wireless chip sets, bio chips, self powered devices, power managements as well as research in the emerging fields of nanoscience. The Research is aligned with the 2030 Abu Dhabi strategic plan calling for diversification of the economy beyond oil and gas and for promoting innovation, entrepreneurship and spinoffs in the semiconductor, energy and ICT sectors among others. Dr. Ismail’s current research focuses on robust low power RF and mm-wave ICs for wireless, bio and multimedia applications with a focus on manufacturable low cost high volume nanometer CMOS solutions for mobile and wearable embedded devices. A more recent interest is on nanoscience aiming to develop devices in the sub 10 nm range based on nano Schottky contacts. He served as a Corporate Consultant to over
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808 30 companies and is a Co-Founder of Micrys Inc., Columbus, Ohio, Spirea AB, Stockholm, Firstpass Technologies Inc., Dublin, Ohio and ANACAD-Egypt (now part of Mentor Graphics). He advised the work of over 50 Ph.D. students and of over 100 M.S. students. He authored or co-authored over a dozen books and over 250 journal publications and has 11 US patents. He is the Founding Editor of the Springer Journal of Analog Integrated Circuits and Signal Processing and serves as the Journal’s Editor-in-Chief. He served the IEEE in many editorial and administrative capacities. He is the Founder of the
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Analog Integr Circ Sig Process (2012) 73:801–808 IEEE International Conference on Electronics, Circuits and Systems (ICECS), the flagship Region 8 Conference of the IEEE Circuits and Systems Society. He is a Consulting Editor of the Springer Advanced Analog Book Series. He received the US Presidential Young Investigator Award, the Ohio State Lumley Research Award four times, in 1992, 1997, 2002 and 2007 and the US Semiconductor Research Corporation’s Inventor Recognition Award twice. He is a Fellow of IEEE.