Microsyst Technol DOI 10.1007/s00542-015-2681-6
TECHNICAL PAPER
Wafer level high‑density trench capacitors by using a two‑step trench‑filling process Tao Zheng1,2 · Gaowei Xu1 · Le Luo1
Received: 26 August 2015 / Accepted: 9 September 2015 © Springer-Verlag Berlin Heidelberg 2015
Abstract This paper reports on the design, fabrication and electrical characterization of high-density SIS trench capacitors by using a two-step deposition process for fast-filling the deep trenches. LPCVD silicon nitride is employed as the dielectric material to provide high efficiency deposition in the high aspect ratio trenches. The capacitance density in trench capacitors with 25 nm thick Si3N4 is characterized as high as 57.8 nF/mm2, while the breakdown voltage in trench capacitors with 35 nm thick Si3N4 is recorded to be as high as 14.5 V. Furthermore, the capacitances are measured over an applied voltage range from −5 to 5 V, showing a small voltage-dependence of 1.2 and 0.6 % V−1 for the 25 and 35 nm thick Si3N4 trench capacitor, respectively. The leakage currents are measured and the current transport mechanisms are analyzed. The ESR and ESL of the capacitors with 25 and 35 nm thick Si3N4 are very small, as low as 35–65 mΩ and 0.2–0.28 pH for 0.04 mm2 electrode surface.
1 Introduction The rapid growth of the wireless market has created an urgent requirement for smaller and lighter components with higher performance and more functionalities (Zoschke * Le Luo
[email protected] 1
State Key Laboratory of Transducer Technology, Science and Technology on Microsystem Laboratory, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, People’s Republic of China
2
University of Chinese Academy of Sciences, Beijing 100049, People’s Republic of China
et al. 2007). Integration of high-density capacitors in silicon interposer is a key issue for high-density and advanced packaging, due to its ability to decrease the form-factor and reduce electrical parasitic parameters such as resistance and inductance (Maeng et al. 2008). In order to significantly increase the capacitance density with sufficient breakdown voltages, moving toward deep trench structures is an inevitable way by using bulk-silicon manufacturing technology based on deep reactive ion etching (DRIE) and electrochemical etching (EE) of micrometer-sized pores in silicon (Brunet and Kleimann 2013; Klootwijk et al. 2011; Roozeboom et al. 2001). In the trench structure, the upper electrode is often deposited by situ-doped low pressure chemical vapor deposition (LPCVD) method. Due to the complex deposition process of in situ doping, the trench pores with the diameter of several micrometer cannot be effectively filled. Contrary to situ-doped LPCVD process, undoped process is of many advantages such as easier deposition, increased deposition rate and improved film thickness uniformity (Howe et al. 1996; Kurokawa 1982; Learn 1985). This paper presents the design, fabrication and electrical characterization of semiconductor-insulator-semiconductor (SIS) trench capacitors by using a two-step deposition process for fast-filling the deep trenches. The reliable process offers high manufacturing yield at relatively low cost. In these capacitors, LPCVD silicon nitride layers (<50 nm) are used as dielectric material, while the effective surface area of the silicon substrate is substantially increased by high aspect ratio (>10:1) deep trench etching. Two main device types are discussed: Si3N4 dielectric layer with a thickness of 25 nm featuring high capacitance density and Si3N4 dielectric layer with 35 nm featuring high breakdown voltage.
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Fig. 1 The (a) top view and (b) cross-section of the proposed trench capacitor
2 Design and structure description Figure 1a, b shows the top view and cross-section of the proposed trench capacitor. The capacitor consists of two electrodes, the thin situ-doped poly and the highly boron doped substrate well separated by the dielectric. In order to fill the trench pores with fast rate, the thick undoped polySi is adopted thanks to the advantages of higher deposition rate, better deposition uniformity and the proper control of film thickness. The patterned silicon wafer surface forms the bottom electrode of the capacitor. The dielectric layer is situated directly underneath the top electrode covering the surface of the silicon substrate. The silicon surface and therefore the capacitor area are enlarged by regularly arranged deep trench pores. The capacitors are designed in the rectangular form with top electrode area ranging from 200 × 200 to 3000 × 3000 μm2. And the top electrode is surrounded by the bottom electrode. The bottom electrode around is 200 μm wide and 30 μm apart from the inner top electrode surface. A hexagonal arrangement of the circular trench pores is adopted, and the essential geometry parameters are trench
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Fig. 2 Fabrication process of the proposed trench capacitor
pore diameter d, pitch of the pore array p and pore height h. In this work, capacitors with pore diameter of 3 μm and pitch of 5.5 μm of the trench are designed. For each unit cell, there is a single cylindrical pore. Thus the capacitance density (Cs) can be approximated by the formula of a cylindrical capacitor, plus an additional parallel capacitance corresponding to the remaining top surface using Eq. (1), where εr is the dielectric constant of the insulator. The factor of capacitance density enhancement ∆ is calculated using Eq. (2).
Cs =
ε0 εr × (
√ 3 2 2 ·p +π √ 3 2 2 ·t·p
√ S3D 2 3 dh ∆= =1+ π 2 S0 3 p
· d · h)
(1)
(2)
Using this approximation, it is possible to estimate the actual device capacitance with good accuracy. The theoretical capacitance density for the 25 nm Si3N4 trench capacitors with the pore height of 46 μm is about 43.5 nF/mm2 with capacitance density enhancement of 17.5.
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3 Fabrication SIS trench capacitors are fabricated on a 4-inch <100> silicon substrate with low resistivity (0.019 Ω cm) and a thickness of 500 μm. Silicon nitride is used as the dielectric layer, for its high dielectric constant and strong resistance to impurity diffusion (Habermehl et al. 2009; Ma 1998). For the dielectric of the trench capacitor, both 25 and 35 nm thick Si3N4 are prepared. Usually thinner dielectric layer would lead to the higher capacitance density, whereas thicker dielectric layer would lead to the higher breakdown voltage. Planar capacitors with identical silicon wafer areas are produced in addition to the trench capacitors. Figure 2 illustrates the fabrication steps, which are detailed as follows. (a) A 2 μm thick silicon dioxide layer is formed by thermal oxidation. Windows for etching trench pores are opened on the silicon dioxide film. The wafers are etched at room temperature for 45 min in an ICP reactor from STS. Typical etching conditions are at the pressure of 26 mTorr, etching and passivation time cycles are 8 and 5 s, respectively, yielding etch rates around 1 μm/min. (b) After the wet cleaning process for removing the dioxide, the borosilicate glass (BGS) is deposited in the trenches. A highly boron-doped substrate is formed after a diffusion process. Afterwards, the remaining BGS is removed. The resistivity of the boron-doped substrate is adjusted to 2 mΩ cm. (c) For the dielectric of the trench capacitor, both 25 and 35 nm thick Si3N4 are deposited by LPCVD. After that, the trench pores are deposited with 0.6 μm in situ n-type doped poly-Si from SiH4 and diluted PH3. Afterwards, 1.5 μm-thick undoped poly-Si is deposited by LPCVD to fill the trench pores. A furnace anneal step of 60 min at 950 °C renders the resistivity of the doped poly-Si to about 2.8 mΩ cm. (d) In order to expose the highly doped poly-Si, the undoped poly-Si is removed in 40 wt% potassium hydroxide (KOH) at 40 °C for about 15 min. (e) A 0.2 μm thick silicon dioxide layer is formed by LPCVD-TOES. Windows for etching doped poly-Si layer are opened on the silicon dioxide film. The doped poly-Si is etched in 40 wt% KOH at 40 °C for about 8 min. Then, the Si3N4 dielectric layer is patterned and etched using ion beam etching. (f) To obtain a low ohmic contact, the whole capacitor area is coated with aluminum. After the sputtering of 0.8 μm aluminum layer, the contacts for the top and bottom electrodes are made by the photolithography and wet etching steps.
Fig. 3 The (a) top (b) cross-sectional SEM image of the fabricated trench capacitor (top electrode area = 2000 × 2000 μm2)
Figure 3a, b show the top and cross-sectional SEM image of the fabricated trench capacitor. Capacitor structures are cleaved and cross-sections are inspected by Hitachi S4800 scanning electron microscopy. As shown in Fig. 3b, the pore structures are characterized by a smooth pore wall with a rounded bottom electrode, a diameter of 3.7 μm and a uniform depth of 46 μm. The pore diameter is slightly larger than the mask opening due to some underetch. Figure 4 shows magnified cross-sectional images at the top and bottom of the trench, showing excellent step coverage of the Si3N4 layer. Results show that uniform and conformal coating of trench pores is obtained in three dimensions.
4 Electrical characterization and discussion The capacitance of both the trench and planar capacitors are measured on wafer with an HP 4284A Precision LCR meter. The results of the capacitance values as a function of the top electrode area of the capacitors are plotted in Fig. 5. As expected, the capacitance density enlargement factor about 22.5 can be seen clearly with a perfect linearity.
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Fig. 6 Normalized C–V measurement for proposed capacitors with both 25 and 35 nm thick Si3N4 dielectric layer (the capacitor area is 600 × 600 μm2)
Fig. 4 Magnified cross-sectional SEM images at the (a) top and (b) bottom of the trench (the thickness of the Si3N4 layer is 25 nm)
Fig. 7 Leakage current density as a function of applied voltage (the capacitor area is 600 × 600 μm2)
Fig. 5 Comparison of capacitance vs. capacitor area of both the trench and planar capacitors
This enables the capacitance density of 57.8 and 40.7 nF/ mm2 for the 25 and 35 nm thick Si3N4 trench capacitor, respectively. To analyze the impact of the voltage on the capacitance, capacitance–voltage (C–V) measurements are performed
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using an HP 4284A Precision LCR meter at the frequency of 10 kHz and a test signal level of 0.1 Vrms (root mean square, effective value of the oscillation voltage) applying a dc voltage from −5 to 5 V at room temperature. The C–V measurements are performed on a series of dies. A typical curve for the capacitance behavior versus bias voltage is depicted in Fig. 6. The capacitance data is normalized to C0 (V = 0 V). The devices feature a small voltage-dependence of 1.2 and 0.6 % V−1 for the 25 and 35 nm thick Si3N4 trench capacitor, respectively. The leakage current is measured with the Agilent 4156C Precision Semiconductor Parameter Analyzer. The current density J as a function of the applied voltage V is shown in Fig. 7. As the current breakdown criteria is 10 μA/cm2
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leakage current through the films, the barrier height (ΦB) for tunneling can be calculated from the Eq. (3), where m* is the effective mass of the electron in nitride film and meff is the effective electron mass in the electrode (Jacqueline et al. 2013).
JF−N
e3 meff 4 E 2 exp(− = 2 ∗ 16π ΦB m 3
√ 3/2 2m∗ ΦB 1 ) e E
(3)
Using an effective mass of the electron in nitride film of 0.5 times the free electron mass (Ma 1998), it is calculated that a barrier height of 0.85 and 1.42 eV for the 25 and 35 nm thick Si3N4 film from the slope of the dashed line. Be aware that the barrier height is the difference of the conduction bands of the electrode and the nitride, an increased barrier height of the trench capacitor with 35 nm thick Si3N4 film indicates an increase of the nitride band-gap on thicker film. To further characterize the capacitors, two-port S-parameters are measured with ANRITSU MS2038C vector network analyzer through on-wafer probing in groundsignal-ground (GSG) configuration. A short-open-load-thru (SOLT) calibration is applied to calibrate the measurement setup over the frequency range from 40 MHz to 20 GHz. The characteristic impedance of the measurement system is 50 Ω. The impedance of the trench capacitor is calculated using Eq. (4), where Z0 is the reference impedance of the S-parameter measurement (Abdel-Fattah et al. 2009). Fig. 8 a Current density versus the square root of applied positive voltage (b) F–N tunneling of trench capacitors with both 25 and 35 nm thick Si3N4 dielectric layer
(JEDEC standard), the breakdown voltage occurs at 8.5 V and 14.5 V for the 25 and 35 nm thick Si3N4 trench capacitor respectively, which is lower than the expected theoretical breakdown voltage. It is believed that, for the same applied voltage, the sharp edges of the pores enhance the electric field thus giving rise to larger leakage currents and lower breakdown voltage. The asymmetry in positive and negative biasing may probably be linked to the different interfaces formed by Si3N4 with the top and bottom electrodes. The conduction mechanism for positive bias smaller than 6.8 and 12.2 V for the 25 and 35 nm thick Si3N4 trench capacitor respectively, is dominated by Schottky conduction (represented in Fig. 8a by the dashed lines). At higher electric fields, the bending of the conduction band of the nitride allows electrons to tunneling through or across the electrodes. The leakage current characteristics of the trench capacitors fit Fowler–Nordheim (F–N) plot very well, as exemplified by the data in Fig. 8b, where J is current density and E is the electric field. By analyzing the F–N
Z=
S21 Z0 · 2 1 − S21
(4)
As shown in Fig. 9, for the 25 and 35 nm thick Si3N4 trench capacitors with an area of 200 × 200 μm2 of top electrode, the ESR is about 35 and 65 mΩ, and the ESL is about 0.2 and 0.28 pH respectively, which are of good values as compared to other devices in the literature. As commented, this small resistance is obtained owing to the use of highly doped silicon. The ESR difference between 25 and 35 nm thick Si3N4 trench capacitors could be attributed to the variable thickness of doped poly-Si which may be over-etched by KOH solution. The SIS trench capacitors in dry-etched silicon clearly show their potential in low-loss and broadband decoupling. Especially in the 1–20 GHz range, relevant to wireless communication, the damping is two orders of magnitude more effective than ceramic SMD capacitors, due to the low ESL and ESR.
5 Conclusion High-density wafer level trench capacitors are fabricated by using a two-step deposition process as to fast-fill the
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Microsyst Technol Acknowledgments The authors would like to thank SIMIT for the manufactory platform and package implementation.
References
Fig. 9 Measured impedance vs. frequency for trench capacitors with different dielectric thickness (top electrode area = 200 × 200 μm2)
deep trenches. This SIS trench capacitor with a 25 nm thick Si3N4 film results in a very high capacitance density of 57.8 nF/mm2, which is obviously superior to normal MIM planar capacitors, even when high-k materials are integrated. The trench capacitors with a 35 nm thick Si3N4 film features a breakdown voltage of 14.5 V, which is high enough for the requirement of medical implantable devices. The very low voltage dependence of the devices is highlighted as one distinct feature due to the high doping concentration of the silicon. The leakage current transport regimes are identified as Schottky conduction at lower voltages and F–N tunneling at higher voltages with a barrier height of 0.85 and 1.42 eV for the 25 and 35 nm thick Si3N4 film devices. Finally, superior ESR and ESL values are obtained in these fabricated trench capacitors, leading to effective decoupling in GHz wireless systems.
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