Analog Integr Circ Sig Process (2014) 80:437–447 DOI 10.1007/s10470-014-0356-3

A 14–10 b dual-mode low-noise pipeline ADC for high-end CMOS image sensors Suk-Hee Cho • Jun-Sang Park • Gil-Cho Ahn Seung-Hoon Lee

•

Received: 4 April 2014 / Revised: 14 June 2014 / Accepted: 16 June 2014 / Published online: 11 July 2014 Ó Springer Science+Business Media New York 2014

Abstract This work proposes a low-noise four-stage pipeline ADC operating at 14 b 50 MS/s and 10 b 70 MS/s for high-end CIS applications. In the 10 b 70 MS/s mode, the last-stage MDAC and flash ADC are turned off rather than the first-stage MDAC and flash ADC for the same input-referred noise in both modes. The proposed ADC shares a single amplifier for the first- and second-stage MDACs to reduce power consumption and chip area. The amplifier thermal noise of the SHA and MDACs is minimized by adjusting the trans-conductance of input and current-source transistors while two separate reference voltage drivers for the MDACs and the flash ADCs reduce the switching noise. The prototype ADC in a 0.13 lm CMOS technology providing 0.35 lm thick-gate-oxide transistors shows the measured DNL and INL within 0.79 and 2.54 LSB in the 14 b mode, and 0.53 and 0.44 LSB in the 10 b mode, respectively. The ADC shows the maximum SNDR and SFDR of 68.5 and 86.7 dB in the 14 b 50 MS/s mode, and the SNDR and SFDR of 60.5 and 77.8 dB for the 10 b 70 MS/s mode, respectively. The ADC with the measured input-referred noise of 1.20 LSBrms/14 b consumes 192.9 mW at the 14 b 50 MS/ s, and 184.9 mW in the 10 b 70 MS/s mode with 3.3/1.2 V dual supplies. Keywords Analog-to-digital converter  Pipeline  CMOS image sensor  Dual-mode  Input-referred noise  Separate reference

S.-H. Cho  J.-S. Park  G.-C. Ahn  S.-H. Lee (&) Department of Electronic Engineering, Sogang University, 35 Baekbeom-ro, Mapo-Gu, Seoul 121-742, Korea e-mail: [email protected]

1 Introduction In contrast with a charge-coupled device (CCD) image sensor, a CMOS image sensor (CIS) has not only many attractive features such as low power, low cost, small chip area, and high-speed operation but also on-chip system integration capabilities with other circuits using CMOS technologies. Thus, it has been recently utilized in a wide range of fields such as mobile devices, medical imaging equipment, automotive systems, and high-resolution digital cameras [1, 2]. In particular, demand for high-performance analog-to-digital converters (ADCs) has drastically increased for high-resolution digital cameras such as digital single-lens reflex (DSLR) cameras and hybrid digital cameras. Figure 1 shows a block diagram of a high-end CIS in high-resolution digital cameras, which consists of a pixel array, a row/column scanner, correlated double sampling (CDS) circuits, analog MUXs, variable gain amplifiers (VGAs), and ADCs. Notably, the sensor requires 24 Mpixels at a frame rate of 10 frame/s (fps) with a resolution of 14 b to provide high-definition images in a stillimage mode, while requiring 6 Mpixels at a frame rate of 60 fps with a resolution of 10 b rapidly to process a large amount of data in a video mode. Recently, single-slope ADCs (SS-ADCs), successive approximation register-based ADCs (SAR-ADCs), and cyclic ADCs have been widely adopted for the columnparallel ADC architecture in the commercial CIS market. However, the SS-ADCs may make it difficult to achieve both high speed and high resolution since the required clock frequency increases by a factor of 2N with N-bit resolution [3, 4]. The SAR-ADCs and cyclic ADCs are capable of implementing high speed, unlike the SS-ADCs, because they need only N cycles for N-bit conversion. Unfortunately, they are still restricted for implementing

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Fig. 1 High-end CIS block diagram for a high-resolution digital camera

both high speed and high resolution. In addition, since the SAR-ADCs should include a digital-to-analog converter (DAC) whose area increases exponentially with resolution, it increases power consumption and chip area. It is also difficult to satisfy a high resolution of over 14 b due to parasitic capacitances and capacitor mismatch [5, 6]. Meanwhile, the pipeline ADCs for the multi-channel ADC architecture are more suitable than the column-parallel ADCs in the CIS products to meet high resolution and high speed and to minimize the mismatch concerns such as fixed-pattern noise (FPN) between the ADC channels. Especially, the pipeline topology has been employed as one of the best candidates to achieve a target specification such as a resolution of 14 b and above several tens of MS/s [7, 8]. A variety of calibration techniques have been recently invented for high resolutions exceeding 14 b [9, 10]. However, the calibration techniques require additional circuits and timing cycles with corresponding increased power consumption and chip area. On the other hand, analog circuits for the CIS applications commonly employ a high supply voltage to acquire a high dynamic range, while digital circuits use a low supply voltage to improve power efficiency at an image signal processor (ISP) [11– 13]. This work proposes a dual-mode pipeline ADC for the multi-channel ADC architecture operating in the 14 b 50 MS/s still-image mode and the 10 b 70 MS/s video mode without any additional calibration techniques. The proposed ADC can support the high-end CIS specifications mentioned above by employing 6 channel ADCs. The ADC converts an analog signal of 2.2VP–P into low voltagebased digital data by using both supply voltages, 3.3 and 1.2 V. The ADC is based on four stages deciding 4, 4, 4,

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and 5 b, respectively, to operate in the two modes. In the 10 b 70 MS/s mode, the last-stage multiplying DAC (MDAC) and flash ADC are turned off rather than the firststage MDAC and flash ADC for the same input-referred noise for the both modes. The amplifier thermal noise of an input sample-and-hold amplifier (SHA) and MDACs is minimized by adjusting the trans-conductance of input and current-source transistors. Furthermore, two separate reference voltage drivers for the MDACs and flash ADCs reduce signal interference and instability problems caused by switching noise. This paper is organized as follows. The proposed ADC architecture is discussed in Sect. 2. The proposed design techniques and detailed circuit implementation are described in Sect. 3. The measured results of the prototype ADC are summarized in Sect. 4. Finally, the conclusion is given in Sect. 5.

2 Proposed ADC architecture The proposed dual-mode low-noise four-stage pipeline ADC operating at 14 b 50 MS/s and 10 b 70 MS/s determines 4 b in the first three stages and 5 b in the last stage, as shown in Fig. 2. To process a wide range of analog signals, an input SHA, MDACs, flash ADCs, on-chip current and voltage (I/V) references, and a clock generator designed using thick-gate oxide transistors with a 0.35 lm minimum length operate under a 3.3 V power supply. On the other hand, a digital correction logic (DCL) block with a decimator circuit designed using thin-gate oxide transistors with a 0.13 lm minimum length processes digital data based on a 1.2 V power supply. The proposed ADC can be

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Fig. 2 Proposed 14 b 50 MS/s and 10 b 70 MS/s dual-mode pipeline ADC

configured in the two operating modes. In the 14 b 50 MS/ s mode, all of the pipelined stages are active, whereas at 10 b 70 MS/s, the last-stage MDAC and flash ADC are turned off rather than the first-stage MDAC and flash ADC for the same input-referred noise for both modes. The SHA based on flip-around architecture adopts a single-stage amplifier with gain-boosting circuits to achieve the required high DC gain and high phase margin while reducing power consumption. Each two-stage amplifier in the MDACs uses a cascode compensation technique for a wide bandwidth and a stable signal settling. Moreover, the first- and second-stage MDACs, MDAC1 and MDAC2, share a high-gain amplifier to reduce power consumption and chip area. Additionally, two separate reference voltage drivers for the MDACs and the flash ADCs reduce signal interference and power consumption. The DCL block converts the digital data based on high voltage into low voltage by employing a level-shift circuit.

3 Circuit implementation 3.1 Input SHA with gain-boosting circuits for minimizing power consumption, chip area, and noise Since an input SHA is a critical functional block that limits the performance of the pipeline ADC, it essentially requires a high-gain amplifier that has a wide bandwidth and a high phase margin to minimize error components such as signal settling error, and non-linearity at the 14 b level resolution. In the case of using a two-stage amplifier, it is possible to obtain a high DC gain and a sufficient output voltage swing range. However, the power consumption of the two-stage amplifier is considerably increased to achieve a sufficient phase margin because the input trans-conductance of the

second-stage amplifier should be increased to push a nondominant pole far away from a unity-gain frequency. In addition, the two-stage amplifier has to employ a frequency compensation technique for stable settling behavior, and it is more affected by thermal noise than a single-stage amplifier [14]. Flip-around and charge redistribution architectures have been commonly used in the SHA. The flip-around SHA using two capacitors has the advantage that the required bandwidth is decreased by half to achieve the same closedloop bandwidth compared to charge redistributed SHA, because the feedback factor (b) of the flip-around SHA is ideally twice as high. Therefore, the flip-around SHA results in less power dissipation. The twice higher b of the flip-around SHA also provides half reduction in thermal noise of the SHA during the holding phase. Although the flip-around SHA provides improvements in power consumption and thermal noise, it has one drawback in that input common-mode voltage is changed according to the difference between the input and output common-mode voltage of the amplifier [15]. The proposed input SHA with flip-around architecture utilizes a single-stage folded-cascode amplifier with gainboosting circuits, as shown in Fig. 3, to provide a high DC gain, a high phase margin, low thermal noise, and a large input common-mode voltage range. The gain-boosting circuits, GBP and GBN, also use a folded-cascode amplifier with a PMOS or NMOS input differential pair to allow for a flexible input common-mode voltage range and to acquire a high DC gain. When using the gain-boosting amplifier, a closely spaced pole and zero (doublet) affecting signal settling behavior are formed around a unity-gain bandwidth of the gain-boosting amplifier (fu,ba) [16]. In order to optimize the signal settling behavior of the main amplifier, the fu,ba should be located between an f-3dB and the second pole of the main amplifier. When it approaches

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Fig. 3 Low-noise gain-boosted amplifier in input SHA

the second-pole, signal settling degradation due to the doublet is mitigated [17]. Considering the above doublet issues, the proposed SHA based on the gain-boosting circuits achieves a high DC gain of 100 dB and a high phase margin around 86°. On the other hand, the dynamic performance of the pipeline ADC is restricted due to kT/C noise caused by sampling switches and amplifier thermal noise in each pipelined stage. The kT/C noise and the amplifier thermal noise are determined by the size of a sampling capacitance and the trans-conductance of MOS transistors of the amplifiers, respectively. The input-referred thermal noise of the proposed folded-cascode amplifier in the SHA is derived in (1), where gm1,2 is the transconductance of input differential pair transistors, M1– M2, and gm4,5, gm10,11 indicate the trans-conductance of current-source transistors, M4–M5 and M10–M11, respectively [14]. ! 2 2gm4;5 2gm10;11 2 Vn;folded;input ¼ 8kT þ þ ð1Þ 3gm1;2 3g2m1;2 3g2m1;2 From (1), it is noted that the M1–M2, the M4–M5, and the M10–M11 transistors contribute most of the thermal noise while cascode transistors, M6–M9, contribute negligible thermal noise. To minimize amplifier thermal noise, the gm4,5 and the gm10,11 are minimized by increasing the overdrive voltage of the M4–M5, and the M10–M11 transistors considering the output voltage swing range of the amplifier. In addition, amplifier thermal noise is further reduced by increasing the gm1,2. Considering the required 14 b accuracy and the kT/C noise at the input signal of 2.2VP–P, a capacitance of 6.0 pF is chosen for a sampling capacitance of the SHA.

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3.2 Shared amplifier and switched bias for low-noise MDACs To implement the high-speed and high-resolution pipeline ADC, an output voltage of MDACs has to settle with a gain error of less than a half LSB of N-bit resolution required at each stage for amplification. The proposed first- and second-stage MDACs, MDAC1 and MDAC2, share a single amplifier with two separate differential input pairs to reduce power consumption and chip area, as shown in Fig. 4, considering the fact that the amplifier operates only during half of a full sampling clock cycle in a switchedcapacitor architecture. The shared amplifier employs a twostage amplifier to meet a high DC gain and a wide bandwidth. Both the first- and second-stage amplifiers are based on a telescopic topology thereby achieving a high DC gain of 102 dB. Inactive input pairs between the two NMOS input pairs of the first-stage amplifier are tied to a fixed bias voltage to remove a memory effect caused by a typical amplifier-sharing technique, as shown in Fig. 4. Moreover, two MOS switches steering a bias current of the first-stage amplifier are turned on and off alternately with a slightly overlapped clock, Q1B and Q2B, as shown in the right side of Fig. 4. The switches can reduce the undesired glitch noise of the shared amplifier during the switching operation. On the other hand, the proposed two-stage amplifier employs a cascode compensation technique where a compensation capacitor, CC, is fed back into a low-impedance cascode node of the first-stage amplifier to obtain a high phase margin with less power consumption compared to a Miller compensation technique [18]. With this compensation technique, the amplifier achieves a phase margin around of 60° and the required bandwidth with low power consumption.

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Fig. 4 High-gain low-noise amplifier with sharing technique for MDAC1 and MDAC2

As the input SHA, the sampling capacitance of the MDAC1 is 6.0 pF considering the kT/C noise because it is also a critical functional block that limits the performance of the pipeline ADC. In the case of the two-stage amplifier, noise resulting from the second-stage amplifier is usually negligible because it is divided by the DC gain of the firststage amplifier. For this reason, the input-referred thermal noise of the proposed first-stage telescopic amplifier, excluding that of the second-stage amplifier, is derived in (2), where gm1,2 is the trans-conductance of the input differential pair transistors, M1–M2, and gm6,7 indicates the trans-conductance of current-source transistors, M6–M7 [14]. ! 2 2g m6;7 2 Vn;telescopic;input ¼ 8kT þ ð2Þ 3gm1;2 3g2m1;2 Since the telescopic amplifier has fewer transistors contributing to thermal noise compared to the folded-cascode amplifier, it is possible to design a low-noise amplifier. In this work, the amplifier thermal noise of the MDACs is minimized under the same principle as the input SHA, which adjusts the trans-conductance of the input and current-source transistors. The proposed ADC should simultaneously implement the two modes, one for the 14 b 50 MS/s mode and the other for the 10 b 70 MS/s mode. For the 10 b 70 MS/s mode, which does not use the whole pipelined stage, there are two architectures: one is to turn off the first-stage MDAC and flash ADC, and the other is to turn off the laststage MDAC and flash ADC. The architecture turning off the first-stage MDAC and flash ADC has the advantage of high power efficiency because power consumption in the first-stage MDAC is higher than that of the later stages. However, it is not suitable for high-end CIS applications

requiring the same input-referred noise for both modes. On the other hand, the noise of the last-stage MDAC3 has a negligible contribution to the input-referred noise of the ADC since it is divided by the gain of the MDAC1 and MDAC2. Therefore, the proposed ADC employs a switch controlled by an SHDNB signal in a bias circuit of the MDAC3, as shown in Fig. 5, to selectively change between the 14 b 50 MS/s and 10 b 70 MS/s modes. At 10 b 70 MS/s, the power consumption of the MDAC3 is reduced by turning off the switch while the ADC achieves the same input-referred noise with the 14 b 50 MS/s mode. In addition, a switch controlled by the SHDNB signal is also applied to a bias circuit of the last-stage flash ADC4 to minimize power consumption in the 10 b 70 MS/s mode. 3.3 On-chip I/V references with separate drivers to minimize switching noise and power consumption I/V references insensitive to supply voltage and temperature variations are essential to achieve required accuracy in the 14 b 50 MS/s and 10 b 70 MS/s modes, respectively. The proposed I/V references used for the input SHA, the MDACs, and the flash ADCs are implemented on-chip for various system applications, as shown in Fig. 6. If only one reference voltage driver for the MDACs and the flash ADCs is applied, interference and instability problems for the reference voltage occur due to switching noise according to a different operating target between the MDACs and the flash ADCs. It is noted that the signal settling behavior of the reference voltage is difficult to satisfy a 14 b accuracy corresponding to the input signal of 2.2VP–P. As a result, the reference voltage driver requires a wide bandwidth and high power consumption to solve the

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Fig. 5 MDAC3 with switch-based bias circuit for 10 b 70 MS/s mode

Fig. 6 I/V references to minimize switching noise and power consumption

above problems. To minimize the problem of signal interference and instability of the reference voltage for the MDACs and the flash ADCs, a current reference generator (IREF) and a voltage level shifter are shared, and only reference voltage drivers based on a single reference voltage are separated, as shown in Fig. 6. Through the two separate reference voltage drivers, the interference and the instability problem caused by the switching noise is minimized. Thus, the reference voltage for the MDACs requiring high resolution can achieve better signal settling behavior with less power consumption. Since the reference voltages based on the switchedcapacitor architecture tend to contain switching noise and transient glitches due to repeated charging and discharging operations, it is difficult to maintain calm and constant

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reference voltages at the 14 b level. Considering the different operation targets between the MDACs and the flash ADCs, apart from internal RC filters at each reference voltage output node, external 0.1 lF bypass capacitors are employed for stable signal settling behavior. Current mismatch can be calibrated in the digital domain by 3 b IVCN digital codes considering various customer environments, and external reference voltages can be used selectively according to system applications.

4 Prototype ADC implementation and measurements The prototype dual-mode ADC operating in the 14 b 50 MS/s and 10 b 70 MS/s modes for high-end CIS

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Fig. 7 Die photo and layout of the dual-mode CMOS prototype ADC operating in the 14 b 50 MS/s and 10 b 70 MS/s modes

Fig. 9 Measured FFT spectrum of the proposed ADC a 14 b 50 MS/ s mode (1/2 fS down sampled) and b 10 b 70 MS/s mode (1/4 fS down sampled) Fig. 8 Measured DNL and INL of the prototype ADC a 14 b mode and b 10 b mode

applications is implemented in a 0.13 lm CMOS technology, as shown in Fig. 7. The ADC occupies an active die area of 1.17 mm2, including on-chip MOS decoupling capacitances of 370 pF to reduce signal interference

between functional blocks, EMI, power supply noise, and high-speed transient glitches. The prototype ADC dissipates 192.9 mW in the 14 b 50 MS/s mode and 184.9 mW at 10 b 70 MS/s. The measured differential non-linearity (DNL) and integral non-linearity (INL) are within 0.79 and 2.54 LSB

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Fig. 11 Measured input-referred noise of the prototype ADC in the 14 b 50 MS/s mode

of (4), the 14 b level quantization noise power of (5), and the input-referred thermal noise power from the kT/C noise and the amplifier in the SHA and the MDAC1 of (6) [19]. 0 1 B Vrms C SNRthermal ¼ 20 log@qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiA 2 2 NQ þ NT Fig. 10 Measured SNDR and SFDR performance of the prototype ADC versus a fS and b fIN

in the 14 b 50 MS/s mode, and within 0.53 and 0.44 LSB in the 10 b 70 MS/s mode, respectively, as shown in Fig. 8. The typical FFT spectrum at 14 b 50 MS/s and 10 b 70 MS/s with a differential input sinusoidal signal of 4 MHz is shown in Fig. 9(a, b), respectively. Figure 10(a) shows the signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) variations of the prototype ADC with the sampling frequencies increased from 10 to 50 MHz in the 14 b 50 MS/s mode and 10 to 70 MHz in the 10 b 70 MS/s mode, respectively, with a differential input frequency of 4 MHz. While the sampling frequencies increase, the measured SNDR and SFDR are maintained above 68.5 and 86.7 dB in the 14 b 50 MS/s mode, and 60.5 and 77.8 dB for the 10 b 70 MS/s mode, respectively. The SNDR and the SFDR are measured with the input frequency of up to the Nyquist frequency in the 14 b 50 MS/s and 10 b 70 MS/s modes, respectively, as shown in Fig. 10(b). When the input frequency increased to the Nyquist frequency, the SNDR and SFDR are maintained above 64.4 and 82.3 dB at 14 b 50 MS/s, and above 58.3 and 70.0 dB at 10 b 70 MS/s, respectively. Theoretically achievable maximum SNRthermal can be expressed in (3). Equation (3) is based on the sinusoidal input signal power with a peak-to-peak amplitude of VP–P

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VPP Vrms ¼ pffiffiffi 2 2 rffiffiffiffiffi 1 VPP NQ ¼ 12 214 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi   4kT 32kT 1 9 NT ¼ þ þ CS 3 CCS 64CCM1

ð3Þ

ð4Þ ð5Þ ð6Þ

In the above equations, CS is the sampling capacitance of the input SHA and MDAC1, and CCS is the load capacitance of the SHA while CCM1 is the compensation capacitance used in the MDAC1. Those values are 6.0, 6.5, and 1.0 pF, respectively. Substituting these values for the above (3), the maximally acquired SNRthermal is about 75.5 dB. The input-referred noise of the proposed ADC is measured with a histogram of 16,384 output samples by employing a fixed DC input signal. The measured inputreferred noise (NI) is 1.20 LSBrms at 14 b 50 MS/s, as shown in Fig. 11. Substituting (4), (5), and the NI for (7), the calculated SNRmeasured is about 73.6 dB, which closely matches the theoretically predicted calculation, SNRthermal, due to only a difference of about 2.0 dB. 0 1 B Vrms C SNRmeasured ¼ 20 log@qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiA NQ2 þ NI2

ð7Þ

Analog Integr Circ Sig Process (2014) 80:437–447 Table 1 Performance summary of the prototype ADC

445

Resolution

14 bits

10 bits

Speed

50 MS/s

70 MS/s

Process

Samsung 0.13 lm CMOS

Supply

A = 3.3 V, DH = 3.3 V, DL = 1.2 V

Input range

2.2VP–P (differential)

SNDR

68.5 dB (@ fIN = 4 MHz)

60.5 dB (@ fIN = 4 MHz)

SFDR

86.7 dB (@ fIN = 4 MHz)

77.8 dB (@ fIN = 4 MHz)

DNL

-0.79/?0.77 LSB

-0.53/?0.38 LSB

INL

-2.54/?2.45 LSB

-0.44/?0.37 LSB

Input-referred noise

1.20 LSBrms

\1 LSBrms

ADC power

192.9 mW

184.9 mW

Die area 1.17 mm2 (= 1.32 9 0.89 mm2)

In the 10 b 70 MS/s mode, the input-referred noise is measured with much less than 1 LSB of 10 b since the laststage MDAC3, which has a negligible contribution to the input-referred noise of the ADC, is turned off. Table 1 summarizes the performance of the prototype ADC, while the performances of other 14 b ADCs are compared in Table 2. The figure of merit (FoM), defined as (8), of the prototype ADC is 1.77 pJ/conversion-step in the 14 b 50 MS/s mode, and 3.05 pJ/conversion-step for the 10 b 70 MS/s mode, including the power consumption of the on-chip reference generator. The prototype ADC shows a high SNDR of 68.5 dB and a low power consumption of 192.9 mW in the 14 b 50 MS/s mode and a very high SNDR of 60.5 dB in the 10 b 70 MS/s mode. The prototype ADC can be applied for high-end CIS applications by simultaneously implementing both the 14 b 50 MS/s stillimage mode and the 10 b 70 MS/s video mode with less power consumption and a small chip area. FoM ¼

Power  fs

ð8Þ

2ENOB

5 Conclusion This work proposes a low-noise dual-mode pipeline ADC operating in a 14 b 50 MS/s still-image mode and a 10 b

70 MS/s video mode for high-end CIS applications. At 10 b 70 MS/s, the last-stage MDAC and flash ADC are turned off for the same input-referred noise in both modes. An input SHA with flip-around architecture employs a single-stage folded-cascode amplifier with gain-boosting circuits to satisfy a high DC gain, a wide bandwidth, and common-mode variation while minimizing power consumption, chip area, and noise. A two-stage amplifier is shared between first- and second-stage MDACs, MDAC1 and MDAC2, without extra series switches and memory effects by employing two separate NMOS input pairs. The amplifier thermal noise of the SHA and the MDACs is minimized by properly adjusting the trans-conductance of input and current-source transistors. The problem of interference and instability of a reference voltage, occurring from different operation targets between the MDACs and the flash ADCs, are much reduced by separating reference voltage drivers. The proposed dual-mode ADC is implemented in a 0.13 lm CMOS and occupies an active die area of 1.17 mm2. The measured DNL and INL are within 0.79 and 2.54 LSB in the 14 b mode, and within 0.53 and 0.44 LSB in the 10 b mode, respectively. The ADC shows a maximum SNDR and SFDR of 68.5 and 86.7 dB in the 14 b 50 MS/s mode, and 60.5 and 77.8 dB in the 10 b 70 MS/s mode, with a 4 MHz input,

Table 2 Performance comparison of recently reported 14 b ADCs References

Speed (MS/s)

Supply (V)

Power (mW)

Area (mm2)

DNL/INL (LSB)

SNDR (dB) FoM (pJ/Conv.)

Process

This Work

50

3.3/1.2

192.9

1.17

0.79/2.54

68.5

1.77

0.13 lm CMOS

[20]

32

2.5

187.5

2.80

0.70/6.00

58.0

9.03

0.25 lm CMOS

[7]

70

2.5

235.0

3.32

0.65/1.80

65.7

2.13

0.13 lm CMOS

[21]

80

3.3/5.0

–

0.40/0.60

74.0

3.66

0.35 lm BiCMOS

[9]

100

1.2

250.0

1.00

0.90/1.30

73.0

0.69

90 nm CMOS

[22]

100

1.5

224.0

1.02

1.10/2.00

66.5

1.30

0.13 lm CMOS

[8]

100

3.0

230.0

7.28

0.80/2.10

72.4

0.68

0.18 lm CMOS

1,200.0

123

446

respectively. The measured input-referred noise of the ADC is 1.20 LSBrms for the 14 b 50 MS/s mode. The ADC consumes 192.9 mW in the 14 b 50 MS/s mode and 184.9 mW in the 10 b 70 MS/s mode with 3.3/1.2 V dual supplies. Acknowledgments This work was supported by the MSIP (Ministry of Science, ICT and Future Planning), Korea, under the ITRC (Information Technology Research Center) support program (NIPA2014-H0301-14-1007) supervised by the NIPA (National IT Industry Promotion Agency), and the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (Grant number 2013R1A1A2004829).

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Analog Integr Circ Sig Process (2014) 80:437–447 13. Storm, G., et al. (2006). Extended dynamic range from a combined linear-logarithmic CMOS image sensor. IEEE Journal of Solid-State Circuits, 41(9), 2095–2106. 14. Razavi, B. (2001). Design of analog CMOS integrated circuits. New York: Mc Graw Hill. 15. Yang, W., et al. (2001). A 3-V 340-mW 14-b 75-M sample/s CMOS ADC with 85-dB SFDR at nyquist input. IEEE Journal of Solid-State Circuits, 36(12), 1931–1936. 16. Ahmadi, M. M. (2006). A new modeling and optimization of gain-boosted cascode amplifier for high-speed and low-voltage applications. IEEE Transactions on Circuits and Systems II, 53(3), 169–173. 17. Bult, K., & Geelen, G. (1990). A fast-settling CMOS opamp for SC circuits with 90-dB DC gain. IEEE Journal of Solid-State Circuits, 25, 1379–1384. 18. Kim, Y. J., Lee, K. H., Lee, M. H., & Lee, S. H. (2009). A 0.31 pJ/conversion-step 12-bit 100 MS/s 0.13 lm CMOS A/D converter for 3G communication systems. IEICE Transactions on Electronics, E92-C(9), 1194–1200. 19. Choi, H. C., Yoo, P. S., Ahn, G. C., & Lee, S. H. (2011). A 14 b 150 MS/s 140 mW 2.0 mm2 0.13 lm CMOS A/D converter for software-defined radio systems. International Journal of Circuit Theory and Applications, 39(2), 135–147. 20. Meruva, A., Jalali-Farahani, B. (2009). A 14-b 32 MS/s pipelined ADC with novel fast-convergence comprehensive background calibration. In Proceedings of IEEE ISCAS (pp. 956–959). 21. Bardsley, S., et al. (2006). A 100-dB SFDR 80-MSPS 14-bit 0.35lm BiCMOS pipeline ADC. IEEE Journal of Solid-State Circuits, 41(9), 2144–2153. 22. Bogner, P., et al. (2006) A 14 b 100 MS/s digitally self-calibrated pipelined ADC in 0.13 lm CMOS. In Proceedings of ISSCC Digest of Technical Papers (pp. 832–841).

Suk-Hee Cho received the B.S. degree in electronics and information engineering from Korea University, Jochiwon, Korea, in 2012. He is currently pursuing the M.S. degree in electronic engineering of Sogang University, Korea. He is a scholarship student supported by LG electronics. His current interests are in the design of high-resolution CMOS data converters, PMICs, and very high-speed mixedmode integrated systems. Jun-Sang Park received the B.S. and M.S. degrees in electronic engineering from Sogang University, Seoul, Korea, in 2012 and 2014, where he is currently pursuing the Ph.D. degrees. His current interests are in the design of high-resolution low-power CMOS data converters, PMICs, and very high-speed mixed-mode integrated systems.

Analog Integr Circ Sig Process (2014) 80:437–447 Gil-Cho Ahn received the B.S. and M.S. degrees in electronic engineering from Sogang University, Seoul, Korea, in 1994 and 1996, respectively, and the Ph.D. degree in electrical engineering from Oregon State University, Corvallis, in 2005. From 1996 to 2001, he was a Design Engineer at Samsung Electronics, Kiheung, Korea, working on mixed analog & digital integrated circuits. From 2005 to 2008, he was with Broadcom Corporation, Irvine, CA, working on mixed-signal circuits. Currently, he is an Associate Professor in the Department of Electronic Engineering, Sogang University. His research interests include high-speed, high-resolution data converters and low-voltage, low-power mixed-signal circuits design.

447 His current research interests include design and testing of high-resolution high-speed CMOS data converters, CMOS communication circuits, integrated sensors, and mixed-mode integrated systems. Dr. Lee has been a member of the editorial board and the technical program committee of many international and domestic journals and conferences including the IEEK Journal of Semiconductor Devices, Circuits, and Systems, the IEICE Transactions on Electronics, and the IEEE Symposium on VLSI Circuits. Since 2006, he has been organizing various industry-university mutual cooperative programs with many companies such as Samsung Electronics, SK Hynix, and LG Electronics. In 2010, he founded Analog IP Research Center supported by the Ministry of Science, ICT & Future Planning, Korea.

Seung-Hoon Lee received the B.S. and M.S. degrees in electronic engineering from Seoul National University, Korea, in 1984 and 1986, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign, in 1991. He was with Analog Devices Semiconductor, Wilmington, MA, from 1990 to 1993, as a Senior Design Engineer. Since 1993, he has been with the Department of Electronic Engineering, Sogang University, Seoul, where he is currently a Professor.

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