Microsyst Technol DOI 10.1007/s00542-017-3550-2

TECHNICAL PAPER

Design, development and implementation of a low power and high speed pipeline A/D converter in submicron CMOS technology Muhammad Imran Khan1,2 • Affaq Qamar3 • Faisal Shabbir4,5 • Rizwan Shoukat6

Received: 4 July 2017 / Accepted: 28 August 2017 Ó Springer-Verlag GmbH Germany 2017

Abstract This research paper focuses on the design, development and implementation of a pipelined analog to digital (A/D) converter of 8 bits with sampling rate of 25 MHz in 350 nm CMOS process technology. The architecture utilizes the digital correction for each stage based on a 1.5 bit per stage structure. A differential switched capacitor circuit consisting of a cascade gm-C op-amp with 200 MHz ft is used for sampling and amplification in each stage. Differential dynamic comparators are used to implement the decision levels required for the 1.5 bit per stage structure. Correction of the pipeline is accomplished by using digital correction circuit consist of D-latches and full adders. Finally, the paper describes the floorplan and layout of design.

& Muhammad Imran Khan [email protected] 1

Department of Electronics Engineering, University of Engineering and Technology (UET), Taxila 47050, Pakistan

2

Micro-/Nano Electronic System Integration R&D Center (MESIC), University of Science and Technology of China (USTC), Hefei 230027, Anhui, China

3

School of Electrical Engineering, Abasyn University, Peshawar 25000, Pakistan

4

Department of Civil and Environmental Engineering, University of Auckland, Auckland, New Zealand

5

Department of Civil Engineering, University of Engineering and Technology (UET), Taxila 47050, Pakistan

6

Department of Microsystems Engineering, IMTEK, University of Freiburg, 79110 Freiburg, Germany

1 Introduction With advances in micro/nano technology, integrated circuits design and portable electronics, the existence of highspeed, low-power and high resolution ADCs are becoming more and more essential (Jiang et al. 2008; Abo 1999; Sun 2005; Razavi 2001; Maloberti 2007; Mallya and Nevin 1989). Variations on analog-to-digital converters are numerous; each tailored for specific performance parameters. More modern converters have implemented some form of parallel processing of the analog signal to increase bit resolution while still maintaining the same speed. Converters of this type include folding, multi-step, and pipeline (Luh et al. 2000; Choksi and Carley 2003; Hastings 2001; Samanen et al. 2002; Kamath 2004; Carter 2000). Converter architectures are still a rapidly developing area. Normally analog-to-digital converters are not strictly limited to pure flash, folding, or pipeline. Implementations with pipelined folding stages or smaller pipelined stages with a large flash section at the end are not uncommon (Carter 2000; Khan and Lin 2014a, b; Khan et al. 2014a, b). Most of these architectures are implemented as discrete converters for board level integration. With a movement toward system on chip, high performance converters are frequently implemented on the same chip with microcontrollers and other digital systems (Khan et al. 2017a, b; Shoukat and Khan 2017a, b). This introduces new noise and process problem which are not as dominant in discrete converter implementations. Additionally, processes tailored for digital logic are not the best processes to make the linear circuits required for analog-to-digital conversion but are becoming more frequently the place where converters physically take shape. With this movement toward chip level integration, it is desirable to have a converter

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architecture that is tolerant of matching and process errors as well as noise introduced by adjacent devices (Carter 2000). This paper focuses on the pipeline architecture because of its high tolerance of process variations, low power consumption, and small area making it an ideal candidate for system level integration. 1.1 System level design The initial simulations were performed using Simulink by first assuming every component to be ideal and then adding various non-idealities like comparator offset, noise, sample-clock jitter, tolerances etc. in different components to analyze their respective influence. It should be noted that system level modeling deals in functional behavior only and adopts a black box approach to internal block descriptions. Figure 1 shows the block diagram of each stage in Simulink. The output of simulation with an input sine wave is shown in Fig. 2. The smooth curve (pink) in Fig. 2 shows the input sine wave while the stair case waveform shown in yellow color shows the output of the converter. By running repeated simulations for numerous design cases and parameters, high level requirements on several of the circuit blocks can be found. The result of many simulations where the parameters for both SR and Bandwidth are swept is shown in Fig. 3. We can see from Fig. 3 that, for 7.5 bits of resolution from converter operating with a sample rate of 25 MHz, a bandwidth of about 200 MHz and slew rate about 120 V/ls is needed. The open loop gain of the amplifier determines the accuracy of the closed loop gain factor. To get an idea of how high gain is needed to reach the performance goals, the simulink model is used; the result is shown in Fig. 4. Notice that in Fig. 4, ENOB starts saturating around an open-loop gain of 1000 (60 dB) and does not increase more in respect to the gain. Therefore, a higher gain than 60 dB will not significantly increase the performance of the ADC.

Fig. 2 Output response of the pipeline ADC in Simulink

Fig. 3 ENOB of ADC vs. slew rate and bandwidth of OPA

Fig. 4 ENOB versus OPA gain

2 Design implementation

Fig. 1 Schematic of a single stage of the pipeline ADC in Simulink

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Now we are going to review the major design decisions that need to be taken into consideration to ensure that the ADC will fulfill the required specifications. Now we shall focus on the actual design implementation.

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2.1 Sample/hold circuit The S/H circuit shown in Fig. 5 is drawn in virtuoso (Cadence). C-Switches were used instead of NMOS because it is impossible to connect the bulk of NMOS transistors to their source. By using C-switch we alleviate the problem with a nonlinear signal dependent transfer function. We can see that VCM was connected with the sources of input transistors instead of ground because of the fact that we are using a single of 3.3 V as supply and VCM = 1.65 V exactly in the mid-point of the supply range. Also by definition the maximum input is allowed to vary between 1.25 and 2.05 V. The circuit was tested for the maximum input frequency at full scale which it is required to operate on e.g. 12.5 MHz which corresponds to exactly half of the Nyquist frequency (the sample rate is 25 MHz in our case). The simulation results are shown in Fig. 6 suggests that, the circuit is performing according to expectation. 2.2 Comparator design considerations In pipeline ADCs with error correction the design requirements on the comparators used in the sub-ADCs are greatly relaxed (Samanen et al. 2002). Offset is no longer a critical parameter. This simple correction algorithm can tolerate comparators offset up to ±Vref/4 in the case of a 1.5 bits per stage architecture. Dynamically latched comparators are frequently used in pipeline ADCs. In these comparators, power consumption is lowered considerably and they can be made to use positive feedback in the latch stage to not require high gains to work (Samanen et al. 2002)

Fig. 5 Sample-and-hold circuit

Fig. 6 Simulation showing sampling of the input

The comparator that was used in paper is a differential dynamic comparator and it is shown in Fig. 7. It is based on two cross coupled differential pairs with switched current sources loaded by a CMOS latch (Samanen et al. 2002). The trip point of the comparator can be set by introducing imbalance between the source coupled pairs (Samanen et al. 2002). Because of the dynamic current sources together with the latch, connected directly between the differential pairs and the supply voltage, the comparator does not dissipate DC power (Samanen et al. 2002). When the comparator is inactive the latch signal Vlatch is at 0 V, which means that the current source transistors M5 and M6 are switched off. Simultaneously the PMOS switch transistors M9 and M12 resets the outputs by shorting them to Vdd. When Vlatch is raised to Vdd, the outputs are disconnected from the positive supply, the switching current sources M5 and M6 turn on and M1–M4 compare (Vin? Vin-) with (Vref? - Vref-). Since the latch devices M7–M8 are conducting, the circuit amplifies the voltage difference at the drains of the input pairs. The threshold voltage of the comparator is determined by the current division in the

Fig. 7 Differential pair comparator (Samanen et al. 2002)

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differential pairs and between the cross coupled branches (Samanen et al. 2002). Formula for calculation of threshold voltage based on transistors widths is presented in Samanen et al. (2002) and by using this formula, we got a relation between widths of input transistors pairs M1–M4 to get the required switching voltage at Vref/4 to be W1 = W2, W3 = W4 ¼) W1/ W3 = 8. The transistors sizes are set large enough to minimize the offset voltage. Now set the length of all transistors to 1 lm and determine W/L ratio to reduce over drive voltage. In practice simulation, we did not see much sensitivity to transistor sizes. The best results were obtained at W = 20 lm for most transistors and M1–M2 are scaled to 24 lm. Figure 8 shows differential comparator built in Cadence. Two inverters are added to output to provide required fan-out. The result of simulation of one comparator that compares a sine wave with Vref = 0.8 V is shown is Fig. 9. The latch signal is set to pre charge the output to high. The out? and out- are differential outputs. When input amplitude is more than Vref/4 = 0.2, out? is set to high and out- goes to low.

Fig. 9 Simulation showing comparison of input with Vref

Transistor sizes in this section are not critical because they are digital logic. Hence we used standard values for them. In NAND and NOT logic, PMOS transistors are scaled to give comparable rise and fall times. Simulation results of DAC block are illustrated in Fig. 10. Here we apply in1 = low and in2 = low and as expected the VDAC? = Vref- = 0.8 V and VDAC- = 0 V.

2.3 DAC design considerations

2.4 Sub-ADC implementation

In the DAC section, output of two comparators is evaluated with a simple digital circuit consisting of NAND and NOT gates. Also these signals are used for analog multiplexer that acts as a digital to analog converter with three stages output. As shown in schematic, it uses NMOS transistors to switch proper voltage Vref? or Vref- at the output of DAC. The outputs are listed below:

In the Fig. 11, the simulation results of the sub-ADC part driven by a sine wave input has been shown. The sub-ADC compares the analog input against the references and generates the two digital and two analog outputs, the MSB, LSB, VDAC? and VDAC- respectively. They correspond to the level of the input value. When the input is more than the threshold voltage of Vref/4 = 0.8/4 = 0.2, then MSB goes high and LSB goes low. Furthermore, these two bits are translated to analog on VDAC? = 2.05 V and VDAC- = 1.25 V outputs. When input is less than -Vref/

Vrefþ  Vref

when Vin [ Vref =4

Vcm when  Vref =4\Vin \Vref =4 Vref  Vrefþ when Vin \ Vref =4:

Fig. 8 Schematic of differential pair comparator built in cadence

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Fig. 10 Simulation of DAC with in1 = low and in2 = low

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Fig. 11 Simulation result of sub-ADC

4 = -0.2 then MSB and LSB are low. The VDAC? = 1.25 and VDAC- = 2.05 in this case. 2.5 Op-amp design considerations Given the requirements we were able to ascertain from our high level Simulink model. We had an overview of the performance that would be required from the operational amplifier as depicted in Fig. 12. Further restrictions on our available degrees of freedom came from the recommendation that we should not use channel lengths under 1 lm for any transistor in order to match the transistors. To have some margin for parasitic capacitances, we designed an OPA to drive a load of 0.5 pF on each leg. This is in conjunction with the requirements on bandwidth and slew rate that we got from the Simulink model. The desired signal swing gave us the necessary information to

Fig. 12 Fully differential folded cascade amplifier

distribute the overdrive voltages and calculate the transistor sizes. To address the issue of the common mode feedback we started out using a continuous time common mode feedback circuit, but in order to make it stable we had to incorporate a compensation network (Luh et al. 2000). This resulted in a working design but with the added current drawn from the continuous time CMFB and the impractical size of the necessary compensation components, we decided to switch to a switched capacitor common mode feedback for our final design. The reset phase intrinsic to the pipeline architecture can be used in our design and it has an advantage to reduce the complexity of the common mode feedback (Choksi and Carley 2003). The Figs. 13 and 14 show some of the most important simulation results for the Op-amp. The open loop gain was determined to be 74.5 dB Figure 14 shows the open loop gain and phase margin of the operational amplifier plotted together. The GBW was measured to be 435 MHz, more than predicted by our model but considering the 6 dB gain for the 29 configuration used in the pipeline stages it is according to specification. The phase margin of 85° allows some losses due to parasitic components added during layout. Figure 15 shows the step response of the opamp. The slewrate was found from doing a transient analysis with an input step. By using cadence calculator, we found that the positive going slewrate was 145 V/lS and respectively the negative going slewrate was 135 V/lS. 2.6 Stage implementation of pipeline After discussing all important design components, we shall now briefly discuss the implementation of the middle stages of ADC, last stage and then the complete design and their simulations.

Fig. 13 Open-loop gain

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pipeline stage from our design as depicted in Fig. 16. An added benefit from doing this is that the three comparators provide a better load to op-amp in the penultimate pipeline stage. The drawback is that now there is no longer any error correction available for the LSB but offsets error in the comparators are alleviated by using especially large differential pair transistors for these comparators. Figure 17 shows the simulation results for the last stage. It should be noted that, this stage uses the same type of comparator as other stages, but with different scaling due to different switching thresholds. Fig. 14 Bode plot showing gain and phase margin

2.6.2 Pipeline stage Figure 18 shows the typical pipeline stage in Cadence. It consists of sub-ADC and switch capacitor amplifier. The simulation result of one stage with sine wave input is shown in Fig. 19. That shows analog output (residue) and digital outputs (msb, lsb) of stage. 2.7 Error correction

Fig. 15 Step response of opamp

2.6.1 Last stage In order to reduce the area and power consumption of the ADC, the design of the last stage was reconsidered. By using a two-bit converter instead of a simple comparator for the last stage we could remove one full

Fig. 16 Last stage of pipeline ADC without an opamp

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The schematic of D-latch is used in delay section. It is the main element of delay section. With proper number of cascading D-latches the essential delay will be made for each output stage. There is not any critical point in the design of this section and we implemented it with standard transistor size. The simulation of delay section is shown in Fig. 20. It shows how outputs are delayed and their dependability on number of D-latches. For example, the last stage with one D-latch in front has one delay and the third stage is delayed with three clocks. After aligning bits by adding some intentionally delay, we used error correction circuits to generate final 8-bits pattern. The error correction consists of eight full adders

Fig. 17 Input–output response of the last pipeline stage

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Fig. 21 Block schematic of digital correction

Table 1 Target specifications

Fig. 18 Pipeline stage

Sampling rate

25 MHz

Analog-to-digital converter (ADC)

8 bits

Process technology

0.35 lm

Maximum input bandwidth

12.5 MHz

Power supply

?3.3 V

Reference voltage

0.8 V

SNDR

47 dB

Table 2 CMOS simulations parameters 350 nm CMOS technology Minimum gate width

20 lm

Maximum gate width

160 lm

MOSFET model

BSIM3

Nominal conditions

VDD = 3.3 V Temperature = 27 °C

Fig. 19 Simulation result of one pipeline stage

Fig. 22 Schematic of whole pipeline ADC

Fig. 20 Simulation result of delay block showing one clock cycle at every output stage

which are configured as shown in Fig. 21. The carry input of each cell comes from previous stage and then it takes time to propagate carry through eight stages (it has to be less than the one period of clock frequency which is 40 ns). In this case, the design of full-adder satisfies the criteria (Tables 1, 2).

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3 Complete ADC Finally, we put whole stages together to make ADC pipeline converter, it is shown in Fig. 22. The first block in Fig. 22 (left hand) as we mentioned before is S/H, it is continued with six typical stages and finishes with last stage. The blocks on right hand show delay and digital correction. The power consumption of completed ADC without clock generator section is about 30 mW (I = 9 mA, supply = 3.3 V). Figure 22 shows plot of input and output of pipeline ADC with a ramp input that is created based on exported file. The red line is input ramp and the blue line is the output of ADC. It shows a perfect linear response, however there is a smooth offset error in result (Fig. 23). Figure 24 shows the spectra of output of completed ADC. Main frequency is 244 kHz, the second and third harmonic floor in the spectra is impressive. The value of SNDR is 47 dB in this way that gives rise to 7.5 bit ENOB. Figures 25 and 26 show the plots of simulation of output reference versus temperature and supply voltage.

Fig. 24 Spectra of output of completed ADC

3.1 Floorplan design and layout As complexity and speed of analog CMOS circuits are increasing, non-idealities in the layout limits both the speed and precision of systems. The layout of an integrated circuit defines geometries that appear on the masks used in fabrication. The geometries include m-well, active, polysilicon, n? and p? implants, interlayer contact windows, and metal layers (Razavi 2001). While the width and length of each transistor is determined by circuit design, most of the other dimensions in a layout are dictated by ‘‘design rules’’ that is a set of rules

Fig. 25 Simulation of output reference versus temperature

Fig. 26 Simulation of output reference versus supply voltage

Fig. 23 Input and output of complete ADC plotted with MATLAB

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that guarantees proper transistor and interconnect fabrication despite various tolerances in each step of processing (Razavi 2001).

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To achieve a proper layout for an integrated electronic system we should start with a floorplan that is a schematic representation of tentative placement of its major functional blocks. Actually this stage is done on paper by hand and it is not an automated stage in Cadence. We can describe the process of making layout as follow. Firstly, divide the design into stages and each stage into below parts: comparator, op-amp, DAC and logic gates in sub-ADC. The layout of each part is drawn separately and is controlled with DRC and LVS check. In drawing separate parts, we should take care about space, design rules, current and power. The next step is putting together parts of stage to make one stage of pipeline ADC. It is suggested to make the general block placement as such to not impede a congest routability between blocks (Hastings 2001) hence we have provided reasonably wide corridors between adjacent blocks. By considering which nodes have a high or low impedance, decisions on which blocks should go where could be made. External noise transfer into a node is determined by the impedance ratio between the node itself and that of the adjacent noise source. High impedance nodes are more sensitive to ambient noise than low impedance nodes. The impedance divider formed between a high impedance node and a noise source will not provide much dampening. Furthermore, since there is only one common substrate, so the capacitive coupling between Vdd/Vss is significant. The clocks as well as the analog signals are transferred through a route in differential pairs whenever to help reduce their immunity to both radiating and receiving adjacent noise. Several distributed power pins should be used to make the impedance connection between the outside world and the die low. Fortunately, the main current consumer, the op-amp operates in class-A and draws constant current, thus easing the requirements on routing and power traces. In our case, the most sensitive nodes are the sampling capacitances and the comparator inputs. Since any slight perturbance there has the potential to affect the accuracy of the converter. We strived for placing the sensitive nodes together and whenever possible drive them from low impedance outputs

Fig. 27 Floorplan of entire ADC and close up on a single pipeline stage

Fig. 28 Layout of pipeline ADC without interconnection between blocks

such as the amplifier when in hold mode. And also physically isolate them from noisy digital parts to the greatest extent possible. One step towards this goal was splitting up the DAC block into a logic block and a switch block. The logic gates could then be moved further away as illustrated in Fig. 27. Since current always flows in loops, we also have to consider the return path of any signals crossing between the analog and digital side. This is best done by ensuring low impedance connections throughout the chip. According to above floorplan, the prepared layout blocks are placed as shown in Fig. 28. The interconnection between blocks has not applied yet. Estimated area based on respective block sizes is about 600 lm 9 400 lm or 0.24 mm2. Each Stage cell is approximately 100 9 180 lm in size.

4 Conclusion In this paper, we designed an ADC with 8-bits resolution and 25 MHZ sampling frequency. We chose a pipeline ADC with 1.5 bit per stage architecture and start our design with a system level design in MATLAB/Simulink. After successful simulations, we continue our work with circuit design of different parts and simulate each part separately. Later, comparator, sample and hold amplifier, digital error correction block and band gap reference were designed. The folded cascade op-amp was designed for a gain of 74.5 dB and unity gain bandwidth of 435 MHz at a load capacitance of 0.5 pF. Furthermore, the OPA settles within 0.2% in less than 8 n and gave slew rate of about 145 V/ lS. Band gab reference circuit was discussed. The temperature and voltage independent reference circuit was simulated and shows 10 ppm accuracy for a temperature range from 0 to 80 °C.

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The power consumption of completed ADC without clock generator section was about 30 mW (I = 9 mA, supply 3.3 V). Also the result of simulation of whole ADC in CADENCE was analyzed by MATLAB script to show input–output characteristic and spectra that lead to a SNDR 47 dB and ENOB 7.5 bit.

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