Analog Integrated Circuits and Signal Processing, 11,163-171 (1996)

Static Linearity Error Analysis of Subranging A/D Converters TAKASHI OKUDA, TOSHIO KUMAMOTO, MASAO ITO, TAKAHIRO MIKI, KEISUKE OKADA, Members, AND TADASHI SUMI, Nonmember Mitsubishi Electric Corporation, ltami-shL 664 Japan

Received June 20, 1995; Revised September 20, 1995

Abstract. An 8- to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits a reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with individual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate fs and the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.

Key Words: subranging A/D converter, coarse conversion, fine conversion, linearity error 1.

Introduction

As video systems have improved, high speed, high resolution A/D converters are now required. Consumer video systems, for example, require an 8- to 10-bit CMOS A/D converter (ADC) with a conversion rate of more than 16 megasample/second (MS/s). Subranging architecture is widely used to realize such A/D converters. Two typical types of this architecture have been reported. One type has individual comparator arrays for coarse and fine A/D conversions (the ADC of this architecture is referred to as a separate ADC in this paper) [1]-[3] and the other has the same comparator array for both conversions (the ADC of this architecture is referred to as an unified ADC in this paper) [4], [5]. The coarse and fine conversions in this architecture are achieved in the same manner as the A/D conversion in a flash ADC. In this architecture, therefore, there is the same type of resistor ladder loading error which was discussed in the flash ADC by Dingwall [6]. His discussion, however, can not be applied for a subranging Copyright, 1996, 1EICE, reprinted With permission from IEICE

ADC, strictly a fine conversion, as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging ADC. This paper describes a static analysis of the resistor ladder loading error to improve static linearity. This analysis can handle fine conversion as well as coarse conversion. The results of the linearity error in the two types of subranging ADC are shown. Furthermore, this paper describes the condition which realizes 10bit accuracy. This analysis is finally verified by circuit simulation.

2. Operation of Subranging ADC A subranging ADC operates in three steps, sampling, coarse conversion and fine conversion. This cycle is repeated at the conversion rate. Figure 1 shows the connection of input part of comparator array in each step in a separate ADC. In the sampling step, an analog input voltage V,n is applied to the capacitors in the coarse and the fine comparator arrays. In the coarse conversion step, coarse reference voltages are applied

164

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Fine comparator

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Fine conversion step

Fig.1.Connectionofconversionstepsin separateADC. V R ~ V/~Comparator array VR~

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Fig.2.Connectionofconversionstepsin unifiedADC. to the coarse comparator array, and compared with Vin to decide the coarse code. The fine comparator array is standing by in this step. In the fine conversion step, according to the result of the coarse conversion, fine reference voltages are applied to the fine comparator array, and compared with Vin to decide the fine code. Figure 2 shows the connection of the input part of a comparator array in each step in a unified ADC. The first two steps are the same as those in the separate ADC, only the last fine conversion step is different. In the unified ADC, fine reference voltages are applied to the same comparator array as in the coarse conversion step and compared with V/n to decide the fine code.

3.

Analysis

3.1. Model of Input Part of Comparator Figure 3 shows a model of the input part of one comparator. The input capacitance f i n is composed of the coupling capacitance of the comparators and the parasitic capacitance of the wires, transistors etc. Assuming that after Cin is charged by the initial voltage Vo, it is switched to reference voltage v(x) at position x, then

Fig.3.Modelofinputpartofcomparator. the electric carrier C i n { U ( x ) -- V0} moves from the resistor ladder to the input capacitor. As this switching is repeated at the conversion rate fs, the static current J = f, Cin{v(x)

-

V0}

(1)

flows from the resistor ladder to the input capacitor. This model is applied to each comparator in the separate and unified ADCs. Both ADCs are analyzed in the same model, but only their initial condition and boundary conditions in the fine conversion step are different.

3.2. Model of Coarse Conversion Figure 4 shows a model of the coarse conversion. The resistor ladder and the comparators are distributed continuously in the region 0 < x < 1. Thestaticcurrentjc(x) which flows out of the extremely small region Ax is Axjc(x)

= ZXxCfs{Vc(x)

-

vi,,}

(2)

from Eq. (1). Where C is the total input capacitance of the comparator array per unit length, Vc(X) is the

Static Linearity Error Analysis of Subranging A/D Converters

.

165

ji(x)

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1

.

.

x+ Ax

.....

~

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x+Ax X

0 Fig. 4. Model of coarse conversion.

Fig. 5. Model of fine conversion.

voltage distribution function along the resistor ladder in the coarse coversion step and V/n is the analog input voltage which initially charges the input capacitors in this step. At the adjacent position x on the resistor ladder, these equations

tinuously in the region 0_
ic(X -t- Ax) - ic(X) = AXjc(X) vc(x + Ax) - Vc(X) = AxRic(X)

(3) (4)

are satisfied, where ic(X) is the current flow at position x on the resistor ladder, and R is the total ladder resistance. From Eqs. (3) and (4), the second differential equation d2vc(X)

dx 2 -- Rjc(X)

(5)

is obtained. Equation (5) satisfies the boundary conditions, vc (0) = 0

(6)

Vc(1) = VR.

(7)

Where VR is the maximum ladder-tap voltage.

3.3. Model of Fine Conversion Figure 5 shows a model of the fine conversion. The resistor ladder and the comparators are distributed con-

AxjI,(x)

AxC

= L Xl

i

X0

{Vis(X) - v ~ . } ,

(8)

where jfs (x) is the current density out of the resistor ladder in the separate ADC, and vfs (x) is the voltage distribution function along the resistor ladder in the fine conversion step. In the same way as Eq. (5) was derived, the second differential equation

d2vfs(X) dx 2 - Rjfs(X)

(9)

is obtained. Equation (9) satisfies the boundary condi-

166

Okuda, Kumamoto, Ito, Miki, Okada, and Sumi

tions

3.4. 1 dvys (x) x=xo - Vys (xo) R dx xoR

(10)

1 dvys(X) x=x, - V R - rye(X1) R dx (1 - x l ) R

(11)

These boundary conditions come from the restriction that the current along the resistor ladder must be continuous at the boundaries, x = x0 and x = xl. In Eqs. (10) and (11), the left side is the current inside the boundary obtained by differentiating the current along the resistor ladder and the right side is the current outside the boundary obtained from Ohm's law. In the unified ADC, because the same comparator array is used in both the coarse and fine conversion steps, the capacitors are initially charged by the coarse reference voltages (0 to VR) in the previous step. In the fine conversion step, these voltages are applied to the ladder-taps in the region (xl -x0). The voltage applied to the ladder-tap at position (x - x0) is, thus, VR(X

Vo(x) -

X1

-

-

-

xo)

X0

(12)

From Eqs. (1) and (12), the static current out of the region Ax on the resistor ladder in the fine conversion step is AxC Axjfu (x) -- - fs X 1 X0 -

-

XlPfu(X )

VR(---X--~X0) } X __ X0 l

(13)

where Jfu (x) is the current density out of the resistor ladder in the unified ADC, and vfu (x) is the voltage distribution function along the resistor ladder in the fine conversion step. Again in the same way as Eq. (5) was derived, the second differential equation d 2 Vfu (X) dx 2 = Rjfu(x)

The static error voltage along the resistor ladder is usually much smaller than the ideal reference voltage. This error, therefore, causes only a negligible current from the resistor ladder. The voltage distribution functions, vc(x), Vfs(X), and vfu(x) in Eqs. (2), (8) and (13) respectively, are replaced by the ideal voltage distribution, x VR. Equations (2), (8) and (13) can be, therefore, approximated by

Axjfs(x) = fs

AxC X1 -- XO

(15)

1 dvfu(x) x = x i - V R - vfu(Xl) R dx (1 - Xl)R

(16)

with the same restrictions as in Eqs. (10) and (11).

(18)

(xVR -- Vin)

AxC Axjfu(X) -- - fs X 1 -- X 0 x IxV R

VR(X __--XoXO)

,

(19)

respectively. This approximation means that the terms over the 4th order in the exact solutions are neglected. Solving the differential equations (5), (9) and (14) under each boundary condition with these equations (17), (18) and (19), the voltage distribution function along the resistor ladder in each conversion step is obtained. In the coarse conversion, from Eqs. (5) and (17) and the boundary conditions (6) and (7), the voltage distribution function Vc(X) is Vc(X) = xVR + C L R

n)xt20'

In the fine conversion of the separate ADC, from Eqs. (9) and (18) and the boundary conditions (10) and (11), the voltage distribution function vf~ (x) is = xVR +

xl - xo

is obtained. In this case, boundary conditions which Eq. (4) satisfies are 1 dvfu(X) x = x o - Vfu(XO) R dx xoR

(17)

A x L ( x ) = fsZXxC(xVR - Vin)

vf,(x)

(14)

Solution o f Equations

X 3 -- ~ " x 2

2

12 Xl)}X +-~--x o In the fine conversion of the unified ADC, from Eqs. (14) and (19) and the boundary conditions (15)

Static Linearity Error Analysis of Subranging A/D Converters

and (16), the voltage distribution function Vfu (x) is

v,u(x)

XVR+ x

CfiRVR (Xl - X0) 2

1 -- (X 1 -- X0)X3 -~- XOx 2 6 2

(22)

4.

Linearity Error

The voltage distribution functions (20), (21) and (22) along the resistor ladder in each conversion cause linearity errors. In a case where the reference voltage is distributed ideally, v(x) = XVR, if one analog input voltage V/n = xVn is applied, then the ADC outputs the ideal digital code corresponding to position x on the resistor ladder. But in a case where the voltage distribution functions are not ideal, that is, where a resistor ladder loading error exists, even if the same analog input voltage is applied, the ADC does not output the ideal digital code. The difference of tap-voltages which causes the difference of codes is defined as the linearity error. Figure 6 shows the linearity errors of the 10-bit ADC (5 coarse-bit and 5 fine-bit) as a function of the laddertap position, which is calculated from Eqs. (20), (21) and (22). Because these errors are the results of static analysis, they are obtained as average errors. The total static linearity error is, therefore, obtained by adding the coarse and fine average errors with the superposition theorem. In this figure, (xl - x0) is 1/25 which is 1LSB for the coarse conversion and the product of the total input capacitance (C), the conversion rate (fi) and the total ladder resistance (R) is 0.04. Figure 6(a) shows the results of the separate ADC and Fig. 6(b) shows the results of the unified ADC. The shapes of these errors are caused by the total amount of static current out of the resistor ladder. The coarse linearity error has negative polarity be-

167

low the middle point and positive polarity above the middle point on the resistor ladder. When an analog input voltage below half VR(Vin < 0.5 VR) is applied as an example, the static current flows into the ladder-taps, whose voltages are smaller than V/n, from the input capacitors and flows out of the ladder-taps, whose voltages are larger than Vin, to the input capacitors. The total amount of current which flows into the resistor ladder from the input capacitors is, therefore, smaller than the total amount which flows out of the resistor ladder to the input capacitors. As a result, the laddertap voltage which is the nearest to V/, decreases, that is, the polarity of error at this point is negative. The other cases (V/, = 0.5VR and V/, > 0.5VR) can be considered in the same way. As a result, the result of coarse linearity error is obtained as in Fig. 6. The fine linearity error has a saw-tooth characteristic which has 32 discrete points. The number of discrete points depends on the number of coarse bits. In the fine conversion of the separate ADC, within the region of each fine conversion, static current out of the resistor ladder is considered in the same way as the coarse conversion. When Vin below the reference voltage at the middle point in this region is applied, the total amount of current out of the resistor ladder is larger than the amount of total current into the resistor ladder. As a result, the error below the middle point is negative. Similarly, the other cases Vin equal to or above the reference voltage at the middle point in this region) are considered. In every region of the fine conversion, the error is caused in the same way, so the saw-tooth characteristic is obtained as in Fig. 6. Especially in the fine conversion of the unified ADC, in addition to this saw-tooth characteristic, an additional error exists. This error is caused by the fact that the same comparator array is used in the coarse and the fine conversion. In the fine conversion, the input capacitors in the comparator array are initially charged by the coarse reference voltages in the previous step. When Vin is smaller than 0.5 VR, as an example, the total amount of current which flows into the resistor ladder from the input capacitors is larger than the total amount which flows out of the resistor ladder to the input capacitors. As a result, the ladder-tap voltage which is the nearest Vi~ increases, that is, the polarity of error at this point is positive. Similarly, the other cases (V~.~ = 0.5 VR and V/n > 0.5 VR) c a n be considered. As the result, the characteristic of this fine linearity error shows opposite polarity to the coarse linearity error as in Fig. 6(b).

Okuda, Kumamoto, Ito, Miki, Okada, and Sumi

168

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5.

Cfs R Dependence on Linearity Error

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x (4Xmax u (Xmax u - - 1) --~-(X1 -- XO)

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(24)

ADCs and that CfsR is under 0.016 in unified ADCs in order to obtain 10-bit accuracy.

at 1 Xraax

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6.

Verification of Analysis

--

2

4- 1 f f 1 2 - 12(xl - x0){1 + 2(xl - xo)}. From Eqs. (23) and (24), it is clear that the maximum linearity error is proportional to CfsR. These equations define the conditions necessary for obtaining the desired accuracy in a subranging ADC. Figure 7 shows, as an example, the CfsR dependence of the maximum linearity error on a 10-bit ADC. It is necessary that CfsR is under 0.030 in separate

This analysis is verified by circuit simulation. Figure 8 shows the circuit in the simulation for the unified ADC. This figure shows the case where the lowest fine-taps are selected. Vrc and Vrf o n the resistor ladder are respectively coarse and fine reference voltages. The voltages VR and Vin are respectively the maximum ladder-tap voltage and the DC input voltage, Cc is the coupling capacitance, Csl is the parasitic capacitance of the wires and the switches, and Cs2 is the parasitic capacitance of the amplifier. Transmission gates are

Static Linearity Error Analysis of Subranging A/D Converters

169

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used as the switches. The timing chart qbl, q~2, q53) in each step is illustrated too. In this simulation, R is 500f2, Cc is 0.2 pF, and Csl, Cs2 are 0.03 pF, 0.046 pF respectively. Figure 9 shows the linearity errors of a 10-bit unified ADC (5 coarse-bit and 5 fine-bit) calculated with this analysis and circuit simulation. The dashed line represents the result of this analysis and the solid line represents the simulated result. The result of this analysis is the same as in Fig. 6(b). The simulated result is obtained from the transient wave-forms of the tap-voltages. The average of the transient wave-forms for DC analog input voltage is plotted in Fig. 9. The simulated result represents the similar sawtooth characteristic as the result of this analysis. The maximum difference of these results is 0.15LSB. Figure 10 shows the maximum linearity error plotted as a function of fs. Solid line is the result of this analysis and dots are simulated result. The result of this analysis is the same as Fig. 7. These figures show

'

0.2

(,

0.0 0

9 4

8

ysis I-" Simulation.

,I

12

16

20

f~ [MHz] Fig. 10. Maximum linearity errors of analysis and simulation.

that this analysis is valid. 7.

Conclusion

Static linearity errors of a subranging ADC have been reported. With respect to the two types of subranging ADC, the following have been clarified. (1) There is a saw-tooth characteristic in the fine linearity error which has been shown for the first time by this analysis. (2) In a unified ADC, the fine linearity error has opposite polarity to the coarse linearity error. (3) The linearity error is proportional to the product

170

Okuda, Kumamoto, Ito, MikL Okada, and Sumi

Cfs R and to obtain 10-bit accuracy it is necessary that Cfs R is under 0.030 in a separate ADC and under 0.016 in a unified ADC.

Acknowledgements The authors would like to thank Dr. Y. Horiba for his encouragement.

References 1. A.G. E Dingwalland V.Zazzu, "An 8-MHzCMOSsubranging 8bit A/D converter." IEEE J. Solid-State Circuits SC-20(6), pp. 1138-1143, Dec. 1985. 2. T. Matsuura, T. Tsukada, S. Ohba, E. Imaizumi, H. Sato, and S. Ueda, "An 8bit 20 MHz CMOS half-flash A/D converter." 1988 ISSCC, pp. 220-221, Feb. 1988. 3. N. Fukushima, T. Yamada, N. Kumazawa,Y. Hasegawa, and M. Soneda, "A CMOS 40 MHz 8b 105 mW two-step ADC." 19891SSCC, pp. 14-15, Feb. 1989. 4. S. Hosotani, T. Miki, A. Maeda, and N. Yazawa,"An 8-bit 20MS/s CMOS A/D converterwith 50-mWpowerconsumption." 1EEEJ. Solid-State CircuitsSC-25(1),pp. 167-172,Feb. 1990. 5. M. Ito, T. Miki, S. Hosotani, T. Kumamoto, Y. Yamashita, M. Kijima, T. Okuda, and K. Okada, '~ 10 bit 20 MS/s 3V supply CMOS A/D converter." IEEE J. Solid-State Circuits SC-29(12), pp. 1531-1536, Dec. 1994. 6. A. G. F. Dingwall, "Monolithic expandable 6 bit 20 MHz CMOS/SOSconverter."1EEEJ. Solid-State CircuitsSC-14(6), pp. 926-932, Dec. 1979.

Toshio K u m a m o t o was born in Osaka, Japan on May 15, 1960. He received the B.S. and Dr. degrees in electrical engineering from University of Osaka Prefecture, Sakai, Japan, in 1983 and 1991, respectively. In 1983 he joined Mitsubishi Electric Corporation, Itami, Japan, where he has been engaged in research and development of high-speed A/D converters. From 1985 to 1987, he was engaged in research and development of three-dimensional LSIs. Presently, he is with the System LSI Laboratory.

Masao Ito was born in Fukuoka, Japan on March 16, 1966. He received the B.S. degree in electric and electronics engineering from Kobe University, Kobe, Japan, in 1989. In 1989 he joined the LSI Laboratory, Mitsubishi Electric Corporation, Itami, Japan. Since then he has been engaged in research and development of high-speed CMOS A/D converters. He is currently with the System LSI Laboratory, Mitsubishi Electric Corporation, Itami, Japan.

Takashi O k u d a was born in Hiroshima, Japan on November 7, 1968. He received the B.S. and M.S. degree in Physics from Science University of Tokyo, Noda, Japan, in 1991 and 1993, respectively. In 1993 he joined the System LSI Laboratory, Mitsubishi Electric Corporation, Itami, Japan, where he has been engaged in research and development of high-speed CMOS A/D converters.

Takahiro Miki was born in Kobe, Japan, in 1957. He received the B.S., M.S. and Ph.D. degrees in electri-

Static Linearity Error Analysis of Subranging A/D Converters

171

cal engineering from Osaka University, Suita, Japan, in 1980, 1982 and 1994 respectively. In 1982 he joined the LSI laboratory, Mitsubishi Electric Corporation, Itami, Japan. Since then he has been engaged in the design of high-speed A/D and D/A converters. Since 1993, he has been with System LSI Laboratory.

Keisuke Okada was born in Osaka, Japan, in 1953. He received the B.E. degree from Osaka University in 1977 and the M.E. degree from Utah State University, 1986. In 1977 he joined the LSI laboratory, Mitsubishi Electric Corporation, Itami, Japan, where he engaged in research and development of LSI testing and signal processing VLSI design. Since 1993 he has been with the System LSI Laboratory, Mitsubishi Electric Corporation, where he is working on the design of video signal processing LSI.

Tadashi Sumi was born in Japan, on May 19, 1948. He received the B.S. and M.S. degree in electronic engineering from Kyoto University, Kyoto, Japan, in 1971 and 1973. He joined the Kita-Itami Works, Mitsubishi Electric Corporation, Itami, Japan, in April 1973. From 1973 to 1992 he had been engaged in the design of NMOS and CMOS static RAM from 1K bit upto 4M bit. From 1992 to 1993 he was in the strategic product planning department and responsible for telecommunication area. He moved to the LSI laboratory in 1993, and since then he has been involved in image processing LSIs, networking LSIs, display processing LSIs and so on. He is currently a Department Manager in logic LSIs for multimedia application of the system LSI Laboratory.