ISSN 1063-7397, Russian Microelectronics, 2007, Vol. 36, No. 5, pp. 342–352. © Pleiades Publishing, Ltd., 2007. Original Russian Text © A.S. Gumenyuk, Yu.I. Bocharov, 2007, published in Mikroelektronika, 2007, Vol. 36, No. 5, pp. 390–400.

CIRCUIT DESIGN

Sample-and-Hold Circuits for High-Speed A/D Converters A. S. Gumenyuk and Yu. I. Bocharov Moscow Engineering Physics Institute (State University), Moscow, 115409 Russia e-mail: [email protected] Received March 20, 2007

Abstract—The design of sample-and-hold circuits (SHCs) for pipelined analog-to-digital converters (ADCs) fabricated in CMOS technology is considered. The most important errors in SHCs of various types are analyzed and methods for their reduction are described. Examples of SHCs for a 1.8-V, 20-M sample/s pipelined 0.18-µm-CMOS ADC are presented. PACS numbers: 84.30.Vn DOI: 10.1134/S1063739707050083

and evaluate the influence of nonideality of components on the final accuracy of SHCs.

INTRODUCTION Sample-and-hold circuits (SHCs) are intended to hdd an analog signal value for a certain time required for the signal processing. These circuits are most widely used in analog-to-digital converters (ADCs) of the pipeline type. Figure 1 shows a schematic diagram of the typical multistage pipelined ADC with 1.5-bit differential stages, each provided with an SHC.

THE BASE SHC DESIGN AND THE MAIN SOURCES OF ERRORS A scheme depicted in Fig. 2 serves a base for all other SHC configurations, but it is never used as such in ADCs because of insufficient accuracy. The most important sources of errors are as follows.

A broadband input SHC allows the ADC to be used in an undersampling mode for the conversion of singleended signals into differential signals. The SHC parameters determine the resolution and dynamical characteristics of ADCs.

(i) The CMOS switch introduces nonlinear distortions into the output signal, since its conductivity in the closed state depends on the input signal level as

In a view of this critical significance of the SHC parameters, it is important to consider the main principles of their design, reveal the main sources of errors,

W g ds = µC ox ----- ( V g – V in – V th ) , L

Stage

K1 +Σ

SHC

×2

SHC

K2

K3

Kn ...

Signal input ADC Synchronization input

DAC Resolution: 1.5 bit

Digital error correction circuit and interface Output Fig. 1. Schematic diagram of the typical pipelined ADC illustrating the use of SHCs.

342

DAC

...

SAMPLE-AND-HOLD CIRCUITS FOR HIGH-SPEED A/D CONVERTERS Vg

343

F1d

Vout

Vout

Vin

Vin

M1

CS

CS

F1

Fig. 2. Simple SHC.

M2

F1 F1d

Fig. 3. SHC with both top- and bottom-plate sampling

V th = V th0 + γ ( ( V in – V b ) + 2 ϕ F –

ϕF ).

where µ is the electron mobility in the transistor channel; ëox is the specific capacitance of the gate insulator; W and L are the width and length of the transistor channel, respectively; Vg is the gate voltage in the open MOS-switch transistor; Vin is the input signal voltage; Vth0 is the threshold voltage for a zero body-to-source voltage; γ is the body factor; ϕF is the surface potential in the strong inversion mode; and Vb is the substrate potential. As can be seen, the input signal level influences the open-switch resistance both directly and via a change in the threshold voltage level. (ii) The switching transistor has a nonlinear junction capacitance relative to the body:

MOS switch channel resistance and the storage capacitance) varies depending on the input signal level.

C j0 , C j = ----------------------------1 + V bs /ϕ F

(iv) There is charge injection when the transistor is sharply switched off. The mobile carriers escape from the channel in the source and drain regions, thus introducing a sampling error [2–4]. Assuming that (in the worst case) all this charge will pass to the capacitance CS, we can estimate the related error as

where ëj0 is a constant and Vbs is the source–body voltage. For this reason, the attenuation and phase retardation introduced by the low-pass RC filter (formed by the

(iii) There is a direct charge feedthrough into the sampling chain via the gate–source and gate–drain capacitance [1]. This linear effect introduces an error that can be estimated as C gd0 -V , ∆V = ---------------------C S + C gd0 g where ëgd0 is the total gate–source and gate–drain capacitance.

C ox - ( V – V in – V th ) . ∆V S = WL ------CS g There are additional common errors inherent in most SHCs irrespective of their particular configurations: (
) the thermal noise of capacitors, which is characterized by the average power ν2 = kT/C, where k is the Boltzmann constant, T is the absolute temperature, and C is the capacitance; (
) the aperture jitter of the control signal, which is related to uncertainty of the moment of SHC switching from the sampling to holding mode. (
) the dependence of the capacitance of some MOS structures on the applied voltage; RUSSIAN MICROELECTRONICS

Vol. 36

No. 5

2007

(
) the effects of charge absorption and relaxation in the dielectric material of capacitors and the transient threshold voltage shifts in MOS transistors [5–7]. METHODS FOR DECREASING ERRORS IN THE BASE SHC SCHEME The charge injection errors can be reduced by introducing an additional switch (Fig. 3) into the base SHC scheme. Here, the sampling capacitor is switched not only from the upper plate side (connected to the input signal chain), but from the lower plate as well (bottom

344

GUMENYUK, BOCHAROV

VinP

F1d

CS F2

F1

VoutP

+ Vref

F1 – F1

F2

VoutN

VinN F1d

CS

Fig. 4. SHC with flip-around capacitors.

plate sampling). As long as the control signals F1 and F1d are on a high level, the output voltage of the sampling capacitor repeats that at the SHC input. When F1 switches to a low level, the switch based on transistor M2 is closed and the capacitor charge is fixed on a level of q = CSVin. The floating state of the capacitor prevents the charge from variation. When F1d also switches to a low level and closes the switch based on transistor M1, the injection cannot change the charge stored in the sampling capacitor. Errors related to a finite resistance of the MOS transistor channel in the closed state of the switch can be reduced by using more complicated (bootstrapped) switches [8, 9]. Errors caused by the direct charge feedthrough to the sampling chain via the junction capacitance, as well as the errors related to other parasitic capacitors can be decreased using an SHC with a differential architecture. This design is based on fully differential operational amplifiers (opamps), typically with current outputs. A specific feature of such opamps is the presence of an incorporated feedback chain (typically based on switching capacitors) with respect to the commonmode signal. This feedback makes the level of the common-mode component of the output signal close to the level of a reference voltage applied to a special input [10]. The necessary level of the common-mode component of the output signal can be set in the absence of feedback for the differential signal. Numerous variants of the SHC design have been proposed, which make use of the aforementioned methods of error reduction. Most of these SHC variants are based on the two main configurations: with flip-around capacitors [11] and with charge redistribution [12] in a fully differential analog circuit. The latter scheme can be implemented using either a shared capacitor [13] or a time-shifted correlated double sampling technique [14].

SHCS WITH FLIP-AROUND CAPACITORS SHCs with flip-around architecture (Fig. 4) have a switching capacitor in each half of the differential scheme. The signal plates of both capacitors are connected to the input in the sampling mode, and to the output in the holding mode. A change in the mode involves alternation of the direction of connection, while the charges remain unchanged. For this reason, SHCs of this type have a unity transmission coefficient. In the sampling mode, F1 and F1d switches are closed, while F2 switches are open; in the holding mode, F2 switches are closed, while F1 and F1d switches are open. In order to reduce errors, this scheme employs the aforementioned method of both top- and bottomplate sampling: upon going to the holding mode, F1 switches are closed before F1d, which prevents uncontrolled charge injection into the capacitors. Figure 5 shows the equivalent schemes of the SHC with fliparound capacitors in the sampling and holding modes. Upon termination of the sampling time, the charges of CS capacitors are qP = (Vref – VinP)CS, qN = (Vref – VinN)CS, where VinP, VinN are the input signals and Vref is the reference voltage (here and below, the subscripts N and P refer to signals in the parts of the opamp scheme related to the noninverting and inverting inputs, respectively The amplifier is not provided with feedback for the differential signal, but the Vout, cm voltages are established approximately equal to Vref because an internal common-mode feedback is present and the outputs are interconnected. In the holding mode, the capacitors are disconnected from the input and connected to the feedback chain of the amplifier. For a sufficiently large differential gain of the opamp, the input potentials can be considered RUSSIAN MICROELECTRONICS

Vol. 36

No. 5

2007

SAMPLE-AND-HOLD CIRCUITS FOR HIGH-SPEED A/D CONVERTERS CS

345

CS

VinP VoutP

VoutP

+

X

+

–

X

–

Vref VoutN

VoutN

VinN CS

CS

Fig. 5. Equivalent schemes of an SHC with flip-around capacitors in the (a) sampling and (b) holding modes.

F1d

CP

C

VinP F1

F2

Vos + A0

Vref

VoutP F1

– F1 CP

VinN F1d

F2

VoutN

C + dC

Fig. 6. Equivalent scheme of an SHC with flip-around capacitors, indicating the main error sources.

approximately equal. Denoting this input potential X, the charges of capacitors in the holding mode ca be expressed as

where ∆Vout = ∆VoutP – ∆VoutN and ∆Vin = ∆VinP – ∆VinN. This circumstance accounts for the SHC operation with a unity transmission coefficient for the differential signal component.

q 'P = ( X – V outP )C S , ESTIMATING THE ERROR OF SHCS WITH FLIP-AROUND CAPACITORS. q 'N = ( X – V outN )C S . The charges of capacitors remain unchanged upon switching from the sampling to holding mode: q P = q 'P ,

q N = q 'N .

For this reason, the differential components of the input and output signals are also the same: ∆Vout = ∆Vin, RUSSIAN MICROELECTRONICS

Vol. 36

No. 5

2007

Figure 6 shows the equivalent scheme of an SHC with flip-around capacitors and indicates the main elements characterizing the error sources: A0 is the opamp gain; Vos is the opamp bias voltage; ëp is the total parasitic capacitance at the opamp input; and dC is the difference of sampling capacitors (dC/C
1). Figure 7 shows the equivalent schemes of this SHC, indicating the main error sources in the sampling and holding modes. By analogy with the above considerations, we obtain the following relations:

346

GUMENYUK, BOCHAROV CP

(a)

(b)

CP

C

C

VinP

+

XP

+ Vref

VoutP

Vos

VoutP

Vos

A0

A0 –

XN

–

VoutN

VoutN

CP VinN

C + dC

C + dC

CP

Fig. 7. Equivalent scheme of an SHC with flip-around capacitors, indicating the main error sources in the (a) sampling and (b) holding modes.

( V ref – V inP )C + V ref C P = ( X P – V outP )C + X P C P , ( V ref – V inN ) ( C + dC ) + V ref C P = ( X N – V outN ) ( C + dC ) + X N C P , 1 X P + V os – X N = ------ ( V outN – V outP ). A0 Taking into account that V outP + V outN ≈ 2V ref , 1 --------------------------- ≈ 1 – ( dC/C ) , 1 + ( dC/C ) we obtain the following approximate expression for the differential components of the output signals:

∆V in – V os ( 1 + C P /C + C P dC/(2C ) ) -. ∆V out ≈ ---------------------------------------------------------------------------------------2 1 + ( 1/ A 0 ) ( 1 + C P /C + C P dC/(2C ) 2

This relation indicates that, for CP
C, the difference of capacitances is the least significant source of error, while the maximum contribution to the total error is due to the opamp bias voltage. This source of error can be eliminated using a scheme depicted in Fig. 8. According to this, the SHC outputs in the sam-

pling mode are disconnected from the opamp and connected to the source of a constant reference voltage Vref; the opamp is provided with feedback, and the sampling capacitors CS store the input signals with the opamp bias voltage, which allows this error to be compensated. RUSSIAN MICROELECTRONICS

Vol. 36

No. 5

2007

SAMPLE-AND-HOLD CIRCUITS FOR HIGH-SPEED A/D CONVERTERS F2

VoutP F1

CS

F1d

VinP

347

F2

F1

+ Vref – F2 VinN

F1d

F1

F1

CS

VoutN

F2 Fig. 8. SHC with compensated opamp offset.

Vref

VinP

F1d

F1d

CF

CS

F2

F1

VoutP

+ F2

Vref

F1 F1

– F2

VoutN

VinN CS

F1d

CF

F1d Vref

Fig. 9. SHC with charge redistribution.

SHCS WITH CHARGE REDISTRIBUTION The SHCs with transmission coefficients different from unity are implemented using schemes with charge redistribution (Fig. 9) or with a common switching capacitor (Fig. 10). The SHC with charge redistribution (Fig. 9) in the sampling mode has F1 and F1d switches closed and F2 switches open. In this mode, the capacitors ëS are charged up to the input signal level, while capacitors CF are completely discharged. In the holding mode (where F1 and F1d switches are open and F2 switches are closed), capacitors ëS are connected in series and the charge is redistributed between ëS and CF. By analogy with the scheme considered above, we can determine RUSSIAN MICROELECTRONICS

Vol. 36

No. 5

2007

the transmission coefficient of the idealized SHC for a differential signal as ëS/CF. The SHC with a common switching capacitor (Fig. 10) also employs the principle of charge redistribution. A difference from the preceding case consists in that the input signal in the sampling mode charges both CF and CS capacitors, which leads to a faster signal establishment on the passage to the holding mode and provides a higher gain (1 + ëS/CF) for the same parameters of capacitors. The SHCs with flip-around capacitors and charge redistribution are usually employed in the entrance stages of ADCs. The SHC with flip-around capacitors is characterized by lower energy consumption and

348

GUMENYUK, BOCHAROV F1d VinP

F1d

CF

CS

F2

F1

VoutP

+ F2

Vref

F1 –

F1

F2

VinN F1d

CS

VoutN

CF

F1d

Fig. 10. SHC with a shared switching capacitor.

noise level, but the differential amplifiers used in this system must possess higher characteristics for the common-mode signals as compared to the analogous characteristics of opamps used in SHCs with charge redistribution [11]. The SHCs with a shared capacitor serve as a basis of multifunction digital-to-analog converters (DACs) entering into pipelined ADCs. Such DACs perform, in addition to their main function, the operations of subtraction and amplification of their differential signals.

ESTIMATING THE ERROR OF SHCS WITH CHARGE REDISTRIBUTION. Figure 11 shows the equivalent scheme of an SHC with charge redistribution and indicates the main elements characterizing the error sources, which are related to nonideality of the opamp: A0 is the finite opamp gain; Vos is the zero voltage shift; and Cp is the total parasitic capacitance at the opamp input. From the condition of charge conservation on the passage from the sampling to holding mode, we obtain the following relations:

C S ( V ref – V inP ) + C p V ref = ( X P – Y )C S + C F ( X P – V outP ) + C p X P , C S ( V ref – V inN ) + C p V ref = ( X N – Y )C S + C F ( X N – V outN ) + C p X N , 1 X P + V os – X N = ------ ( V outN – V outP ), A0 where Y is the potential of the common point of CS capacitors in the holding stage.

Using these relations, we obtain the following approximate expression for the differential components of the output signals:

( C S /C F )∆V in – V os ( 1 + C S /C F + C p /C F ) ∆V out = -----------------------------------------------------------------------------------------------. 1 + ( 1/ A 0 ) ( 1 + C S /C F + C p /C F )

This relation indicates that the differential output signal is independent of the reference voltage Vref

(which determines the level of the common-mode component at the SHC output). It can be readily shown that RUSSIAN MICROELECTRONICS

Vol. 36

No. 5

2007

SAMPLE-AND-HOLD CIRCUITS FOR HIGH-SPEED A/D CONVERTERS

349

Vref Cp F1d

CS

F1d

CF

VinP F1

F2

VoutP

Vos +

F2

Vref

A0

F1

– F1

VoutN F2

VinN F1d

CS

CF

Cp

F1d Vref

Fig. 11. Equivalent scheme of an SHC with charge redistribution, indicating the main error sources.

Allowance for the effect of a difference of capacitances CS and CF in this scheme with a unity gain (CF = C, CS = C + dC) yields the following formula:

an error related to the common-mode component of the input signal in this scheme can be ignored even for a relatively small common-mode signal attenuation ensured by the opamp.

∆V in ( 1 + dC/C ) – V os ( 2 + C p /C + dC/C ) ∆V out = ---------------------------------------------------------------------------------------------------. 1 + ( 1/ A 0 ) ( 2 + C p /C + dC/C ) It should be noted that errors introduced by the switching elements are virtually the same for all SHC

schemes with differential architecture considered above. The charge injection can be suppressed to a conVref Cj CS

Rp

VinP

Vsp Vref Rp

Vsn

VinN Cj

CS

Vref

Fig. 12. An equivalent scheme used to evaluate the errors due to switch resistance in the closed state. RUSSIAN MICROELECTRONICS

Vol. 36

No. 5

2007

350

GUMENYUK, BOCHAROV

Dynamic and noise characteristics of SHCs SHC type

SHC time constant

Thermal noise

Flip-around capacitors

(CINCL + CINCS + CSCL)/gmCS

kT/CS

Charge redistribution

(CFCL + CFCEQ + CSCL)/gmCF

kT/CS

Shared capacitor

(CFCL + CFCEQ + CEQCL)/gmCF

kT/(CS + CF)

siderable extent owing to the symmetry of this scheme and using the aforementioned method of both top- and bottom-plate sampling for CS and CF. In addition, the use of a differential architecture substantially decreases the direct charge feedthrough to the input circuit via the gate–source and gate–drain capacitances of the switching MOS transistors. The error related to a finite resistance of switches in the closed state can be evaluated using an equivalent

scheme depicted in Fig. 12. In the sampling mode, the switches are characterized by the resistance Rp and the total parasitic capacitance Cj, which is connected to a dc source (for certainty, Vref). Assuming that this scheme is the input part of an SHC with charge redistribution, which has no other sources of error except for the one under consideration, the influence of the resistance and the parasitic capacitance of the switch on the differential component of output signal is evaluated as

CS + C j 1 - --------------------------------------------- . ∆V out = ∆V in ----------------C F 1 + jωR p ( C S + C j ) This relation reveals a contradictory character of requirements to the input switches of broadband SHCs. Indeed, it is necessary to provide for their minimum resistance in the closed state at a limited size of MOS transistors, which is necessary to minimize the parasitic capacitance. This problem is conventionally solved using bootstrapped switches. DYNAMIC AND NOISE CHARACTERISTICS OF SHCS The operation speed and noise characteristics of SHCs are limited by the corresponding parameters of opamps. However, the SHC structure, in turn, determines both the capacitive load of an opamp (and, hence, its operation speed) and the additional thermal noise introduced by the SHC capacitors. A comparative analysis of the operation speed of SHCs with fliparound capacitors and charge redistribution was performed in [15]. In a similar manner, it is possible to evaluate the operation speed of an SNC with a shared capacitor. The results of estimation of the time constant characterizing the rate of signal variation at the SHC output and the level of thermal noise caused by the capacitors are presented in the table, where ëL is the load capacitance; ëS, CF are the sampling and holding capacitors, respectively; ëIN is the input parasitic capacitance of the opamp; CEQ = CIN + CS; and gm is the opamp transconductance. As was noted above, the

scheme with a shared capacitor ensures a faster settling of signals on the passage to the holding mode than does the scheme with charge redistribution (for the same gain exceeding unity). In addition, the thermal noise introduced by the parasitic capacitance is also lower in the SNC with a shared capacitor. PRACTICAL APPLICATION The results presented were used in designing SHCs for a 7-bit 20-Msample/s pipelined ADC with a 1.8-V supply. This ADC has to be the main unit of a multichannel system-on-chip (involving up to 128 channels) and, therefore, minimization of the power consumption is among the main tasks. The ADC has a fully differential architecture based on 1.5-bit stages. The SHC at the ADC entrance was designed using a scheme with charge redistribution analogous to that depicted in Fig. 9. The sampling capacitors (0.8 pF) were based on a metal–metal structure with 5 and 6 metallization layers, which ensured their good matching. All switches (except for the input) were based on n-channel 4.0/0.18-µm CMOS transistors. The input switches were designed using a scheme with bootstrapping [9]. The SHC was based on a differential opamp implementing switched-capacitor common-mode feedback (Fig. 13) with the following parameters: differential gain, 62 dB; bandwidth, 190 MHz; current consumption, 780 µA. RUSSIAN MICROELECTRONICS

Vol. 36

No. 5

2007

SAMPLE-AND-HOLD CIRCUITS FOR HIGH-SPEED A/D CONVERTERS

351

Vb0

Vdd

VinN

VinP

VoutP

VoutN

Vb1

Vb2

F2

F1

F1

F2d

F1d

F1d

F2

Vref

Vb2

Vref F2d

Fig. 13. Schematic diagram of the differential opamp used in the proposed SHC.

Fig. 14. Layout of the SHC used at the ADC front end.

Figure 14 shows the SHC layout. The project was realized on a technological basis of the UMC Company using 0.18-µm-CMOS analog, digital, and RF components.

RUSSIAN MICROELECTRONICS

Vol. 36

No. 5

2007

Figure 15 presents a plot of the relative SHC error ε (reduced to the total absolute error scale) versus differential input signal. This curve was plotted using experimental data obtained at a sampling frequency of

352

GUMENYUK, BOCHAROV |ε|, % 0.8

0.6

0.4

0.2

0 –600

–400

–200

0

200

400 Ud, mV

Fig. 15. A plot of the absolute value of SHC error ε versus differential input signal at a sampling frequency of 20 MHz.

20 MHz for a quasi-constant input signal (with a frequency much smaller than the sampling frequency). In conclusion, the results of computer modeling of the proposed SHC schemes using a “Spectre” stimulator (from a “Cadence Virtuoso” program package) and an 0.18-µm-CMOS component library of the UMC Company, as well as the experimental investigation of SHC prototypes manufactured at the UMC Company plant confirmed the main results obtained in this study. REFERENCES 1. Wilson, W., Massoud, H.Z., Swanson, E.J., et al., Measurement and Modeling of Charge Feedthrough in N-Channel MOS Analog Switches, IEEE J. Solid-State Circuits, 1985, vol. SC-20, no. 6, pp. 1206–1213. 2. Wegmann, G., Vittoz, E., and Rahali, F., Charge Injection in Analog MOS Switches, IEEE J. Solid-State Circuits, 1987, vol. SC-22, no. 6, pp. 1091–1097.

Voltage Shifts in MOSFET’S, IEEE J. Solid-State Circuits, 1994, vol. 29, no. 3, pp. 239–252. 7. Zanchi, A., Tsay, F., and Papantonopoulos, I., Impact of Capacitor Dielectric Relaxation on 14-bit 70-MS/s Pipeline ADC in 3-V BiCMOS, IEEE J. Solid-State Circuits, 2003, vol. 38, no. 12, pp. 2077–2086. 8. Abo, A. and Gray, P., A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, IEEE J. SolidState Circuits, 1999, vol. 34, no. 5, pp. 599–606. 9. Dessouky, M. and Kaiser, A., Very Low-Voltage DigitalAudio Modulator with 88-dB Dynamic Range Using Local Switch Bootstrapping, IEEE J. Solid-State Circuits, 2001, vol. 36, no. 3, pp. 349–355. 10. Gumenyuk, A.S. and Bocharov, Yu.I., Designing Differential CMOS Amplifiers for ADCs, Skhemotekhnika, 2006, no. 12, pp. 2–6. 11. Yang, W., Kelly, D., Mehr, L., et al., A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist Input, IEEE J. Solid-State Circuits, 2001, vol. 36, no. 12, pp. 1931–1936.

3. Chen, M.-J., Gu, Y.-B., Wu, T., et al., Weak Inversion Injection in Analog MOS Switches, IEEE J. Solid-State Circuits, 1995, vol. 30, no. 5, pp. 604–606.

12. Lewis, S., Fetterman, H.S., Gross, G.F., Jr., et al., A 10-b 20-Msample/s Analog-to-Digital Converter, IEEE J. Solid-State Circuits, 1992, vol. 27, no. 3, pp. 351–358.

4. Dai, L. and Harjani, R., CMOS Switched-Op-AmpBased Sample-And-Hold Circuit, IEEE J. Solid-State Circuits, 2000, vol. 35, no. 1, pp. 109–113.

13. Thompson, D. and Wooley, B., A 15-b Pipelined CMOS Floating-Point A/D Converter, IEEE J. Solid-State Circuits, 2001, vol. 36, no. 2, pp. 299–303.

5. Fattaruso, J.W., De Wit, M., Warwar, G., et al., The Effect of Dielectric Relaxation on Charge-Redistribution A/D Converters, IEEE J. Solid-State Circuits, 1990, vol. 25, no. 6, pp. 1550–1561.

14. Li, J. and Moon, U., A 1.8-V 67-mW 10-bit 100 MS/s Pipelined ADC Using Time-Shifted CDS Technique, IEEE J. Solid-State Circuits, 2004, vol. 39, no. 9, pp. 1468–1476.

6. Tewksbury, T., Lee, H., and Miller, G., Characterization, Modeling, and Minimization of Transient Threshold

15. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000, pp. 423–439. RUSSIAN MICROELECTRONICS

Vol. 36

No. 5

2007