Journal of ELECTRONIC MATERIALS, Vol. 37, No. 6, 2008
Regular Issue Paper
DOI: 10.1007/s11664-008-0387-6 2008 TMS
Decapsulation Method for Flip Chips with Ceramics in Microelectronic Packaging T.I. SHIH1,2 and J.G. DUH1,3 1.—Department of Materials Science and Engineering, National Tsing Hua University, Hsin-chu, Taiwan. 2.—United Microelectronics Corporation, Hsin-chu, Taiwan. 3.—e-mail:
[email protected]. edu.tw
The decapsulation of flip chips bonded to ceramic substrates is a challenging task in the packaging industry owing to the vulnerability of the chip surface during the process. In conventional methods, such as manual grinding and polishing, the solder bumps are easily damaged during the removal of underfill, and the thin chip may even be crushed due to mechanical stress. An efficient and reliable decapsulation method consisting of thermal and chemical processes was developed in this study. The surface quality of chips after solder removal is satisfactory for the existing solder rework procedure as well as for die-level failure analysis. The innovative processes included heat-sink and ceramic substrate removal, solder bump separation, and solder residue cleaning from the chip surface. In the last stage, particular temperatures were selected for the removal of eutectic Pb-Sn, high-lead, and lead-free solders considering their respective melting points. Key words: Lead-free, decapsulation method, flip chip, microelectronic packaging, ceramic substrate
INTRODUCTION Flip-chip technology (FCT) provides a great deal of advantages in current microelectronic packaging, such as high pin density, low assembly cost, and high reliability.1–5 To conduct microstructural characterization and failure analysis on current flip chips bonded to ceramic substrates, solder bumps should be completely removed from the chip to expose the area of interest for further examination. However, a die soldered onto the ceramic substrate of a flip-chip package is likely to be damaged during the removal process owing to the heavy etching and abrasion resistance of the ceramic substrate as well as the poor uniformity of the mechanical polishing. The bump-printing process in the assembly house is a critical step for integrated circuit (IC) packaging. Currently, several decapsulation methods have been adopted in the failure analysis laboratory, such as manual chemical methods, auto-decapsulation (autodecap) machines, and laser decapsulation.
(Received March 10, 2006; accepted May 19, 2007; published online February 20, 2008)
The equipment for manual decapsulation includes a hot plate with a temperature controller, fuming nitric acid, a beaker, and a dropper. In most cases, there is die corner damage due to the poor uniformity of manual polishing. Alternatively, an autodecap machine consisting of a chemical etching facility can be used. This method has been extensively used as a routine process for the decapsulation of conventional packages, such as quad flat packages (QFPs), ball grid arrays (BGAs), and chip size packages (CSPs). A recently developed method based on laser decapsulation is presented in Fig. 1. This laser technology allows an operator to remove individual layers of the mold compound all the way through the lead frames to the substrate. The use of laser decapsulation is more convenient than the cut-andpolish method, and also eliminates the need for costly and hazardous chemicals. A work example of mechanical polish decapsulation is shown in Fig. 2. The ceramic substrate was successfully removed from the chip. However, this approach requires lots of human resources and is time consuming. In addition, the poor uniformity of manual polishing increases the risk of die damage. 845
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Fig. 1. Flip-chip packages before and after mold compound removal by a laser decapsulation facility.
human power, the success rate of the manual method is estimated to be as low as 50% for chip separation and as low as 10% for an acceptable surface condition for electrical probing. A number of rework and replacement methods for encapsulated flip-chip bonding have been investigated using available commercial underfill techniques.6–13 Nevertheless, there is still no effective way to decapsulate a flip chip bonded to a ceramic substrate. The purpose of this study was to develop a safe, convenient, and reliable method for decapsulation in the pre-rework of flip-chip packages. The aim was to improve package productivity with a modified thermal treatment. EXPERIMENTAL PROCEDURE
Fig. 2. Example of manual polish decapsulation.
Manual grinding and polishing are generally used in the industry to separate flip chips from substrates. As well as the consumption of time and
The three types of substrates used in this study are listed in Table I. Eutectic and lead-free solders bonded to ceramic substrates and the high-lead solder on organic build-up substrates were employed to investigate the feasibility of the decapsulation process. The chemical composition, physical specification, and application of each solder material are detailed in Table II. A sketch of a flip chip
Table I. Types of Substrates Employed Organic Laminate Max. layer Z0 matching Dielectric constant Dielectric loss angle (10-4) Termination R Coefficient of thermal expansion (CTE) (10-6) Moisture absorption Thermal conductivity YoungÕs moduli Tg
6 Uncontrolled 4.5 (1 MHz) 70 (1 MHz)/130 (1 GHz) N/A 10–16 0.3% 0.24 W/m K 3.0 GPa 180C
Organic Build Up 12 Uncontrolled 3.7 (build up 1 MHz)4.5 (core 1 MHz) 270 (1 MHz)/220 (1 GHz) (build up)70 (1 MHz)/130 (1 GHz) (core) N/A 100 (build up)10-16 (core) 0.3% 0.24 W/m K 2.3 GPa (build up)3.0 GPa (core) 180C
Al2O3 Ceramic 20 Controlled 24 (1 MHz)/31 (2 GHz) 24 (1 MHz)/31 (2 GHz) Built in 7.1 N/A 14 W/m K 310 GPa None
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Table II. The Three Types of Solder Bump Used in the Study Items
Composition
Feature
Application
Eutectic
Sn/Pb = 63/37
1. Tm = 183C 2. Tp = 225C, compatible with surface-mount technology processing
Plastic ball grid array (PBGA)
High lead
Sn/Pb = 3/97, 5/95, 10/90
1. Tm = 310C to 320C 2. Tp = 350C
Must use a ceramic substrate or presoldering eutectic solder on organic substrate when Tp = 225C
Lead free
Major Sn-Ag and Sn-Ag-Cu
1. Tm = 221C (Sn-Ag), Tm = 217C (Sn-Ag-Cu) 2. Tp = 245C to 250C
Environmental protection
Fig. 3. Ceramic flip-chip package with heat sink.
packaged with a ceramic substrate and a heat sink is shown in Fig. 3. It should be noted that there were variations in these structural details for different solder balls and their corresponding applications. The overall procedures developed in this study could be divided into several steps as follows: Step 1: Heat sink removal for ceramic flip-chip packages (if there is no heat sink in the flip-chip package, one goes directly to Step 2). The heat sink could be removed from ceramic flip-chip packages with fuming nitric acid of 75C in 1 min. An alternative method was directly heating the package on a hot plate to 80C and carefully removing the heat sink with handy shovel. Step 2: Ceramic substrate and solder bump separation. After heat sink removal, the solder bump in the package could be separated from the ceramic substrate by heating to 80C on the hot plate after thermal cycle treatment to induce cracks within the solder balls. The surface with the solder removed is shown in Fig. 4. The underfill residual on the chip surface was revealed by optical microscopy (OM) after ceramic substrate removal. Step 3: Underfill removal. For a package with underfill, the underfill could be removed from the chip surface by fuming nitric acid at 75C in 1 min on a hot plate. Another method was directly etching of the package at 80C. A reactive-ion etcher (RIE) was employed in an argon environmental, and the underfill was carefully removed with the N2 gun. Step 4: Solder ball residue clean out from the Al/Cu pad. For the probing technique in failure analysis, the solder residue had to be completely removed from the pad surface by heating above the melting
Fig. 4. Chip surface with solder residue on the pad.
points of the solders used. As shown in Table II, the solder removing temperatures for eutectic, highlead, and lead free solders were controlled in the ranges of 180C to 185C, 315C to 320C, and 215C to 220C, respectively. RESULTS AND DISCUSSION If the package is not properly handled as indicated in step 1, the chip back attached to the heat sink can be damaged, as shown in Fig. 5. In contrast, by appropriate treatment, OM images for flip-chip packages with three types of solder before and after heat-sink removal following the proposed
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Fig. 5. Failure cases of conventional decapsulation: (a) manual decapsulation, (b) manual polish, (c) die delaminated by hot plate, and (d) solder ball removal by oil bath.
treatment described in step 1 are shown in Fig. 6. The chip surface with the underfill successfully removed after step 3 is shown in Fig. 7. However, the case of incomplete underfill removal is represented in Fig. 8, if the sample was not properly treated. For comparison, the clear pad surfaces without any solder residue after step 4 are presented in Fig. 9. Typical failure cases for the mentioned decapsulation methods are shown in Fig. 5. The chip damaged by manual decapsulation due to overetching with fuming nitric acid is shown in Fig. 5a, and 5b shows the die corner damage owing to poor uniformity of manual polishing. The melted solder ball caused by the overheating on hot plate is also shown in Fig. 5c. In addition, the solder residue on the pad surface as seen in Fig. 5d is attributed to insufficient temperature of the oil bath. Although the laser process is accurate and straight for electrical test, the high laser power applied could damage the joint sample and also cause danger for people and environment. This study further provides an approach for decapsulating a package consisting of a heat sink, a plurality of solder bumps, a substrate, underfill, and a plurality of solder balls. The heat sink is placed over the rear surface of the chip, and the solder bumps are placed on its active surface. Since the solder bump is removed by utilizing its own physical properties, the cost for removing the solder bumps is low. To demonstrate the advantage of the decapsulation technique developed in this study fully, a test
specimen, i.e., a flip-chip ball-grid array with leadfree solder balls was trialled. Following the detailed procedures described in steps 1 through 4 in the previous section, complete pads with solder bump were derived. The mechanism behind each technical step for the modified thermal method of decapsulation developed in this study can be described with the aid of Fig. 10, in which Fig. 10a shows a sketch of the ceramic flip-chip package with a heat sink. The heat sink removal from the flip-chip package in Fig. 10b was attributed to the difference in the thermal expansion coefficients between the chip and the heat sink. Material expansion when heated and contraction when cooled down caused the removal of the heat sink from the ceramic package. The separation of the ceramic substrates and solder bumps in Fig. 10c was due to the chemical mechanical polishing effect. The combination of anisotropic dry etching and isotropic wet etching acted to remove the underfill in Fig. 10d. Figure 10e exhibits the solder ball residue cleaning from an Al/Cu pad; the removal of the solder bump resulted from the difference in the melting points of the various materials employed. It should be mentioned that, in addition to the procedures described in the previous section, some modifications in the decapsulation process could be employed to achieve better performance. As an example, in step 3 as well as the mentioned procedure,
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Fig. 6. Micrographs of flip-chip packages before and after heat-sink removal in various solders after step 1: (a, b) eutectic solder with ceramics, (c, d) lead-free solder with ceramic, and (e, f) high-lead solder with organic.
there are other ways to remove the under bump metallization (UBM) and underfill of solder bumps: 1. To etch the package at 80C directly, RIE was employed in an Ar environment, and underfill was carefully removed by using an N2 gun. In fact, the detailed recipe was O2 and Ar with volume flows of 10 sccm and 50 sccm, respectively, as shown in Table III. 2. For packages with underfill, the underfill could be removed from the chip surface by fuming nitric acid at 75C for 1 min on the hot plate. In comparison with conventional decapsulation methods, this newly developed approach is fast. The chemical composition, physical specification, and application of each solder material are listed in Table II. Based on the melting temperature, specific
solder removal temperature ranges could be determined for various types of solder residue after bump separation from the substrate. The chip removal and solder ball clean-up processes could be accomplished within 10 min. Moreover, it shows fast curability. The new process exhibited an almost 100% success rate. In contrast, the success rate of the manual method can be as low as 50% for chip separation. For further applications, it is demonstrated that this decapsulation method can be applied to the industryÕs existing solder rework procedures. The rework is achieved by thermal cycle treatment for the removal of the silicon die followed by solvent cleaning (or use of the RIE machine) of the underfill residue and then heating to the melting point of solders to remove the solder ball from the die for Pb-Sn eutectic, high-lead, and lead-free solders.
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Fig. 7. Chip surface without underfill residue.
CONCLUSIONS A novel and fast flow decapsulation method for microelectronic packaged devices (flip chips with ceramic substrates) is proposed. The solder ball can be completely removed from the pad surface by heating above the melting points of the respective solders. Inspection accuracy in the failure analysis is thus successfully achieved. During laboratory testing, this newly developed process exhibits a nearly 100% success rate. It is also cost effective and has a fast throughput. Laboratory practice demonstrates that the chip removal and solder ball clean-up processes can be accomplished within 10 min. Particular temperature levels of fuming
Fig. 9. OM images showing (a) Pb-Sn eutectic, (b) lead-free, and (c) high-lead solders clearly removed.
Fig. 8. Two failure cases of underfill removal: (a) with underfill residue on the chip by reactive-ion etching (RIE): (b) with underfill residue on the chip due to solder ball damage by fuming nitric acid on the hot plate.
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Table III. The Detailed Operating Conditions of the Reactive-Ion Etcher (RIE) Used in This Study. Recipes: Smart 1 Indictively coupled plasma (ICP) RIE Press Power Power Time Pressure 50 mTorr
8000 W
under Contract acknowledged.
100 W
80 s
O2
Ar
10 sccm 50 sccm
NSC-94-2216-E-007-016
are
REFERENCES
Fig. 10. Mechanism for each technical steps for ceramic substrate with heat sink: (a) a sketch of a ceramic flip-chip package with a heat sink, (b) heat-sink removal for ceramic flip-chip packages, (c) ceramic substrate and solder bump separation, (d) underfill removal, and (e) solder ball residue cleaning from an Al/Cu pad.
nitric acid used in this new decapsulation process were also successfully evaluated for various solders, including eutectic Pb-Sn, high-lead, and lead-free materials. ACKNOWLEDGEMENTS The joint assembly preparation from United Microelectronics Corporation (UMC) and financial support from National Science Council, Taiwan
1. M. McCormack, S. Jin, G.W. Kammlott, and H.S. Chen, Appl. Phys. Lett. 63, 15 (1993). 2. L.F. Miller, IBM J. Res. Develop. 13, 239 (1969). 3. J.H.L. Pang, T.H. Low, B.S. Xiong, L.H. Xu, and C.C. Neo, Thin Solid Films 462–463, 370 (2004). 4. J.H.L. Pang, T.H. Low, B.S. Xiong, and F.X. Che, Proceedings of IEEE, 2003 Electronics Packaging Technology Conference (Singapore, 2003), pp. 470–478. 5. F.A. Stam and E. Davitt, Microelectron. Reliab. 41, 1815 (2001). 6. B. Ma, Q.K. Tong, and A. Savoca, Electronic Components and Technology Conference, Proceedings. 50th. P252-5 (1998). 7. D. Suryanarayana, J.A. Varcoe, and J.V. Ellerson, Proceedings of 45th Electronic Components & Technology Conference (Las Vegas, NA, 1995), pp. 524–528. 8. K.R. Grebe, J.M. McCeary, D. Suryanarayana, and H.M. Tong, U.S. patent 52,74913 (January 1994). 9. T. Gregorich, H. Hoang and S. Mok, First Symposium on Flip Chip Technology (San Jose, CA, Febuary 1994). 10. S.V. Vasan, P.T. Truong, and G. Gody, Circuit World 21, 16 (1995). 11. Y. Tsukada, S. Tsuchida, and Y. Mashimoto, Proceedings of 43rd Electronic Components & Technology Conference (Orlando, FL, 1993), pp. 199–204. 12. F.L. Pompeo, A.J. Call, J.T. Coffin, and S. Buchwalter, Interpak 95 (Hawaii, 1995). 13. B.L. Gutierrez and C.Y. Yu, U.S. patent 5371328 (6 December 1994).