J Comput Electron DOI 10.1007/s10825-015-0776-z

Dual-channel trench LDMOS on SOI for RF power amplifier applications Mayank Punetha1 · Yashvir Singh1

© Springer Science+Business Media New York 2015

Abstract An integrable RF dual-channel trench LDMOS (DCT-LDMOS) structure is proposed on SOI by incorporating trenches in the drift region. The gate electrode of DCT-LDMOS is placed vertically in a trench at the centre of structure thus forming two channels in p-base region which carry drain current in parallel. Other two identical trenches filled with oxide are symmetrically located on both sides of p-base to enhance reduced-surface-field effect in the device. The electric field modulation by the trenches together with dual-channel leads to significant improvement in DC and RF performance of the proposed device. The performance of DCT-LDMOS is evaluated and compared with that of the conventional LDMOS using 2-D simulations. The proposed structure exhibits 1.47 times increase in breakdown voltage, 25 % reduction in on-resistance, 2.4 times higher output current, and 2 times improvement in peak transconductance when compared to the conventional device for identical device area. Furthermore, the DCT-LDMOS achieves 45 % higher cut-off frequency and 14 % improvement in maximum oscillation frequency over the conventional counterpart. Keywords RF LDMOS · Dual-channel · Trench-gate · Breakdown voltage · Cut-off frequency

1 Introduction Silicon-on-insulator (SOI) technology is preferred over the bulk substrates for fabrication of power integrated circuits

B 1

Yashvir Singh [email protected] Department of Electronics & Communication Engineering, G. B. Pant Engineering College, Pauri Garhwal, Uttarakhand 246 194, India

(PICs) due to excellent isolation and ease of integration of different devices on a single chip to get advantages of improved reliability, lower power consumption and reduction in volume, weight and cost. Among various power semiconductor devices, laterally double-diffused metal-oxidesemiconductor field effect transistors (LDMOS) are key components used in PICs as RF power amplifiers for wireless applications [1–4]. For these circuits, the desirable performance parameters of an RF LDMOS are high drive current (ID ), low threshold voltage (Vth ), low on-resistance (Ron ), high transconductance (gm ), high breakdown voltage (Vbr ) at a specified cut-off frequency (fT ) and maximum oscillation frequency (fmax ). In a conventional LDMOS design, it is not possible to satisfy all these conditions simultaneously because these parameters are interlinked with each other and any attempt to improve one may degrade the others. Therefore, one has to make a trade-off among these parameters in a conventional LDMOS. For improving trade-off, several modifications in conventional RF LDMOS have been reported in literature [5–9]. A reduced-surface-field (RESURF) dielectric-regioninserted (REDI) LDMOS was proposed by Han Xiao et al. [6] in which an oxide layer and highly doped p+ region were inserted in the drift layer. This technique was used to reduce the drain capacitance and electric field near the drain region for improving RF characteristics and Vbr of the device. The REDI-LDMOS was demonstrated to achieve fT of 18 GHz and high ID (0.4 mA/µm at VGS = 2 V) with Vbr of 15 V. Another RF LDMOS structure called Isolated-LDMOS was reported [7] to improve the fT and fmax up to 30 and 53 GHz, respectively. However, no significant improvement in Vbr was noticed. For higher Vbr , the RF LDMOS structures utilising the effect of mechanical stress were proposed [8]. Although, these devices exhibit a Vbr of 45 V and gm of 70 µS/µm at the cost of reduction in ID (0.12 mA/µm at

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VGS = 3V) and fT (5.3 GHz). The Vbr of these structures was further improved to 55 V with a modified RF LDMOS layout using drain contact wider than channel region [9]. From these studies, it is clear that improvement in Vbr leads to degradation in fT and ID . Therefore, new design concepts are needed to get a well-balanced compromise among all performance parameters of an LDMOS. Although, incorporating trenches in the LDMOS design has been successfully demonstrated to enhance the static and switching performance [10–16] but proper attention has not been given to evaluate the RF characteristics of a trench-LDMOS structure. Therefore, in order to improve both DC and RF characteristics, we propose a dual-channel trench LDMOS (DCTLDMOS) structure on SOI. The proposed device has a trench at the centre in which gate is placed to create two channels in the p-base region while other two trenches filled with oxide are symmetrically located on both sides of p-base. The proposed structure provides significant improvements in ID , Vbr , gm , fT , and fmax as compared to the conventional and other reported structures in literature.

(a)

2 Device structure and operation

(b) The schematic cross-sectional view of the conventional and the proposed DCT-LDMOS structures are shown in Fig. 1. In both the devices, n+ -polysilicon is used as gate material with identical gate length of 0.5 µm and a total device length of 5 µm. As illustrated in Fig. 1a, the conventional LDMOS is a planar structure with gate, source and drain electrodes placed on the top and gate-polysilicon is extended over the drift region to act as horizontal field-plate [17]. The positive gate bias creates a single channel in the p-base and current flows from drain to source for positive drain voltages. Under off-state, the gate and source are grounded and increasing drain bias causes spreading of depletion region in the n-drift layer towards drain. The peak electric field responsible for breakdown occurs on the silicon surface at the end of fieldplate. Although, for a given drift region length and doping concentration, the field-plate length is optimized to obtain maximum Vbr but the electric field still peaks on the surface which restricts further improvement in Vbr . This limits the trade-off between Vbr and Ron . It may be noted that the fieldplate length also affects the gate-to-drain capacitance (Cgd ) and hence high frequency response of the device. Moreover, the flow of drain current near the surface through single channel provides low ID and gm of the conventional LDMOS. In order to improve performance parameters, the DCT-LDMOS as shown in Fig. 1b is proposed by incorporating trenches in the drift region. The gate electrode is placed in a trench at the centre of structure and gate polysilicon is extended downward in the drift region to act as vertical field-plate. The other two identical trenches filled with oxide are located symmetrically

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Fig. 1 Schematic cross-sectional view of the conventional LDMOS and the proposed DCT-LDMOS structures

on sides of p-base between source and drain. A positive gate bias creates two vertical channels in p-base along the sidewalls of the gate-trench resulting in parallel flow of drain current through both the channels. The parallel conduction of dual-channels not only enhances the ID but also improves the gm due to better control of gate over ID . The trenches of DCT-LDMOS fold the drift region in vertical and horizontal directions which increases effective drift region length and reduces electric field due to enhanced RESURF effect [1] leading to higher Vbr . Moreover, the improvement in gm together with reduction in total capacitance of the proposed device results in better fT and fmax . The optimized structural parameters used in simulation for both the structures are listed in Table 1. For 2-D simulations, the width of both the devices is kept 1 µm as default in the device simulator and the simulated quantities are thus obtained per unit width of both the devices. Therefore, the advantages of proposed DCT-LDMOS over conventional LDMOS are achieved at identical device length (5 µm), device width (1 µm) and drift region doping (2 × 1016 cm−3 ). It may be noted that the full-cell pitch of the DCT-LDMOS is 50 % as compared to the

J Comput Electron Table 1 Optimized structural parameters used in study Symbol

Units

Conv. LDMOS

DCT-LDMOS

L

µm

5.0

5.0

LG

µm

0.5

0.5

tox

nm

30

30

tBOX

µm

0.5

0.5

tSi

µm

0.75

2.20

t1

µm

–

1.50

LD

µm

3.3

–

LFP

µm

1.8

–

L1

µm

–

1.0

L2

µm

–

0.6

tox1

nm

150

150

Nd

cm−3

2 × 1016

2 × 1016

p-base

cm−3

8 × 1016

8 × 1016

full-cell pitch of conventional LDMOS. The DCT-LDMOS having stepped-gate structure with unequal tox and tox1 can be fabricated using a procedure as reported in [18].

3 Results and discussion The conventional LDMOS and the proposed DCT-LDMOS structures were implemented in the device simulator (ATLAS) [19] and 2-D simulations were carried out for both the devices. In these simulations, Shockley–Read–Hall (SRH), concentration-dependent mobility (CONMOB), fielddependent mobility (FLDMOB), Fermi-Dirac carrier statistics (FERMIDIRAC) and Selberherr’s (IMPACT SELB) models were used. The DC and RF characteristics of both the structures are evaluated and compared with each other. Figure 2 compares the off-state breakdown characteristics of the DCT-LDMOS with that of the conventional device. The Vbr is extracted at an ID of 1 × 10−12 A/µm. At drift-region doping of 2 × 1016 cm−3 , the conventional LDMOS shows a lower breakdown voltage of 64 V whereas the proposed DCTLDMOS provides higher breakdown voltage of 94 V. In other words, the breakdown voltage of the proposed device is 1.47 times that of the conventional LDMOS. This large improvement in Vbr can be explained by analysing the electric field distribution inside the drift region of each device. Figure 3 shows 2-D electric field contours in the drift region of both the structures at drain-source voltage (VDS ) of 30 V. As seen, in case of the conventional LDMOS, the electric field peaks on the silicon surface below the end of field-plate (marked point ‘A’ in Fig. 3a). Although the length of field-plate is optimised to reduce the electric field in the drift region but the peak of electric field still occurs on the surface. On the other hand, in case of the proposed structure, the peak electric field

Fig. 2 Breakdown characteristic of the DCT-LDMOS and the conventional LDMOS

shifts into bulk of silicon near the bottom edge of gate-trench (marked point ‘B’ in Fig. 3b). This is because the presence of trenches in drift region causes faster spreading of depletion region due to enhanced reduced-surface-field (RESURF) effect leading to reduction in peak electric field [1]. Figure 4 gives the electric field variation along the cut-lines 1–2 and 3–4 (as shown in Fig. 3) in the conventional LDMOS and the DCT-LDMOS structures, respectively. As evident from this figure, the peak electric field is 0.33 MV/cm in the DCT-LDMOS as compared to 0.35 MV/cm in the conventional LDMOS. A reduction in peak electric field in the drift region leads to higher breakdown voltage which is true for a fixed drift region length. The trenches of DCT-LDMOS fold the drift region in vertical and horizontal directions resulting effective drift region length of 3.3 µm (between n+ -drain region and p-base) which is equal to that of the conventional LDMOS (LD = 3.3 µm). For an LDMOS, the on-resistance (Ron ) is calculated as the ratio of drain voltage to drain current when device operates in linear region. The Ron is multiplied by the device length to get specific on-resistance (Ron,sp ). Figure 5 shows the variation of Ron,sp with gate bias (VGS ) for both the devices. As seen, the proposed structure exhibits lower Ron,sp as compared to the conventional device due to parallel conduction of two channels. At VGS = 10 V, the Ron,sp of proposed and conventional devices is found to be 0.46 and 0.61m.cm2 , respectively leading to 25 % reduction in Ron,sp . Figure 6 gives the plot of output characteristics of both the structures at different VGS . As evident from these characteristics, the proposed device exhibits higher ID and larger safe operating area as compare to the conventional LDMOS. At VGS = 3 V, the planar LDMOS gives an ID of 0.10 mA/µm while it increases to 0.24 mA/µm in case of the DCT-LDMOS i.e. the ID of proposed device is 2.4

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J Comput Electron Fig. 3 2D electric field contours at VDS = 30 V in a conventional LDMOS b DCT-LDMOS

(a)

(b)

Fig. 4 Electric field distribution on surface for conventional LDMOS and in the Si around the gate trench for DCT-LDMOS at VDS = 30 V

Fig. 5 ON-resistance variation of the DCT-LDMOS and the conventional LDMOS

times higher than that of the conventional counterpart. In other words, ID for the DCT-LDMOS is significantly higher despite its higher Vbr . The reason for higher ID of the proposed structure is parallel conduction of two channels formed along the side walls of gate-trench. The transfer characteristics of both the devices operating in saturation are shown in Fig. 7. The threshold voltage (Vth ) is extracted in saturation region by the linear extrapolation √ method using ID versus VGS curve. The value of Vth for DCT-LDMOS is found to be 0.89 and 0.91 V for conven-

tional LDMOS in saturation region. There is no significant difference in Vth of two devices because their doping concentration is same as given in Table 1. For integrated RF power amplifiers, the gm of an LDMOS should be as high as possible. In comparison to conventional device, the proposed structure gives a better control of gate over the ID and hence provides higher gm because the current of two channels is simultaneously affected by the same gate electrode. As seen from Fig. 7, the peak gm of DCT-LDMOS is 148 µS/µm as compared to 73 µS/µm of the conventional LDMOS lead-

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Fig. 6 Output characteristics of the DCT-LDMOS and the conventional LDMOS

Fig. 8 Short-circuit current gain and unilateral power gain of the DCTLDMOS and the conventional LDMOS

Fig. 7 Transfer and transconductance characteristics of the DCTLDMOS and the conventional LDMOS at VDS = 15 V

Fig. 9 Cgd and Cgs of the DCT-LDMOS and the conventional LDMOS

ing to 2 times improvement. Figure 8 shows the variation of short circuit current gain and unilateral power gain with operating frequency for the conventional LDMOS and half-cell of DCT-LDMOS. These characteristics are obtained from ac simulations performed in the device simulator at bias conditions corresponding to peak gm in both the devices i.e. VGS = 3 V and VDS = 15 V. The fT is extracted as the point on frequency axis at which the short circuit current gain of the device becomes unity while fmax is extracted as the point where unilateral power gain is unity. The fT of planar LDMOS and DCT-LDMOS is found to be 5.8 and 8.4 GHz, respectively i.e. the proposed structure exhibits nearly 45 % higher fT . On the other hand, the fmax of proposed device is 25 GHz as compared to 21.8 GHz of the conventional device providing 14 % improvement in fmax . Figure 9 shows the variation of gate-drain capacitance (Cgd ) and the

gate-source capacitance (Cgs ) for the conventional LDMOS and half-cell of the DCT-LDMOS at same bias conditions as that for frequency extraction. The Cgd of conventional and DCT-LDMOS is found to be 0.06 and 0.09 fF/µm, respectively. The proposed structure has a higher Cgd due to presence of the oxide-trench in the drift region which gives an additional capacitance between gate and drain contacts. Whereas, the Cgs of the conventional LDMOS is observed to be 1.91 f F/µm as compared to 1.33 f F/µm of the DCTLDMOS. The proposed device exhibits a lower Cgs due to reduced interaction between the source metal and the polysilicon gate with respect to the conventional LDMOS [20]. Since the total capacitance (Cgd + Cgs ) of the DCT-LDMOS is smaller than that of the conventional LDMOS, therefore, the improvement in fT of DCT-LDMOS is due to reduction in total capacitance of the structure.

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Fig. 10 Drain current and transconductance as a function of drift region doping for the DCT-LDMOS

The performance of proposed structure depends upon various device parameters such as drift region doping (Nd ) and trench depth (t1 ). For a full device length of 5 µm, the variation in performance parameters is obtained using 2D simulations. Figure 10 gives the variation of ID and gm with Nd of the DCT-LDMOS. An increase in Nd reduces the drift region resistance which improves both ID and gm . The effect of Nd on Vbr and fT of proposed structure is shown in Fig. 11. The Vbr of DCT-LDMOS improves slowly with increase in Nd up to 2 × 1016 cm−3 and decreases rapidly thereafter. This is because for Nd = 2 × 1016 cm−3 , maximum RESURF effect is observed in the drift layer which minimizes the electric field leading to maximum Vbr . For further increase in Nd , the drift region is not fully depleted on drain side which increases the electric field and hence reduces the Vbr . As depicted from Fig. 11, initially, the fT improves with increasing Nd due to increase in gm . While at higher Nd , the fT saturates due to slow saturation in gm as well as increase in Cgd . The Cgd includes gate/drift overlap capacitance and gate/drift junction capacitance [20]. At higher Nd , the gate/drift junction capacitance increases due to increase in space charge in the depletion region. At optimum Nd of 2 × 1016 cm−3 , the effect of t1 on Vbr and fT is plotted in Fig. 12. For smaller value of t1 , the drift region is not fully depleted which increases electric field and device shows lower Vbr . At t1 = 1.5µm, entire drift region is depleted which provides more uniform field distribution and the device achieves maximum Vbr of 94 V. Further increase in t1 leads to increase in electric field near drain contact resulting decrease in Vbr . On the other hand, the fT of DCT-LDMOS degrades with increasing t1 due to increase in drift region resistance which lowers gm of the device. A summary of performance of proposed device compared with other reported LDMOS structures for half-cell is given in Table 2. The trade-off between Vbr and fT is measured

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Fig. 11 Breakdown voltage and cut-off frequency as a function of drift region doping for the DCT-LDMOS

Fig. 12 Breakdown voltage and cut-off frequency as a function of trench depth (t1 ) for the DCT-LDMOS

as the product of Vbr and fT . As seen, the DCT-LDMOS provides higher Vbr × fT over the other LDMOS devices. Moreover, the half-cell pitch of DCT-LDMOS is 2.5 µm in comparison to 7.5 µm of TGLDMOS which provides 3 times reduction in cell pitch. Therefore, the proposed device is a superior LDMOS for integrated RF power amplifier applications.

4 Conclusion An RF DCT-LDMOS structure on SOI is obtained by incorporating trenches in the drift region of planar technology. The gate electrode of DCT-LDMOS is placed in a trench to create two channels in the p-base which enhances the current drivability and transconductance of the device. The

J Comput Electron Table 2 Performance comparison of the RF LDMOS structures for half-cell pitch Structures

Cell pitch (µm)

I D (mA/µm)@ VGS = 3V

Vbr (V)

fT (GHz)

fmax (GHz)

Vbr × fT (V Ghz)

Conventional LDMOS

5.0

0.10

64

5.8

21.8

371.2

Multi-finger LDMOS [8]

–

0.12

45

5.0

16.2

225.0

Annular LDMOS [8]

–

0.12

41

5.3

16.5

217.3

WD-LDMOS [9]

–

0.15

55

5.3

18.0

291.5 530.1

LDMOS with SFP [20]

9.0

–

93

5.7

17.1

TGLDMOS [20]

7.5

–

81

6.7

16.8

542.7

Proposed DCT-LDMOS

2.5

0.12

94

8.4

25.0

789.6

trench structure increases the RESURF effect to suppress the peak electric field in the drift region leading to higher breakdown voltage. Moreover, the DCT-LDMOS exhibits significant improvement in cut-off frequency and maximum oscillation frequency due to increased transconductance and reduced capacitance as compared to conventional LDMOS for identical device length. Moreover, the proposed structure provides higher Vbr × fT product with reduced cell-pitch in comparison with earlier reported TGLDMOS structure in literature. This work demonstrates the suitability of DCTLDMOS structure for integrated RF power amplifiers.

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