Analog Integrated Circuits and Signal Processing, 14, 223–233 (1997)

c 1997 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands. °

Low-Cost CMOS Interface for Capacitive Sensors and Its Application in a Capacitive Angular Encoder XIUJUN LI, GERBEN W. DE JONG, GERARD C. M. MEIJER, FERRY N. TOTH AND FRANK M. L. VAN DER GOES Faculty of Electrical Engineering, Delft University of Technology Mekelweg 4, 2628 CD Delft, The Netherlands [email protected]

Received March 20, 1996; Accepted December 20, 1996

Abstract. A low-cost CMOS integrated interface for capacitive sensors is presented. The interface is composed of two separate chips: a capacitance-controlled oscillator and a selector, which result in a structure that is able to measure several capacitances accurately and has a microcontroller-compatible output. In this interface, even large parasitic capacitances of up to 3 nF between the terminals of the capacitor to be measured and ground are allowed. Prototypes of the interface chips have been fabricated in a 0.7-µm CMOS process. The frequency of the oscillator amounts to 90 kHz. For the capacitance measurement, the interface has a resolution of 11.3 ppm and a nonlinearity of 300 ppm over a measurement range of 2 pF. In this paper, also the application of the interface in an accurate capacitive angular encoder is discussed. Key Words: sensor interface, capacitance measurement, capacitive sensor 1.

Introduction

Capacitive sensors are used in a wide variety of measurement and control systems, such as liquid-level gauges, pressure meters, accelerometers and precision positioners. In these applications, the capacitances to be measured are often in the range of 0.1–10 pF, and usually a high resolution is required [1–4]. Special care has to be taken in processing the small capacitances of capacitive sensors. The use of very high frequencies would increase the values of the signals, but this has the disadvantage that the limited bandwidths of amplifiers and comparators would impose a limitation on the accuracy of the processing. However, large bandwidths usually require large current consumption. For these reasons, often high-performance capacitive elements appear with frequencies below 100 kHz. To handle the small sensor signals in an accurate way, a number of precautions have to be taken into account. Amongst these precautions are shielding to reduce the effect of EMI and guarding to limit the effect of the electric-field bending. However, these techniques introduce rather large parasitic capacitances between the two terminals of the capacitor and ground (see Figure 1). The values of the two parasitic capacitors C p1

and C p2 are application dependent and not very stable. For instance, due to movement of the connecting wires, the two parasitic capacitances can easily change. Fortunately, as has been shown in previous papers [1, 3], the effects of these parasitic capacitances can be eliminated by applying the two-port measurement method. In this method, the effect of the parasitic capacitances C p1 and C p2 is reduced by applying a low impedance voltage source and a low impedance current detector, respectively. Synchronous detection can be used to limit the effect of both noise and EMI. For a user, the signal processing can be simplified by using a special transducer interface for capacitive sensors. Recently, a novel capacitive-sensor interface based on a first-order relaxation oscillator has been presented [5]. This interface can offer an accurate interface for the capacitive sensors, with a resolution of 50 aF in a measurement time of 100 ms. In this paper, an alternative design of such an interface based on a modified Martin oscillator is presented [6]. The interface, which has multiple inputs for the capacitive sensor and a microcontroller-compatible output, is realized in a 0.7-µm CMOS process. The input stage has been optimized so that relatively large parasitic capacitances are allowable.

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Fig. 1. The two-port capacitance-measuring circuit.

2. 2.1.

Measurement System for Multiple Capacitance Two-Port Measurement

Generally, the terminals of a capacitive sensing element Cs are connected by parasitic capacitances C p1 and C p2 (see Figure 1) to ground. For a major part, the existence of these parasitics is a consequence of measures taken to improve the accuracy. In most applications, these parasitic capacitances are much larger than the capacitances to be measured, and their values may not be constant. The influences of these two parasitic capacitances can be eliminated by applying the two-port measurement. Figure 1 shows a typical configuration of this kind of circuit in which one of the sensor electrodes is connected to a voltage source and the other to the input of a current detector, which has a very low input impedance to ground. The parasitic capacitances C p1 and C p2 are in parallel with the voltage source and the low input impedance of the current detector, respectively, and thus do not affect the detected current I .

2.2.

The Complete Measurement System

Figure 2(a) shows a diagram of the complete capacitive sensor system, which is mainly composed of three parts, the capacitive sensing element, an interface and a microcontroller [4]. The capacitive sensing element is a multielectrode structure of which the capacitor values are sensitive to the physical quantities, such as position, speed, force and humidity. The interface has a multicapacitance input and a single period-modulated output, and it includes a nearly linear capacitance-controlled oscillator, a selector and a frequency divider. In our realization, the capacitance-controlled oscillator and the frequency divider are integrated in a single chip, the selector is integrated in another single chip. The capacitance-

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(a)

(b) Fig. 2. (a) A diagram of the capacitive sensor system. (b) The waveform at the output of the interface.

controlled oscillator linearly converts the capacitor values of the sensing element to the period-modulated signals. The selector, which is controlled by a microcontroller, selects the capacitance to be measured. A frequency divider decreases the frequency of the output signal of the interface to obtain a lower interrupt rate of the microcontroller. This increases the throughput and thus the efficiency of the microcontroller. Figure 2(b) shows the waveform at the output of the interface, where the periods Ts1 . . . Tsn correspond to the measured capacitances Cs1 . . . Csn , respectively. Their relationship is:

Tsi = K Csi + Toff

(i = 1, 2, . . . , n), (1)

where K and Toff are the transfer coefficient and the offset of the interface, respectively. The microcontroller performs the measurement and the data processing. It also enables the communication with the outside digital world. In order to eliminate or reduce the effect of parasitic capacitances between the two terminals of capacitor and ground, according to the two-port measurement technique, the input terminal of the capacitance-controlled oscillator should have a very low input impedance to ground (current detector), and the output terminal of the selector should have a very low output impedance to ground (voltage source).

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Fig. 3. A capacitance-controlled oscillator.

3. 3.1.

The Capacitance-Controlled Oscillator and Its Nonidealities Capacitance-Controlled Oscillator

In view of its simplicity and the linearity of the capacitor value-to-period transfer, a relaxation oscillator has been used for the capacitance-controlled oscillator. Figure 3 shows the circuit diagram of this capacitancecontrolled oscillator, which is based on the modified Martin oscillator. It is mainly composed of five parts: an OTA-C integrator, a comparator, a switched current source, a switch-control logic block and a Schmitt trigger buffer. The capacitances Cs1 . . . Csn are to be measured. C p2 and C p3 are parasitic capacitances. The resistors Rdiv1 and Rdiv2 , and the operational amplifier (OA) supply a voltage bias level of VCC /2. The operational transconductance amplifier (OTA) and the capacitor Cint form an OTA-C integrator with a low input impedance for the switched current Ich . The output state of the comparator changes as soon as the output voltage of the integrator crosses the value of the voltage bias (VCC /2). The charge on the capacitors Coff and 6Csi (i = 1 . . . n) is periodically dumped into and undumped from Cint . The charge/discharge states of the switched current source are controlled by the switch-control logic which is synchronized with the output signal of the oscillator. For the ideal situation, the relationship between the period of the square-wave signal at the output of the oscillator and the capacitance Csi to be measured, can be described by: Tp = 2

(6Csi + Coff )VCC + 4td , Ich

(2)

where VCC is the power supply voltage, Ich is the amplitude of the charge/discharge current, td is the delay time in the oscillator loop, which is mainly determined by the delay time of the comparator.

3.2.

Nonlinearity

By using the three-signal approach in the measurement of the capacitances, the effect of the nonidealities in the oscillator, which cause additive or multiplicative errors, are eliminated [7]. However, the influence of measurement errors that cause nonlinearity in the capacitancecontrolled oscillator will not be eliminated. Some of the oscillator’s main nonlinearity sources are discussed in the following.

A. The Parasitic Capacitance C p2 and Limited OTA Transconductance One of the main aims of the present design is to allow a large parasitic capacitance at the input terminal. However, due to the nonzero impedance at the input of the integrator, the effect of the parasitic capacitance C p2 cannot be eliminated completely. This will cause a relative nonlinearity ε N L with a value of: ¶ 0 0 Ich C p2 Cint + C p2 C p3 + C p3 Cint 1 + 2 VCC Coff Cint gm0 ! Ã Tp Cint gm0 , (3) × exp − 0 0 2 C p2 Cint +C p2 C p3 +C p3 Cint

εN L ∼ =

µ

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Fig. 4. The effect of the parasitic capacitance C p2 on the nonlinearity according to equation (3).

where Tp is the oscillator period and 0 C p2 = C p2 + Coff + 6Csi .

(4)

A large transconductance of the OTA will decrease the effect of the parasitic capacitance on the nonlinearity, which is in agreement with general feedback theory. To illustrate the effects of the various parameters in equation (3) on the nonlinearity, Figure 4 depicts, as an example, the ε N L for Cint = 60 pF, C p3 = 40 pF and Tp = 10 µs, versus the value of the parasitic capacitance C p2 for three conditions of the remaining parameter gm0 . The parasitic capacitance C p2 also results in an additive term on the period of the oscillator. It is: Tadd =

0 2(Cint + C p2 )C p3

gm0 Cint

.

(5)

For constant parasitic capacitance, this additive term will be eliminated by using the three-signal method in the capacitance measurement. B. Output Impedance of Switched Current Source The output impedance Rso of the switched current source results, in combination with the input impedance of the integrator, in an LF pole. This pole, with a time constant τ L F = gm0 Roo Rso Cint results in a relative nonlinearity [8]: εN L =

Tp , 2gm0 Roo Rso Cint

(6)

where Roo is the output resistance of the OTA. For instance, when substituting some values gm0 = 0.01 A/V, Cint = 60 pF, Tp = 10 µs, Roo = 100 MÄ and Rso = 100 MÄ, we find that the nonlinearity amounts

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C. Frequency-Variable Delay Time of Comparator The frequency-variable delay time td (= td0 + aT + bT 2 + cT 3 + · · ·) of the comparator will cause nonlinearity in the transfer from the capacitance to the period. A constant and linear-variable delay time of the comparator with the period will not cause nonlinearity. However, the second- and higher-order terms of the delay time of the comparator will cause a relative nonlinearity ε N L , εN L ∼ = 4Tp (b + · · · + cTp + · · ·),

(7)

where b and c are the second- and third-order term coefficients of the delay time of the comparator, respectively. From the above discussion, it can be concluded that a small nonlinearity requires large values for transconductance gm0 and the integrator capacitance Cint . However, a large value of the integrator capacitance Cint will decrease the value of the output signal of the integrator, which negatively affects the SNR and thus the resolution for a certain measurement time. Meanwhile, formula (3) shows that the value of the parasitic capacitance C p3 should be as small as possible when a large parasitic capacitance C p2 is allowed and a small nonlinearity is required.

4.

4.1.

Design of the Capacitance-Controlled Oscillator OTA-C Integrator

Figure 5 shows the circuit diagram of the OTA-C integrator which is comprised of an operational transconductance amplifier (OTA) and the capacitor Cint . The OTA is a simple differential operational transconductance amplifier with two input MOS transistors, M11 and M13 , and some current mirrors. The current mirrors at the output stage are cascaded to obtain a large output impedance.

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Fig. 5. A circuit diagram of the OTA-C integrator.

For the OTA with a single pole with a time constant τ p , the transfer function of the integrator is: gm0 − sCint (1 + sτ p ) Vout ³ ´, =− 1+s(C p2 C p3 +C p2 Cint +Cint C p3 )(1+sτ p ) Ich sgm0 Cint (gm0 Cint ) (8) where the capacitances C p2 and C p3 are the parasitic capacitances at the input and output of the integrator, respectively. If the transconductance and the bandwidth of the OTA are large enough, formula (8) can be simplified to: 1 Vout ∼ . =− Ich sCint

(9)

The large transconductance and the limited bandwidth of the OTA will cause instability of the integrator. The phase margin ϕm is µr ¶ τ p gm0 ◦ −1 ∼ . ϕm = 90 − tan C p2 + C p3 + C p2 C p3 /Cint (10) Formula (10) shows that to ensure a minimum phase margin of, for instance, 60◦ , the values of C p2 or C p3 should exceed a certain minimum value. However, a large value of C p3 would seriously affects the nonlinearity of the oscillator as shown by formula (3). Therefore, it is preferable to ensure that C p2 is not too 00 small. This is realized by connecting a capacitor C p2 to the input terminal of the oscillator. For instance, consider a phase margin of 60◦ . When gmo = 0.01

A/V, f p = 1/(2π τ p ) = 40 MHz, C p3 = 40 pF and Cint = 40 pF, the value of the capacitance C p2 should be larger than 40 pF. It has been shown that an OTA with large values of the transconductance gm0 is required to enable a large parasitic capacitance at the input of the oscillator. A straightforward way to obtain an OTA with a large transconductance value is to increase the width/length ratio W/L of the input transistors M11 and M13 , or the tail current Itail of these transistors. In our design with W/L = 4000/1.2 and Itail = 500 µA, we obtain gm0 ∼ = 0.01 A/V.

4.2.

Switched Current Source

Figure 6 shows a switched current source which supplies the charge/discharge current Ich for the OTA-C integrator. Simple current mirrors with source resistors are employed to obtain the current source with a sufficiently high output impedance. The required amplitude of the charge/discharge current Ich can be determined from the formula (2). It is: Ich =

2Coff Vcc , Toff − 4td

(11)

where Toff is the period of the oscillator when no measurand (capacitor to be measured) is connected. For instance, when Toff = 10 µs, Coff = 1.3 pF, VCC = 5 V and td = 0.5 µs, then a current Ich of 1.6 µA is required. The sizes of the transistors M2 and M9 , which

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Table 1. Some parameters and simulated results for the OTA and switched current source.

Quantities

Symbol

Value

Transconductance Tail current Output resistance of OTA Bandwidth (−3dB) Charge/discharge current Output resistance

gm0 Itail Roo fp Ich Rso

12.4 mA/V 500 µA 280 MÄ 44 MHz 1.6 µA 1.2 GÄ

Fig. 6. Switched current source.

supply the charge/discharge current, are chosen according to the following formula: (

W M2 L M2

=

L M2 =

K pn K pp λ0 p λ0n

·

W M9 L M9

L M9

(12)

where K pn , K pp , λ0n and λ0 p are the process parameters. The first formula ensures that the Vgs -to-IDS transfers of the NMOS and PMOS transistors are equal in spite of different values of K p . The second one ensures that the output resistances of the charge and discharge current sources are equal in spite of different values of λ0 . The cascading transistors M3 and M5 , M4 and M6 are used to obtain the high output impedance Rso . Further, they act as switches, which are controlled by a break-before-make logic circuit. The break-beforemake logic circuit ensures that at all times the switched current source has a high output impedance.

4.3.

Fig. 7. Some periods of some voltages in the oscillator.

4.4.

The circuits shown in Figures (5) and (6) have been simulated using PSPICE with level 2 models. Table 1 shows some parameters and simulated results for the OTA and the switched current source for a 5V power supply. A complete oscillator has also been simulated. The comparator was modeled with a constant delay time of 0.4 µs. The oscillation frequency is about 100 kHz. Figure 7 shows the periods of some voltages in the oscillator, under the conditions, C p2 = 60 pF, Coff = 1.3 pF, Cint = 40 pF and VCC = 5 V.

Comparator 5.

A frequency-variable delay time of the comparator will cause nonlinearity in the transfer of the capacitancecontrolled oscillator (see formula (7)). In our design, a standard cell for the comparator with a specified delay time of about 0.4 µs is used.

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Simulated Results

The Selector

In the multiple-capacitance measurement based on the above-mentioned measurement principle, a selector is required to select the capacitance to be measured. According to the two-port measurement method, the out-

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Fig. 8. Logic diagram of the selector.

puts of the selector should have a low impedance. Figure 8 shows a diagram of the selector which is based on a shift register. It has nine signal outputs, one control output (shift out), a signal input, a shift input, a control input and a clear input. The shift input and control input are used to set up the output state. The selector outputs have a resistance of about 65 Ä, the maximum output current amounts to about 8 mA. The capacitive load capability is about 10 nF. 6.

Table 2. Some important experimental results and parameters.

Parameters

Values

Supply voltage Power consumption Oscillator frequency Frequency divider number Non-linearity over 2pF range Resolution Allowed parasitic capacitance at input Allowed parasitic capacitance at output

5V ± 10% 12 mW 90 kHz 32 330 ppm 11.3 ppm See Fig. 11 10 nF

Implementation and Experimental Results

A prototype of the proposed interface has been fabricated in 0.7 -µm CMOS technology. The capacitancecontrolled oscillator and the selector are implemented on two separate chips. This was found to be necessary to avoid cross-talk effects by the parasitic capacitances, for instance, between the pins and the sensor electrodes. The internal capacitors values amount to Coff = 1.3 pF, Cint = 60 pF and C p2 = 40 pF, respectively. The interface is used to measure multiple capacitances in the range 0 − 2 pF. Figure 9 shows a photomicrograph of the oscillator chip and Table 2 shows some important experimental results and parameters. The measurement resolution has also been determined as a function of the measurement time. In many applications of capacitance measurement, the threesignal approach [7] is used to eliminate the unknown offset and unknown gain error of the signal processor [2–5,7]. Therefore, in the measurement of the resolution, three phases, TC x1 , TC x2 and Toff (C x = 0) which respectively correspond to C x1 of 1 pF, C x2 of 1 pF and C x of 0 pF, have been measured for the different measurement times. The ratio of two capacitance is calculated from C x1 /C x2 = (TC x1 − Toff )/(TC x2 − Toff ). The standard deviation (resolution) of the result is depicted

in Figure 10. The parasitic capacitance C p2 amounts to 20 pF. For short measurement times, the quantization noise, which originates from the sampling by the microcontroller, is dominant. For these short times, the resolution is inversely proportional to the measurement time. The effect of the parasitic capacitance C p2 (Figure 2(a) and Figure 3) on the nonlinearity has also been measured (see Figure 11). In Figure 11, it is shown that for large parasitic capacitances (larger than 3 nF), the measured nonlinearity is in agreement with the result calculated from formula (3) (see Figure 4).

7.

An Application

The proposed and implemented interface has been used in a capacitive encoder with multiple electrodes. Figure 12 shows a capacitive angular sensing element, which consists of three parallel discs [4]. For this kind of capacitive sensor, nine capacitances have to be measured in order to obtain an absolute angular position

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Fig. 9. A photomicrograph of the oscillator chip.

Fig. 10. Standard deviation of the measurement C x1 /C x2 versus the total measurement time.

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Fig. 11. The effect of the parasitic capacitance C p2 on the nonlinearity.

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Conclusions

A low-cost CMOS interface for the capacitive sensor, based on a Martin relaxation oscillator, has been presented. Because of the application of the two-port measurement and the optimization of the input stage, parasitic capacitances of up to about 3 nF are allowed for the measurement of small capacitances. When using two separated chips, the interface is able to measure several multiplexed capacitances accurately, while avoiding cross-talk effects. The interface chips have been implemented in 0.7-µm CMOS technology. The measured resolution and nonlinearity over a measurement range of 2 pF are 11.3 ppm and 300 ppm, respectively. The designed interface has been found to be very useful to implement an accurate measurement system. As an example, an accurate capacitive angular encoder has also been discussed.

Acknowledgements The authors thank Paul C. de Jong and Guijie Wang, of the Dept. of Electrical Engineering, Delft University of Technology, for their discussions and help. We also thank MIETEC for supplying prototypes of the chips.

Fig. 12. The sensing element of the capacitive encoder.

over the full measurement range of 360◦ [4]. The capacitor values are in the range of 0–0.5 pF. The double-side PCBs are used to implement the common and segmented electrodes and to carry the interface chips. The oscillator chip is mounted at the common electrode PCB and the selector chip at the segmented electrode. The two chips are connected by a shielded wire which is assembled in the housing of the encoder. This specific way of assembling is used to minimize undesired cross-talk effects. A microcontroller with a counting clock of 3 MHz is employed to perform the measurement of the periods of the output signal from the interface, data processing, logic control for the selector, and the communication with the outside digital world. The resolution of the capacitive encoder limited by noise amounts to 11 arcsec (17 bits) in a measurement time of 300 ms. The measured systematic nonlinearity is less than ±58 arcsec (14 bits) over the measurement range of 360◦ .

References 1. S. M. Huang, M. S. Beck, R. G. Green, A. L. Stott, “Electronic transducers for industrial measurement of low value capacitances,” J. Phys. E: Sci. Instrum. 21, pp. 242–250, 1988. 2. F. N. Toth, H. M. M. Kerkvliet, G. C. M. Meijer, “Ultra-linear, low-cost measurement system for multi-electrode pF-range capacitor,” in Proceedings of the IEEE, IMTC/95, Boston, USA, Apr. 1995, pp. 512–515. 3. F. N. Toth and G. C. M. Meijer, “A low-cost, smart capacitive position sensor,” IEEE Trans. Instrum. Meas. 41(6), pp. 1041– 1044, Dec. 1992. 4. X. J. Li, G. W. de Jong, G. C. M. Meijer, “An accurate low-cost capacitive absolute angular-position sensor with a full-circle range,” IEEE Trans. Instrum. Meas. 45(2), pp. 516–520, April 1996. 5. F. M. L. van der Goes and G. C. M. Meijer, “A novel lowcost capacitive-sensor interface,”IEEE Trans. Instrum. Meas. 45(2), pp. 536–540, April 1996. 6. J. van Drecht, “Relaxatie oscillator,” Pat. Appl. 91.01076, The Netherlands, 1991. 7. G. C. M. Meijer, J. van Drecht, P. C. de Jong and H. Neuteboom, “New concepts for smart signal processors and their application to PSD displacement transducers,” Sensors and Actuator A35, pp. 23–30, 1992. 8. G. W. de Jong, “Data sheet CapCo selector chip set for interfacing capacitive sensors,” Technical Report, Delft University of Technology, March 1995.

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Xiujun Li was born in Tianjin, China on Feb. 19, 1963. He received the B.S. degree in physics and the M.S. degree in electrical engineering from Nankai University, Tainjin, China in 1983 and 1986, respectively. He joined the Department of Electronic Science, Nankai University in 1986. He is now working toward the Ph.D. degree at Dept. of Electrical Engineering, Delft University of Technology, The Netherlands. His research intersts are in the area of te smart capacitive sensor and signal processing.

Photo not available at time of print

ing from the Delft University of Technology, Delft, The Netherlands, in 1972 and 1982, respectively. Since 1972 he has been part of the Laboratory of Electronics, Delft University of Technology, where he is an associate professor, engaged in research and teaching on analog ICs. In 1984 and part-time in during 1985–1987, he was seconded to the Delft Instruments Company in Delft, where he was involved in the development of industrial level gauges and temperature transducers. In 1996 he was one of the founders of the company Sensart, where he is a consultant in the field of sensor systems. Dr. Meijer is a member of the Netherlands Society for Radio and Electronics and of the IEEE.

Gerben W. de Jong was born in The Hague, The Netherlands, on December 25, 1965. He received his ingenieurs (M.S.) and Ph.D. degrees in electrical engineering from the Delft University of Technology, Delft, The Netherlands, in 1989 and 1994, respectively. His Ph.D. work was on smart capacitive sensors. After his Ph.D. work, he has developed ICs for smart capactivie sensors at the DUT, Dept. of Electrical Engineering. From Oct. 1995 he works at the Philips Research Laboratory in Eindhoven, The Netherlands.

Ferry N. Toth was born in Sydney, Australia, on August 4, 1966. He received the ingenieurs (M.S.) and Ph.D. degrees in electrical engineering from the Delft University of Technology, Delft, The Netherlands, in 1990 and 1997, respectively. From 1990 to 1991, he was employed by Delft Instruments Tang Gauging BV, formerly known as Enraf Nonius, where he was engaged in the development of a capacitive level gauge. After this he was employed by the Delft University of Technology, where he was involved in scientific research on intelligent capacitive sensors. He is currently employed by ENRAF BV, which is part of the Delft Instruments Group, Delft, and is involved in the development of a new generation of intelligent capacitive level gauges.

Gerard C. M. Meijer was born in Wateringen, The Netherlands, on June 28, 1945. He received the ingenieurs (M.S.) and Ph.D. degrees in electrical engineer-

Frank M. L. van der Goes was born in Delft, The Netherlands, on February 21, 1966. He received the

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Low-Cost CMOS Interface ingenieurs (M.Sc.) and the Ph.D. degree in electrical engineering from the Delft University of Technology in 1990 and 1996 respectively. Since 1996 he has been part of the Integrated

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Transceivers Group of Philips Research. His main interests lies in the field of A/D conversion and front-ends for digital RF receivers.

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