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Scan BIST with biased scan test signals XIANG Dong1† , CHEN MingJing2 & SUN JiaGuang1 1
School of Software, Tsinghua University, Beijing 100084, China;
2
Deptartment of Computer Science and Engineering, University of California, San Diego, La Jolla, CA 92093, USA
The conventional test-per-scan built-in self-test (BIST) scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flipflops are shifted out while shifting in the next test vector like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the test signals of the scan chains. Different biased random values are assigned to the test signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly, and most circuits can obtain complete fault coverage or very close to complete fault coverage. random testability, scan-based BIST, test signal, biased random testing
1
Introduction
Scan-based BIST can be simply classified into two types: Test-per-scan and test-per-clock[1,2] test schemes. In test-per-clock BIST, a test vector is applied and its test responses are captured and compressed every clock cycle. This test scheme needs fewer test vectors to reach the same fault coverage as that for the test-per-scan test scheme. However, it requires insertion of an XOR gate into each scan flip-flop, which is placed into the functional paths. The area overhead and timing overhead introduced by such a test scheme are unacceptable in most cases. The BILBO[3] is an example of the test-per-clock BIST scheme. In test-per-scan BIST scheme, a test vector is first shifted into the scan chains, and then a functional cycle is adopted to capture test responses. The test responses captured in the scan flip-flops are shifted out when the next test vector is scanned in. Test application time based on the test-perReceived May 30, 2006; accepted June 6, 2006 doi: 10.1007/s11432-008-0078-1 † Corresponding author (email:
[email protected]) Supported in part by the National Natural Science Foundation of China (Grant Nos. 60373009 and 60425203)
Sci China Ser F-Inf Sci | Jul. 2008 | vol. 51 | no. 7 | 881-895
scan scheme is more than that of the test-per-clock scheme. Test responses at the data inputs of scan flip-flops are unobservable during the shift cycles in the test-per-scan BIST scheme. Test length of scan-based BIST is usually determined by the hard-to-detect faults. Test length reduction of the hard-to-detect faults is an important issue. Various techniques are adopted to handle the problem. The most popular techniques include biased random testing[2,4−7] and test point insertion[8,9]. Other methods include designing a more effective test generator[8,10−12] and reseeding techniques. Deterministic BIST methods obtain complete fault coverage. Weighted random testing refers to applying test patterns that have different signal probabilities instead of 0.5 to primary inputs in order to reduce test length or test application time to reach the given fault coverage. Bardell, McAnney, and Savir[2] proposed a very simple procedure to propagate the weight at each gate backward to the primary inputs. The procedure to generate a weight set for primary inputs in ref. [2] was further modified for LSSD designed circuits in ref. [6]. Most recently, new techniques were proposed by Jas, Krishna and Touba[4] to compress and store weight sets, which can reduce tester storage requirements and tester bandwidth requirements by orders of magnitude. However, most biased random testing methods need to store multiple weight sets on-chip, and multiple session testing is usually necessary, which can make the control logic very complex. Tsai, Cheng and Bhawmik[12] proposed a novel BIST scheme that inserts multiple capture cycles after the scan shift cycles during a test cycle. Thus, fault coverage of the scan-based BIST can be greatly improved. An improved method of the above paper was presented recently in ref. [11]. The method in ref. [11] selected different number of capture cycles after the shift cycles during one test cycle, which can increase the proportion of at-speed test and enhance test quality of scan-based BIST. A scan chain partitioning scheme was presented most recently in ref. [8] to improve effectiveness of scan BIST based on structural analysis. Experimental results showed that the proposed method works better than the test-per-scan BIST combined with an effective phase shifter[13] . In this paper, a biased random testing scheme is proposed that avoids using a more complicated test generator or modifying the scan flip-flops. Unlike the conventional test-per-scan scheme, our method can insert capture cycles at any time if necessary. The proposed method does not need to use a more complicated test generator or modify the scan flip-flops. Our method only needs to assign different weights on the scan test signals of the scan chains. In the rest of this paper, preliminaries and motivations of the paper are presented in section 2. Testability issues of the test-per-scan BIST scheme are studied in section 3. Testability features of the proposed BIST scheme based on biased scan test signals is introduced in section 4. Testability estimation for the proposed test scheme is presented in section 5. Selection of weights for the new scan-based BIST scheme is introduced in section 6. Experimental results are given in section 7. Section 8 concludes the paper finally.
2 Preliminaries A scan cycle is the period in which a test pattern is shifted into (or test responses are shifted out of) the scan chains. The length of a scan cycle (the number of clock cycles) is equal to the number of scan flip-flops in the longest scan chain. A capture cycle is the period between two adjacent scan cycles. The circuit is set to the functional mode during the period when the test pattern is applied 882
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to the circuit and the test responses are captured in the scan flip-flops. A test cycle consists of a scan cycle followed by a capture cycle. The i-controllability Ci (l)(i ∈ {0, 1}) measure of a node l is defined as the probability for a randomly selected input vector to set l to value i. The observability O(l) is defined as the probability for a randomly selected input vector to propagate the value of l to a primary output or the scan-out signal of a scan chain. The signal probability of a node is the same as its 1controllability measure. The detection probability pdf (l/i) is defined as the probability to detect a fault l/i (l stuck-at i) by a randomly selected input vector. The conventional STUMPS scan architecture[2] may be unable to obtain good enough fault coverage. Almost all of the previous biased random testing methods only apply biased vectors to the primary inputs. There is no effective method to generate biased vectors at the pseudo-primary inputs without modifying the scan flip-flops. Usually, the scan test signals of all scan flip-flops are controlled to the test mode during the scan shift cycles, and the functional mode during the capture cycles. As shown in Figure 1, all scan chains SC1 , SC2 , . . . , SCk share the same test signal test. In test mode, test is set to 1, and it is set to 0 when the circuit is set to the functional mode. The test1 is a random signal. The test signal of the scan chains is activated if both test and test1 are set to value 1. Usually, the number of stages of the pseudo-random test pattern generator (PRTG) is fixed, and a well designed phase shifter[13] can avoid interdependences among the outputs of the PRTG.
Figure 1
Assign the scan test signals of the scan flip-flops with random signals of weight 0.5.
Tsai, Cheng, and Bhawmik[12] pointed out that scanning a flip-flop in scan-based BIST may make observability of its data input worse. The values of the primary outputs can be observed every clock cycle, but test responses propagated to the data inputs of scan flip-flops are observed only once during the whole test cycle. Test responses propagated to data inputs of the scan flip-flops are unobservable during the scan shift cycles for the test-per-scan BIST scheme. It is quite clear that more capture cycles can make scan flip-flops more observable. Once the test responses are captured at the scan flip-flops, they are propagated to the primary outputs or other scan flip-flops in the same scan chain. Methods in refs. [11,12] inserted multiple capture cycle after all shift cycles XIANG Dong et al. Sci China Ser F-Inf Sci | Jul. 2008 | vol. 51 | no. 7 | 881-895
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unlike the conventional test-per-scan BIST scheme. It is reasonable to detect the random resistant faults if more capture cycles are inserted. Table 1 presents results of some benchmark circuits by using a random test signal for all scan chains. Column 2 presents fault coverage of the conventional test-per-scan BIST scheme, and column 3 presents fault coverage of the scan-based BIST scheme by using a random test signal for all scan chains with a random signal. We present the results for both BIST schemes after 30000 clock cycles. The random test signal scheme presents better fault coverage for all circuits presented in Table 1. However, the randomly controlled test signal test scheme is unable to obtain very good results for all circuits. A greedy procedure will be presented to select weights for the scan test signals of the scan chains. Table 1 Scan-based BIST with randomly controlled scan enable signal Circuits
FC(%)(test-per-scan)
FC(%)(random test signal)
#Clock cycles
s3271
99.6212
99.8580
30000
s3330
89.0440
94.1192
30000
s4863
96.8505
99.4306
30000
s35932
91.8008
92.0026
30000
s38417
91.7303
93.3828
30000
3 Testability of the test-per-scan BIST scheme Most of the previous test-per-scan schemes used the BIST architecture as shown in Figure 1 by sharing the same test signal test. The outputs of the linear feedback shift register (LFSR) are connected to the phase shifter (PS). The primary inputs and the extra pins of the control test points, if necessary, are connected to the outputs of the PS. Scan-in signals of the scan chains are also driven by the phase shifter. The scan-out signals of the scan chains are connected to the multiple input signature register (MISR). Observation test points, if necessary, are also connected to the MISR. The MISR can be compressed, the details of which are introduced in section 7 and ref. [15]. A new testability estimation technique for the test-per-scan BIST test scheme is presented first. Figure 2 presents a test cycle for a scan chain of the test-per-sca BIST scheme, which consists of a capture cycle of the previous test cycle and k shift cycles of the current test cycle, where k is the length of the longest scan chain. As shown in Figure 2, test responses at the pseudo-primary outputs are captured in the corresponding scan flip-flops at the capture cycle of the previous test cycle, which is followed by k shift cycles. The random signals are shifted in from the scan-in signal, while the captured test responses of the scan flip-flops are shifted out from the scan-out signal sequentially. Consider the ith scan flip-flop receives the test response captured at the (i−1)th scan flip-flop for the 1st shift cycle. It receives the test response captured by the (i − 2)th scan flip-flip at the 2nd shift cycle. Finally, the ith scan flip-flop receives the test response captured by scan flip-flop 1 at the (i − 1)th shift cycle. The ith scan flip-flop begins to receive random signals shifted from the scan-in from the ith clock cycle to the k th clock cycle. As for the scan flip-flop k, it does not receive random signal until the kth shift cycle. The scan flip-flops without arrows in Figure 2 receive random signals and apply to the circuit. All primary outputs receive test responses at all clock cycles while the pseudo-primary inputs receive test responses only at the capture cycles. Signal probabilities of the pseudo-primary inputs cannot be thought as 0.5 during the shift cycles. We want to estimate controllability of the pseudo884
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primary inputs (PPIs) and observability of the pseudo-primary outputs (PPOs). The location of a scan flip-flop in a scan chain does have impact on its testability. We consider the ith scan flipflop in a scan chain. As for the (k + 1)th clock cycle (capture cycle) of test cycle t (t 1), its controllability is the controllability of its data input in the k th clock cycle. Testability for all internal nodes can be estimated based on the COP measure[14].
Figure 2 A test cycle of the test-per-scan BIST scheme.
Let the length of the scan chains be k . As shown in Figure 3, each test cycle is partitioned into four different phases. A test cycle for the conventional test-per-scan test scheme contains k shift cycles and the capture cycle. The shift cycles of each test cycle are further partitioned into three parts for the ith scan flip-flop: 1) the first (i − 1) shift cycles; 2) the shift cycles after the (i − 1)th clock cycle except the kth shift cycle; and 3) the kth clock cycle. As shown in Figure 3, the (k + 1)th clock cycle is the capture cycle.
Figure 3
Testability estimation of the tth test cycle for the test-per-scan BIST scheme.
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Let us consider the controllability of the the pseudo-primary inputs of the ith (i > 1) scan flipflop during test cycle t (t > 1). Its signal probability of the j th clock cycle (1 j i − 1) is the signal probability of the (i − j)th scan flip-flop at the capture cycle of test cycle (t − 1). Signal probability of the ith scan flip-flop after the (i − 1)th shift cycle is 0.5 because it receives random signals during the remaining shift cycles. Therefore, it is not good to consider controllability of the pseudo-primary inputs as 0.5 for all shift cycles. Observability of the pseudo-primary outputs (PPOs, inputs of the scan flip-flops) is 0.0 during the first (k − 1) shift cycles as shown in Figure 3. It is noted that observability of the input of a scan flip-flop at the k th clock cycle is the same as the observability of its output at the (k + 1)th clock cycle because the value of the input of the flip-flop is propagated to its output at the (k + 1)th clock cycle, which is used as a test at the capture cycle. As for the last phase, that is, the (k + 1)th clock cycle, controllability of the output of the scan flip-flop is the same as its input’s controllability at the k th clock cycle. Furthermore, observability of the input of a scan flip-flop is 1.0, whose value will be captured and shifted out through the scan chain during the shift cycles of the next test cycle. Observability of the primary outputs is 1.0 for all clock cycles. Testability of the circuit during the capture cycles is estimated for the original circuits. However, testability estimation of the circuit based on the COP measure can converge quickly because the testability of the pseudo-primary inputs of the scan flip-flops have the constraints as shown in Figure 3. Observability of the pseudoprimary inputs can be improved if more capture cycles are inserted in the process of scan shift, but not after all scan shift cycles. Weighted test vectors can also be applied to the pseudo-primary inputs in this case. Testability estimation using this test scheme should be similar to the one as stated above. Note that all scan chains are set to the same mode at any time because they share the same scan test signal. It is impractical to estimate testability of all nodes by clock cycles. A simple and more accurate scheme can be stated as follows. Initially, controllability of the pseudo-primary input (PPI) of the ith scan flip-flop is set to 0.5 · (k − i + 1)/(k + 1), and observability of the pseudo-primary output (PPO) of the ith scan flip-flop is set to 1/k . The COP measure is adopted to estimate testability measures of all nodes iteratively. Controllability and observability measures of the PPI and PPO of the ith scan flip-flop can be estimated as the average measures of them during the k + 1 clock cycles in a test cycle. The 1-controllability measure C1 (PPIi ) of the ith scan flip-flop is calculated as follows based on Figure 2: i 0 j=1 C1 (PPOj ) + 0.5 · (k − i + 1) , C1 (PPIi ) = (1) k+1
1 + O0 (PPIi ) , (2) k+1 where C10 (l) and O 0 (l) the 1-controllability measure and observability measure of node l in the previous round of testability calculation, and k is the length of the scan chains. It is found that testability measures become stable very quickly using the above scheme, and the initial values do not have great impact on the final results. O(PPOi ) =
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4 Testability features of the proposed test scheme The proposed test scheme uses different scan test signals to control different scan chains as shown in Figure 4 when the circuit is set to the test mode, where weights w1 , w2 , . . . , wk ∈ {0.5, 0.625, 0.75, 0.875}. Different values are assigned to different scan test signals of separate scan chains at the same clock cycle. Therefore, testability is studied corresponding to different scan chains. Testing with respect to each scan chain can still be partitioned into test cycles, where neither the number of shift cycles nor the number of capture cycles contained in each test cycle is fixed. Let k be the length of the scan chains, and k and k be the number of shift cycles contained in the t and t + 1 test cycles as presented in Figure 5. It should be noted that k and k can be greater than or less than k . Testability of the scan flip-flops is also closely related to the next test cycle.
Figure 4 The new scan-based BIST architecture with biased scan test signals.
As shown in Figure 5, two consecutive test cycles are presented. The first test cycle contains k shift cycles and l capture cycles. And the second test cycle contains k shift cycles and l capture cycles. Testability estimation during a test cycle is partitioned into 5 phases for the ith scan flip-flop if i < k . Otherwise, testability estimation of the ith scan flip-flop contains only the 1st, 4th, and 5th phases as presented in Figure 5 if i > k . Testability estimation of the ith scan flip-flop for the first two phases is the same as that in Figure 3. As for the k th clock cycle, testability estimation of the ith scan flip-flop is still the same as that in Figure 3. As for testability of the scan flip-flops during clock cycles k to (k + l − 1), the signal probability of the pseudo-primary input is the signal probability of its data input in the last clock cycle, and the observability of the pseudo-primary output is the observability of its output for the next clock cycle. As for the last clock cycle, the signal probability of the pseudo-primary input is the same as the previous capture cycles, however, the observability of the pseudo-primary output is determined by its location and the number of shift cycles contained in the next test cycle. Consider the test schemes XIANG Dong et al. Sci China Ser F-Inf Sci | Jul. 2008 | vol. 51 | no. 7 | 881-895
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in refs. [11,12], observability of the pseudo-primary output must be 1.0 because the number of shift cycles in the next test cycle is equal to the length of the scan chain, i.e., test response captured at the scan flip-flop can always be propagated to the scan-out signal of the scan chain. In our test scheme, observability of the pseudo-primary output is 1.0 if the number of shift cycles in the next test cycle is greater than or equal to k − i, where i is the location of the scan flip-flop in the scan chain, and k is the length of the scan chain. If the number of shift cycles in the next test cycle is less than k − i, observability of the pseudo-primary output of the scan flip-flop is
O(PPOi ) = 1 − (1 − O(PPIi+1 )) · (1 − O(PPIi+2 )) · · · · · (1 − O(PPIi+k )).
Figure 5 Testability of the tth test cycle for the two consecutive test cycles.
That is, the test response captured at the scan flip-flop is propagated to any one of the pseudoprimary inputs PPIi+1 , PPIi+2 , . . . , PPIi+k in this case. Up to now, we can say that the proposed test scheme is actually a generalized test scheme of the ones in refs. [11,12] with multiple capture cycles. According to our method, neither the number of shift cycles nor the number of capture cycles is fixed.
5 Testability estimation for the proposed test scheme Testability is calculated using the scheme as shown in Figure 4 for the scan chains with biased scan test signals. Testability estimation for a scan chain with a biased scan test signal is presented in this section. Controllability estimation based on the test scheme is introduced in subsection 5.1, and observability estimation is presented in subsection 5.2. 5.1 Controllability estimation As shown in Figure 6, a weight p is assigned to the scan test signal of the scan chain. The signals PPIi and PPOi are the pseudo-primary inputs and pseudo-primary outputs of the ith scan flip-flop 888
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for i = 1, 2, . . . , k. Signal probability of the signal PPI1 can be calculated as follows: 1 C1 (PPI1 ) = · p + C1 (PPO1 ) · (1 − p), (3) 2 where p is the weight of the scan test signal. In eq. (3), the first term on the right-hand side indicates the probability for the signal P P I1 to get value 1 by the pseudo-random input Sin when the scan chain is set to the test mode, and the second term represents the probability to assign value 1 to the signal PPI1 by its data input PPO1 when the scan chain is controlled to the functional mode. The signal probability of PPI2 can be calculated as follows:
C1 (PPI2 ) = p · C1 (a1 ) + C1 (PPO2 ) · (1 − p),
(4)
where C1 (a1 ) = C1 (PPI1 ). The first term on the right-hand side of eq. (4) represents the probability for the pseudo-primary input PPI2 to be set to value 1 when the scan chain is set as the test mode, and the second term stands for the probability for the signal PPI2 to be assigned value 1 by its data input when the scan chain is controlled to the functional mode. Similarly, we can obtain testability measure of signal PPIk as follows:
C1 (PPIk ) = p · C1 (ak−1 ) + (1 − p) · C1 (PPOk ),
(5)
where C1 (ak−1 ) = C1 (PPIk−1 ). Signal probability calculation for other combinational nodes is the same as the conventional test-per-scan BIST using the COP[14] measure.
Figure 6 A scan chain with a biased scan test signal.
5.2 Observability estimation Observability measures of all nodes corresponding to the scan chain with the biased scan test signals can be obtained as follows. First, let us consider the last scan flip-flop as shown in Figure 6.
O(ak−1 ) = 1 − (1 − O(PPIk−1 )) · (1 − O(bk−1 )),
(6)
O(bk−1 ) = p · O(ak ) = p,
(7)
O(PPOk ) = O(ak ) · (1 − p) = 1 − p.
(8)
In eq. (6), we think the fault effect on ak−1 can be observed if it can be observed from either PPIk−1 or bk−1 . The fault effect on bk−1 can be observed if the node ak is observable and the scan chain is set as test mode. The fault effect on the pseudo-primary output of the k th scan flipflop is observable if the node ak is observable and the scan chain is set to the functional mode. Observability corresponding to the second scan flip-flop can be calculated as follows:
O(a2 ) = 1 − (1 − O(PPI2 )) · (1 − O(b2 )), O(b2 ) = p · O(a3 ), XIANG Dong et al. Sci China Ser F-Inf Sci | Jul. 2008 | vol. 51 | no. 7 | 881-895
(9) (10) 889
O(PPO2 ) = O(a2 ) · (1 − p).
(11)
Similarly, observability of signals corresponding to the first scan flip-flop can be calculated as follows:
O(a1 ) = 1 − (1 − O(PPI1 )) · (1 − O(b1 )), O(Sin ) = p · O(a1 ), O(PPO1 ) = O(a1 ) · (1 − p).
(12) (13) (14)
Eqs. (3)–(14) can be utilized to evaluate the cost function to be presented later in section 6, which is used to select weights for all scan chains by minimizing the cost function. Assume the BIST process is partitioned into multiple test sessions, the weights assigned to the scan test signals of the scan chains can be updated after each session. This technique can further improve the test effectiveness of the scan-based scheme.
6 Selecting weights for the scan test signals of the new scan-based BIST architecture The architecture of the proposed test scheme is presented in Figure 4 when the circuit is set to test mode. All biased signals are assigned to the scan test signals during test. In the scan-based architecture as shown in Figure 4, different weights w1 , w2 , . . . , and wk are assigned to the scan test signals of the scan chains SC1 , SC2 , . . . , and SCk , respectively, where w1 , w2 , . . . , wk ∈ {0.5, 0.625, 0.75, 0.875}. The reason why we do not assign any weight less than 0.5 to the scan test signals is that we do not want to insert more capture cycles than scan shift cycles. An effective method is presented to select weights for the scan test signals of the scan chains. Selection of the weights on the scan test signals of the scan chains is determined by the following testability cost function, |C1 (l) − C0 (l)| . (15) G= O(l) l/i∈F
where l/i represents the stuck-at i (i ∈ {0, 1}) fault at line l. In eq. (15), F is the random resistant fault set that contains the faults whose detection probability is no more than 10 times of that of the hardest fault[2] . Note that eq. (15) does not consider redundant faults according to a deterministic test generator. Our method tries to minimize the cost function as given in eq. (15). Our method does not need to insert complex hardware into the original circuit in order to generate different weights for the scan test signals of the scan chains. The biased signals assigned to the scan test signals of the scan chains can be generated easily as in ref. [2]. The biased signals of weights 0.625, 0.75, and 0.875 can be generated as follows. The signal of weight 0.625 can be produced by connecting two pseudo-random signals with a 2-input AND gate, whose output is connected with a 2-input OR gate. Another input of the OR gate is a pseudo-random signal. The biased signal of weight 0.75 can be obtained from the output of a 2-input OR gate, whose inputs are pseudorandom signals. The signal of weight 0.875 can be obtained from the output of the 3-input OR gate, whose inputs are pseudo-random signals. The weights for the scan test signals of the scan chains are determined once and for all. That is, the weights do not need to be updated in the process of testing. The extra logic to generate the weights for the test scheme consists of only the 4 gates, which introduces trivial area overhead compared to the previous biased test pattern generators. The 890
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circuit turns to operational mode when test is set to 0, and all weights are assigned to the scan chains when test is set to 1. The circuit turns to test mode when test is set to 1. Let all scan chains be assigned separate scan test signals. We consider assigning one of the following weights {0.5, 0.625, 0.75, 0.875} to scan test signals of the scan chains. In the weight selection procedure, S is the scan chain set and SC is a specific scan chain. Initially, S contains all scan chains in the circuit, and scan test signals of all scan chains are assigned that of the regular test-per-scan test scheme. Initially, controllability of the pseudo-primary input (PPI) of the ith scan flip-flop is set to 0.5 · (k − i + 1)/(k + 1), and observability of the pseudo-primary output (PPO) of the ith scan flip-flop is set to 1/k as presented in section 3. Iterative testability estimation is used for all nodes based on eqs. (3)–(14) and the COP measure[14]. It is found that testability measures for all nodes become stable very quickly. The procedure to determine weights can be illustrated as follows: First, all scan chains use the common test-per-scan scan test signals. That is, scan test signals are set to 1 in scan shift cycles and set to 0 in capture cycles. A test cycle for the original scan test signals contains k scan shift cycles followed by one capture cycle, where k is the length of the longest scan chain. Our method selects a weight for the first scan chain scan test signal to minimize the cost function. After the best weight has been selected for the first scan chain, our method selects the best weight for the scan test signal of the second scan chain that minimizes the cost function as presented in eq. (15). For each scan chain, if no weight can be selected, just leave its scan test signal as the one in conventional test-per-scan BIST scheme. Continue the above process until proper weights have been chosen for all scan test signals of the scan chains. The detailed procedure to determine weights for the scan test signals is presented in Figure 7. The details to calculate the testability measure of the circuit have been introduced in sections 3, 4 and 5. Different weights can be obtained by connecting two or more pseudo-random signals as in ref. [2]. select-weight-for-scan-enables() { 1. Assign the same values to the scan-enable signals as the regular test-per-scan BIST scheme to all scan chains. 2. While the scan chain set S = ∅, do (a) Select a scan chain SC from the scan chain set S, S = S − {SC}. (b) Assign each weight in {0.5, 0.625, 0.75, 0.875} to the scan enable signal of scan chain SC, testability estimation is adopted to evaluate the cost function as presented in eq. (15). (c) Select the best weight w ∈ {0.5, 0.625, 0.75, 0.875} for the scan chain SC that makes the cost function as presented in eq. (15) minimum. 3. For each scan chain, if no weight can be selected, simply leave its scan-enable signal as the one in the conventional test-per-scan test scheme. } Figure 7
7
Procedure to select different weights for the scan-enable signals of the scan chains.
Experimental results
The proposed biased-test-signal-based (BTS) method has been implemented with a Sun Blade 2000 workstation. In all our experiments, the length of all scan chains is set to 10 in order to be compatible with that in refs. [11,12], and it consistently obtains better fault coverage in almost all cases for designs with other scan chain length. Multiple scan chains or primary outputs can be connected XIANG Dong et al. Sci China Ser F-Inf Sci | Jul. 2008 | vol. 51 | no. 7 | 881-895
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with XOR gates, whose outputs are connected to the MISR in order to reduce the size of the MISR. A pseudo-random test pattern generator (PRTG) of 24 stages is adopted to generate test patterns for all circuits. The phase shifter is generated exactly according to that in ref. [13]. All experimental results in this paper are collected after 500 k clock cycles. All extra faults of the DFT logic are excluded and all methods use the same PS and PRTG in order to present fair comparison. The PROOFS sequential fault simulator is used for all fault simulation work in this paper. Our method needs sequential fault simulation in many cases. This can increase the CPU time to do fault simulation. However, test stimuli are assigned to the primary inputs and pseudo-primary inputs for any clock cycle instead of only primary inputs like fault simulation for synchronous sequential circuits. Therefore, the CPU time to do fault simulation for the proposed test scheme is still close to the conventional test-per-scan scheme (STS), and other two multiple capture cycle test schemes. The two multiple capture test schemes[11,12] also need to do sequential fault simulation. As shown in Table 2, the original area of the circuit (area (orig.)), area of the phase shifter (area (PS)), area of the weight generator (area (connect)), area overhead (AO) are presented. Area overhead in Table 2 represents extra area added by our method, which includes area overhead of logic to generate weights for the scan test signals and area of the test points. Fault coverage of the circuit without test point, the number of test points (ntp), and fault coverage after the given number of test points have been inserted (FC(test point)) are given after 500k clock cycles. The area overhead in Table 2 includes extra area overhead of the weight generator and the control test Table 2 Performance evaluation of the proposed method Circiuts
Area (orig.)
Area(PS)
Area(connect)
CPU (s)
No test point FC(%)
s1269
1417
168
17
0.10
s1423
1904
192
17
0.28
s1512
1834
272
17
s3271
3859
292
s3330
4136
s3384 s4863 s5378
With test points
AO(%)
ntp
FC(%)
99.8743
0
99.87
1.20
99.2504
5
99.26
1.42
0.22
96.9168
5
98.33
1.47
17
1.35
99.9527
0
99.95
0.44
412
17
1.16
97.5845
5
99.57
0.65
4619
472
17
1.62
97.6473
5
98.25
0.58
5132
456
17
1.41
100
0
100
0.33
6002
404
17
2.23
99.2971
6
99.32
0.48
s6669
7819
820
17
5.16
100
0
100
0.22
s9234
10207
320
17
12.43
91.8811
20
93.65
0.56
s9234.1
10081
440
17
12.39
90.7887
20
94.41
0.57
s13207
18007
752
17
60.07
98.0482
0
98.05
0.09
s13207.1
17687
972
17
48.64
98.5787
20
98.75
0.32
s15850
19643
564
17
43.16
95.0055
15
97.32
0.24
s15810.1
19011
1012
17
56.86
95.4166
15
97.51
0.25
s35932
455449
1604
17
332.5
92.0026
5
99.98
0.06
s38417
48824
1480
17
573.0
98.2357
15
99.26
0.10
s38584
47584
1216
17
472.2
96.3260
13
97.34
0.09
s38584.1
47324
1396
17
329.5
96.4462
15
97.63
0.10
b14
21323
432
17
25.3
92.1238
15
94.65
0.22
b15
21639
620
17
65.3
89.1306
15
96.77
0.22
b20
43003
628
17
161.1
95.4125
20
96.60
0.13
b21
43811
628
17
162.4
93.3872
20
96.44
0.13
b22
63957
788
17
347.9
94.9924
20
96.90
0.09
892
XIANG Dong et al. Sci China Ser F-Inf Sci | Jul. 2008 | vol. 51 | no. 7 | 881-895
points, where areas of the PRTG, MISR and the phase shifter are not included. The proposed method obtains very good fault coverage for most circuits without test point. Circuits s4863 and s6669 even get complete fault coverage, while circuits s1269, s1423, s3271 and s5378 obtain close to complete fault coverages. Circuits s3330, s13207, s15850, s38417, and s38584 also get up to 97.58%, 98.05%,95.01%, 98.23%, and 96.33% fault coverages, respectively. It is shown in the fourth column in Table 2 that the hardware overhead introduced by the new test generator for the biased scan test signals is almost negligible for all circuits. Extra area overhead introduced by our method is much less than that of the previous biased test generators that need to modify the scan flip-flops and store multiple weight sets on-chip. The area overhead produced by the phase shifter (PS) is presented in the third column in Table 2. Our method is compared with the MTS[12] , TTS[11] and the conventional test-per-scan test scheme STS when no test point is inserted as shown in Table 3. The MTS[11] method is implemented, and the test vector sets for different circuits are generated based on the obtained test schemes. The MTS, TTS, and STS test schemes still use the phase shifter[13] to generate tests. The TTS is implemented completely. Results of TTS are quite compatible with those presented in ref. [12], while results of MTS are much better than those given in ref. [11] for most circuits. Table 3 Comparison with previous methods FC(%) (without test points)
Circuits
With test points
BTS
MTS[12]
TTS[11]
STS
s1269
99.87
98.99
99.31
s1423
99.25
98.95
s1512
96.92
s3271
99.95
s3330
97.58
s3384
97.65
97.62
97.87
s4863
100
99.25
99.29
s5378
99.30
98.93
98.89
98.18
MTS[12]
BTS
STS
ntp
FC(%)
ntp
FC(%)
ntp
FC(%)
98.99
−
−
−
−
−
−
98.30
5
99.26
5
99.22
5
98.91
96.86
96.28
96.28
5
98.33
5
97.88
5
99.57
99.91
98.25
−
−
−
−
−
−
94.33
94.41
91.51
5
99.57
5
98.40
5
97.73
96.36
5
98.25
5
97.65
5
97.47
97.54
−
−
−
−
−
−
6
99.32
6
99.17
6
98.79
97.29
s9234
91.88
90.70
78.71
88.02
20
93.65
20
93.61
20
92.50
s13207.1
98.55
97.31
98.10
97.31
20
98.75
20
98.05
20
98.05
s15850
95.01
93.86
93.85
93.64
15
97.32
15
96.51
15
96.19
s15850.1
95.42
94.12
94.01
93.48
15
97.51
15
96.58
15
96.28
s38417
98.24
97.06
97.26
95.85
15
99.26
15
98.86
15
98.05
s38584
69.33
95.91
95.88
95.46
13
97.34
13
97.12
13
96.83
b14
92.12
91.49
91.62
89.93
15
94.65
15
94.17
15
92.69
b20
95.41
94.00
94.70
93.28
20
96.60
20
95.52
20
94.15
b21
93.39
93.01
94.26
91.83
20
96.44
20
95.64
20
94.79
b22
94.99
94.37
94.80
93.54
20
96.60
20
95.71
20
94.68
average
96.77
95.91
96.08
94.88
−
97.54
−
96.94
−
96.29
The BTS, MTS and TTS test schemes get better fault coverage for all circuits than the STS when no test point is inserted. BTS gets much better results than STS for circuits s3330, s3384, s4863, s9234, s9234.1, s13207.1, s15850, s15850.1, s38417, b14, b20, b21, and b22. It is shown that BTS outperforms MTS for all circuits. It obtains much better fault coverage than MTS for circuits s9234, s13207.1, b20, s15850, s15850.1, s38417 and s3330. Compared to the TTS test scheme, our method gets better fault coverage for all circuits except circuits s3384 and b21. The XIANG Dong et al. Sci China Ser F-Inf Sci | Jul. 2008 | vol. 51 | no. 7 | 881-895
893
new method gets a little better results for circuits s3271, s35932, and s38417 than the TTS test scheme. However, BTS gets much better results for circuits s3330, s9234, s15850, and s15850.1 than TTS. Comparison of BTS with MTS and STS is also presented in Table 3 after a number of test points have been inserted. The BTS works better than MTS and STS for all circuits with test points.
Figure 8 Test effectiveness comparison with variable scan chain lengths. (a) s9234; (b) s15850.1; (c) s38584; (d) s13207.1.
Figure 8 presents performance comparison among BTS, STS, MTS, and TTS when the length of the scan chains varies from 10 to 50. For circuits s15850.1 and s13207.1, BTS always gets better fault coverage than all other three methods for any scan chain length. There still exists some anomaly. The BTS method obtains a little worse fault coverage for circuit s38584 than MTS when scan chain length is set to 40 or 50. As for circuit s9234, BTS obtains a little worse results than TTS when the scan chain length is set to 40 or 50. Test length comparison with the conventional test-per-scan test scheme STS (combined with the phase shifter in ref. [13]) is presented in Table 4. Up to 99.7% test length reduction is obtained while the average test length reduction is about 90%.
8 Conclusions A method to generate weighted pseudo-random vectors for the pseudo-primary inputs was proposed by assigning different weights to the scan test signals of the scan chains. The proposed method does not need to design a complex weighted test generator or modify the scan flip-flops, or store multiple weight sets on-chip. Neither the number of shift cycles nor the number of capture cycles for each test cycle is fixed based on the new test generation method. The proposed method needs only one test session, which makes control logic and control scheme very simple. Experimental results showed that the method works better than two recent scan-based BIST schemes 894
XIANG Dong et al. Sci China Ser F-Inf Sci | Jul. 2008 | vol. 51 | no. 7 | 881-895
Table 4 Test length comparison with the single capture cycle test scheme Circuits
STS FC(%)
BTS cycles
FC(%)
cycles
Reduction(%)
s1269
98.99
28063
98.99
754
97.31
s1423
98.30
238515
98.30
9599
95.98
s1512
96.28
340722
96.28
80361
76.41
s3271
98.25
2249470
98.27
3749
98.50
s3330
91.51
468605
91.52
7998
98.29
s3384
96.36
422008
96.38
1145
99.73
s4863
97.54
473761
97.56
3810
99.20
s5378
98.18
398035
98.18
32478
91.84
s9234
88.02
489947
88.04
39215
92.00
s13207.1
97.31
497372
97.31
77713
84.38
s15850
93.64
451733
93.64
58902
86.96
s15850.1
93.48
412391
93.48
89263
78.35
s38417
95.85
492938
95.88
84809
83.2
s38584
95.46
476061
95.46
40375
91.52
b14
89.93
471393
89.93
18122
96.16
b20
93.28
495103
93.28
63025
87.27
b21
91.38
428009
91.83
54201
87.34
b22
93.54
481618
93.55
129216
73.17
Average
94.88
−
94.88
−
89.87
using multiple capture cycles for each test cycle and the conventional test-per-scan test scheme with a single capture cycle. 1 Abramovici M, Breuer M A, Friedman A D. Digital Systems Testing and Testable Design. New York: IEEE Press, 1995 2 Bardell P H, McAnney W H, Savir J. Built-in test for VLSI: Pseudo-Random Techniques. New York: Wiley, 1987 3 Koenemann B, Mucha J, Zwiehoff C. Built-in logic block observation technique. In: Proc. of IEEE Int. Test Conference. 1979. 37–41 4 Jas A, Krishna C V, Touba N A. Weighted pseudorandom hybrid BIST. IEEE Trans VLSI Syst, 2004, 12(12): 1277–1283 5 Pomeranz I, Reddy S M. 3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits. IEEE Trans Comp Aid Des ICAS, 1993, 24(7): 1050–1058 6 Savir J. Distributed generation of weighted random patterns. IEEE Trans Comp, 1999, 48(12): 1364–1368 7 Wang S. Low hardware overhead scan-based 3-weight random BIST. In: Proc. of IEEE Int. Test Conference. IEEE Computer Society Press, 2001. 868–877 8 Xiang D, Chen M J, Sun J G, et al, Improving test effectiveness of scan-based BIST using scan chain partitioning. IEEE Trans Comp Aid Des Integrated Circuits and Systems, 2005, 24(6): 916–927 9 Xiang D, Xu Y, Fujiwara H. Non-scan design for testability for synchronous sequential circuits based on conflict resolution. IEEE Trans Comp, 2003, 52(8): 1063–1075 10 Chakrabarty K, Murray B T. Design of built-in test generator circuits using width compression. IEEE Trans Comp Aid Des ICAS, 1998, 17(10):1044–1051 11 Huang Y, Pomeranz I, Reddy S M, et al. Improving the property of at-speed tests. In: Proc. of IEEE/ACM Int. Conf. Computer-Aided Design. 2000. 459–463 12 Tsai H C, Cheng K T, Bhawmik S. On improving test quality of scan-based BIST. IEEE Trans Comp Aid Des ICAS, 2000, 19(8): 928–938 13 Rajski J, Tamarapalli N, Tyszer J. Automated synthesis of large phase shifters for built-in self-test. In: Proc. of IEEE Int. Test Conference. IEEE Computer Society Press, 1998, 1047–1056 14 Brglez F. On testability of combinational networks. In: Proc. of IEEE Int. Symp. on Circuits and Systems. IEEE Cir. and Sys. Society Press. 1984. 221–225 15 Xiang D, Chen M, Fujiwara H. Using weighted scan enable signals to improve test effectiveness of scan-based BIST. IEEE Trans Comp, 2007, 56(12): 1619–1628
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